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[46.135.46.162]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ade1d754653sm67989966b.20.2025.06.05.23.29.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jun 2025 23:29:06 -0700 (PDT) From: Tomeu Vizoso Date: Fri, 06 Jun 2025 08:28:26 +0200 Subject: [PATCH v7 06/10] dt-bindings: npu: rockchip,rknn: Add bindings Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250606-6-10-rocket-v7-6-dc16cfe6fe4e@tomeuvizoso.net> References: <20250606-6-10-rocket-v7-0-dc16cfe6fe4e@tomeuvizoso.net> In-Reply-To: <20250606-6-10-rocket-v7-0-dc16cfe6fe4e@tomeuvizoso.net> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Oded Gabbay , Jonathan Corbet , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Sumit Semwal , =?utf-8?q?Christian_K=C3=B6nig?= , Sebastian Reichel , Nicolas Frattaroli , Kever Yang , Robin Murphy , Daniel Stone , Da Xue , Jeff Hugo Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, linux-doc@vger.kernel.org, linux-media@vger.kernel.org, linaro-mm-sig@lists.linaro.org, Tomeu Vizoso , Krzysztof Kozlowski X-Mailer: b4 0.14.2 Add the bindings for the Neural Processing Unit IP from Rockchip. v2: - Adapt to new node structure (one node per core, each with its own IOMMU) - Several misc. fixes from Sebastian Reichel v3: - Split register block in its constituent subblocks, and only require the ones that the kernel would ever use (Nicolas Frattaroli) - Group supplies (Rob Herring) - Explain the way in which the top core is special (Rob Herring) v4: - Change required node name to npu@ (Rob Herring and Krzysztof Kozlowski) - Remove unneeded items: (Krzysztof Kozlowski) - Fix use of minItems/maxItems (Krzysztof Kozlowski) - Add reg-names to list of required properties (Krzysztof Kozlowski) - Fix example (Krzysztof Kozlowski) v5: - Rename file to rockchip,rk3588-rknn-core.yaml (Krzysztof Kozlowski) - Streamline compatible property (Krzysztof Kozlowski) v6: - Remove mention to NVDLA, as the hardware is only incidentally related (Kever Yang) - Mark pclk and npu clocks as required by all clocks (Rob Herring) v7: - Remove allOf section, not needed now that all nodes require 4 clocks (Heiko St=C3=BCbner) Signed-off-by: Sebastian Reichel Signed-off-by: Tomeu Vizoso Reviewed-by: Krzysztof Kozlowski --- .../bindings/npu/rockchip,rk3588-rknn-core.yaml | 118 +++++++++++++++++= ++++ 1 file changed, 118 insertions(+) diff --git a/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-cor= e.yaml b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.ya= ml new file mode 100644 index 0000000000000000000000000000000000000000..0588c085a723a34f4fa30a9680e= a948d960b092f --- /dev/null +++ b/Documentation/devicetree/bindings/npu/rockchip,rk3588-rknn-core.yaml @@ -0,0 +1,118 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/npu/rockchip,rk3588-rknn-core.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Neural Processing Unit IP from Rockchip + +maintainers: + - Tomeu Vizoso + +description: + Rockchip IP for accelerating inference of neural networks. + + There is to be a node per each core in the NPU. In Rockchip's design the= re + will be one core that is special because it is able to redistribute work= to + the other cores by forwarding register writes and sharing data. This spe= cial + core is called the top core and should have the compatible string that + corresponds to top cores. + +properties: + $nodename: + pattern: '^npu@[a-f0-9]+$' + + compatible: + enum: + - rockchip,rk3588-rknn-core-top + - rockchip,rk3588-rknn-core + + reg: + maxItems: 3 + + reg-names: + items: + - const: pc + - const: cna + - const: core + + clocks: + maxItems: 4 + + clock-names: + items: + - const: aclk + - const: hclk + - const: npu + - const: pclk + + interrupts: + maxItems: 1 + + iommus: + maxItems: 1 + + npu-supply: true + + power-domains: + maxItems: 1 + + resets: + maxItems: 2 + + reset-names: + items: + - const: srst_a + - const: srst_h + + sram-supply: true + +required: + - compatible + - reg + - reg-names + - clocks + - clock-names + - interrupts + - iommus + - power-domains + - resets + - reset-names + - npu-supply + - sram-supply + +additionalProperties: false + +examples: + - | + #include + #include + #include + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + npu@fdab0000 { + compatible =3D "rockchip,rk3588-rknn-core-top"; + reg =3D <0x0 0xfdab0000 0x0 0x1000>, + <0x0 0xfdab1000 0x0 0x1000>, + <0x0 0xfdab3000 0x0 0x1000>; + reg-names =3D "pc", "cna", "core"; + assigned-clocks =3D <&scmi_clk SCMI_CLK_NPU>; + assigned-clock-rates =3D <200000000>; + clocks =3D <&cru ACLK_NPU0>, <&cru HCLK_NPU0>, + <&scmi_clk SCMI_CLK_NPU>, <&cru PCLK_NPU_ROOT>; + clock-names =3D "aclk", "hclk", "npu", "pclk"; + interrupts =3D ; + iommus =3D <&rknn_mmu_top>; + npu-supply =3D <&vdd_npu_s0>; + power-domains =3D <&power RK3588_PD_NPUTOP>; + resets =3D <&cru SRST_A_RKNN0>, <&cru SRST_H_RKNN0>; + reset-names =3D "srst_a", "srst_h"; + sram-supply =3D <&vdd_npu_mem_s0>; + }; + }; +... --=20 2.49.0