From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 637F527C179 for ; Thu, 5 Jun 2025 19:24:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151455; cv=none; b=b2/nrRoq4jv//O10Kf4nG0HLf8vAxyCLKp3yz6sqXu03UwhLTJ/WU7SIhbwOJfN8yDO37eDSRoZYTbryCC7Jjg1jmnb6+hF/SHjGsogx87+VTYe5yFdHDh2lUA/IQVweJslMxB6YzywZqOIdWmL7MAeborX5PoY/2ppPZ3Z1Ofc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151455; c=relaxed/simple; bh=6Pf/tXMZzJo5FfKHir7iP/T7zDvDoWdK5wp07Bj9XFo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=uwAXFzjBKqn3dXfgkxjP7P1w2BPkpsRbj++K4gmqjtcfLCEs4H53ysyiNW1bL6MnoQoYsTKhhsWQHTaGoIZJarsITHU/301QfGI12nm4nvFund6D+5GkIyOsboo6GNCAEhV2DaChkbQyvgRFeeujWVYn47WA4zzY0uSMivCezQE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=CbsIvaIQ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=7Y7zJbPL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="CbsIvaIQ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="7Y7zJbPL" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151452; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=moW3grsIEEkZ24nmNYOLsz6RTNF0J1cs4slM6upzMSY=; b=CbsIvaIQ+bas0+eL4kt8Vx3JpOCwCsS0s4As6sD8nA+tSj0sRLPvqyGHRjx4cmPgeMPwAL wGAyo9P5PRWZYnxcwREWK/LmgDF64Rp26IP8lm+/WEmkCUdirZCSRi7suKYvEdfAHcbsNa sKTnXse64hvuQ1zdRx8uJ/CBB8hL7FDWu5Rs+xj/YNc/KGgtlZ6QaIrArzhdkUxKRb9WBC 9a8iOA6xH9xtk9h6sbBw2twvTFQrUHWvVOdqFee4i2oi8+bfOyQXJYZNr1r+nbOMBeEjG7 MQ5hPCLdYEObgQFooTKS3HRQbjic+HuKK6FQZSHNVmJCt3LTyapOOaUtyIX6AA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151452; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=moW3grsIEEkZ24nmNYOLsz6RTNF0J1cs4slM6upzMSY=; b=7Y7zJbPLyB7UdfllbHAtT/GpbP7jSDSMskWOKQOgaginVJUEZm9BcBon5V36GTaq9yvfji IthbvNCEWjtGaSCw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 01/27] x86/cpuid: Remove transitional header Date: Thu, 5 Jun 2025 21:23:30 +0200 Message-ID: <20250605192356.82250-2-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All CPUID call sites were updated at commit: 968e30006807 ("x86/cpuid: Set as the main CPUID heade= r") to include instead of . The header was still retained as a wrapper, just in case some new code in -next started using it. Now that everything is merged to Linus' tree, remove the header. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid.h | 8 -------- 1 file changed, 8 deletions(-) delete mode 100644 arch/x86/include/asm/cpuid.h diff --git a/arch/x86/include/asm/cpuid.h b/arch/x86/include/asm/cpuid.h deleted file mode 100644 index d5749b25fa10..000000000000 --- a/arch/x86/include/asm/cpuid.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0 */ - -#ifndef _ASM_X86_CPUID_H -#define _ASM_X86_CPUID_H - -#include - -#endif /* _ASM_X86_CPUID_H */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C5E4227CCE0 for ; Thu, 5 Jun 2025 19:24:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151458; cv=none; b=DpLYMYXQcIUghy6e0+eQNHT2vRYiZow6n9ccDA8v46ly4uGJ5MWG3oD5p/jTVYoH2B/4TGbkY7l2dZYNBGZjfnnwVmE5To7HYXYfwgbt0IS0PNhT1t7EXkQ43XGLehji/UdpRWEPPF+SB+lWaLcBGoGkJ1CsgVP24Tl1ghF0fOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151458; c=relaxed/simple; bh=F4tqLRtbGgjBpOY21OndsaKH9Gm167SzfWMAbd4Sp5M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QJf1UkhT+J7RMfHL5jmV5u8mCZNOmnn5M7HWqg0D7m0Lv3uohOSm1plK/898Q+XiP/+lJjIrOfez++zuS50K65lfjSYZHUqk0c1JMiNUYmuav8UTQLjeCJdL0N28eD02xW8i0czT/oPxxX7N/wasK/HoOrcFbyDqKpj/O1X5Nec= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KkCtZJnl; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=oDl0P0AG; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KkCtZJnl"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="oDl0P0AG" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151455; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=amNIawb44I9zROWG5Fp3ygnS3V/5NV1r2k2CpbHjiNU=; b=KkCtZJnlgkoaW60KefV5QCnjyBN9xw/NmBWKCc1UQ7GXzOyXxpyh/TTp3aFwZXrZzveujn RQUrKHndtZzJOhC7tSjVTVs1JK01q+Ua+x+4T/dfcvI3GWjtISXPVafU8txr/vPe6sq70i w2AyjdJ1Zu4GGBuydLCa84SKecqM8F4JovC4Xu0ouZ3BbLiIWBH3AGnAF9oIbmLCJTKNca SzJt8DKsqqmI6O6odmAdY4psoAJm25MTrqMZ8qwuQLXny0l0TYWV8kv6cnVO+FpyK6RaMg jPqWeIRQy8JDSK7IokTi8ur8vrgsSrLS9rQv7i4SF6DTpDQjcTFs/MiZGt5tKw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151455; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=amNIawb44I9zROWG5Fp3ygnS3V/5NV1r2k2CpbHjiNU=; b=oDl0P0AGeJYA2wg45260GkyrmMV7JjM+T9/fTHQ2V+vYQzg5n/ctyNGXtlHs21NPvKLkf1 P3CKVOenYmv5wJCg== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 02/27] x86/cpuid: Rename cpuid_leaf()/cpuid_subleaf() APIs Date: Thu, 5 Jun 2025 21:23:31 +0200 Message-ID: <20250605192356.82250-3-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" A new CPUID model will be added where its APIs will be designated as the "official" CPUID API. Free the cpuid_leaf() and cpuid_subleaf() function names for that model. Rename them accordingly to cpuid_read() and cpuid_read_subleaf(). Note, for kernel/cpuid.c, rename its local file operations read function from cpuid_read() to cpuid_read_f() so that it does not conflict with the new names. No functional change. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 6 +++--- arch/x86/kernel/cpu/topology_amd.c | 2 +- arch/x86/kernel/cpu/topology_ext.c | 2 +- arch/x86/kernel/cpuid.c | 5 ++--- 4 files changed, 7 insertions(+), 8 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 44fa82e1267c..2b9750cc8a75 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -131,12 +131,12 @@ static inline void __cpuid_read(u32 leaf, u32 subleaf= , u32 *regs) __cpuid(regs + CPUID_EAX, regs + CPUID_EBX, regs + CPUID_ECX, regs + CPUI= D_EDX); } =20 -#define cpuid_subleaf(leaf, subleaf, regs) { \ +#define cpuid_read_subleaf(leaf, subleaf, regs) { \ static_assert(sizeof(*(regs)) =3D=3D 16); \ __cpuid_read(leaf, subleaf, (u32 *)(regs)); \ } =20 -#define cpuid_leaf(leaf, regs) { \ +#define cpuid_read(leaf, regs) { \ static_assert(sizeof(*(regs)) =3D=3D 16); \ __cpuid_read(leaf, 0, (u32 *)(regs)); \ } @@ -228,7 +228,7 @@ static inline u32 cpuid_base_hypervisor(const char *sig= , u32 leaves) */ static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) { - cpuid_leaf(0x2, regs); + cpuid_read(0x2, regs); =20 /* * All Intel CPUs must report an iteration count of 1. In case diff --git a/arch/x86/kernel/cpu/topology_amd.c b/arch/x86/kernel/cpu/topol= ogy_amd.c index 843b1655ab45..efef40733e04 100644 --- a/arch/x86/kernel/cpu/topology_amd.c +++ b/arch/x86/kernel/cpu/topology_amd.c @@ -79,7 +79,7 @@ static bool parse_8000_001e(struct topo_scan *tscan, bool= has_topoext) if (!boot_cpu_has(X86_FEATURE_TOPOEXT)) return false; =20 - cpuid_leaf(0x8000001e, &leaf); + cpuid_read(0x8000001e, &leaf); =20 tscan->c->topo.initial_apicid =3D leaf.ext_apic_id; =20 diff --git a/arch/x86/kernel/cpu/topology_ext.c b/arch/x86/kernel/cpu/topol= ogy_ext.c index 467b0326bf1a..41fdcce16a38 100644 --- a/arch/x86/kernel/cpu/topology_ext.c +++ b/arch/x86/kernel/cpu/topology_ext.c @@ -70,7 +70,7 @@ static inline bool topo_subleaf(struct topo_scan *tscan, = u32 leaf, u32 subleaf, default: return false; } =20 - cpuid_subleaf(leaf, subleaf, &sl); + cpuid_read_subleaf(leaf, subleaf, &sl); =20 if (!sl.num_processors || sl.type =3D=3D INVALID_TYPE) return false; diff --git a/arch/x86/kernel/cpuid.c b/arch/x86/kernel/cpuid.c index dae436253de4..5b21ecbd9c8e 100644 --- a/arch/x86/kernel/cpuid.c +++ b/arch/x86/kernel/cpuid.c @@ -58,8 +58,7 @@ static void cpuid_smp_cpuid(void *cmd_block) complete(&cmd->done); } =20 -static ssize_t cpuid_read(struct file *file, char __user *buf, - size_t count, loff_t *ppos) +static ssize_t cpuid_read_f(struct file *file, char __user *buf, size_t co= unt, loff_t *ppos) { char __user *tmp =3D buf; struct cpuid_regs_done cmd; @@ -119,7 +118,7 @@ static int cpuid_open(struct inode *inode, struct file = *file) static const struct file_operations cpuid_fops =3D { .owner =3D THIS_MODULE, .llseek =3D no_seek_end_llseek, - .read =3D cpuid_read, + .read =3D cpuid_read_f, .open =3D cpuid_open, }; =20 --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 807B327D77A for ; Thu, 5 Jun 2025 19:24:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151464; cv=none; b=QUsc7RBUSw01RGvJmMR0ERwhr+7JPYQrUKzTs5XFdx6ROT5DcpG6QJUjJchAo0HArTN4qN21MgxRZb36PaUevEfz8bOeeefK79inNjl+MyphaHpQFEaOumYXeTeD+/TLJ+WXj06I0g2U5A1SrzVFMaFmMtV+/KqbkBmJY086R7w= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151464; c=relaxed/simple; bh=hKFDSkKCdphgtH2LTdXdSC/zL9LfNEgbZ4nhBIrF5lY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=RUMD7vIEuvqbvqWas2BLWWZb3S0O/8roldo2GNBv5uCduoy5LlqflajiAnIALBzW8x9vjEH++aHGoWu74dRgfo89xL4zyjLooLlEW2xLzfyyIrKOx7pa6LMFvp4xdGKoO5cI8atz31ExmMx3ACRTL8ku1pL0JVm7uju2We2wxm0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=synB4aIX; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=TBdmgdK7; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="synB4aIX"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="TBdmgdK7" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151458; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ciAP+w2VKtvZD/K7O3uLXVucQsr5IHouJ4YnYItiFGc=; b=synB4aIXJ7/w3j3EIQF8ReypPFNs4TO5cYajSCW7VWndEoaMG7OPCq+e9ZSP3P+6nutDRN qpCkkfyVgDPgReLE2cp+6zCsGH0OPPY1PJii2TuoG3v+YJ3P0RtmzDLiGgVjzP1QONOxId +nR+V2odsE+gKSkg2knAtU8QzFGDDmrrlgE5hgQO0CdqrISYOWj1q/dB2RTrE9v44w7JIf Dyc8mdi1Ifk9eqF3m/IsB+7pVvu3EpZqWC94Zt709BVnvB+ZWJARyXM3stidb1h970TLzD t3yEFcPO6cK0ZbmdCkHIoIF3783p3eI4NKR9roC0vBdSNIIs07UTc4rRYmT7qg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151458; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ciAP+w2VKtvZD/K7O3uLXVucQsr5IHouJ4YnYItiFGc=; b=TBdmgdK7pxM36oIAwcjosazApUK6HIfYdzjX2Ad0yCHPDp+TUlcTNGc8MDuUaBAVBI+ANm dFm2H0UgbPkp1NBQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 03/27] x86/cpuid: Introduce Date: Thu, 5 Jun 2025 21:23:32 +0200 Message-ID: <20250605192356.82250-4-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To centralize CPUID access across the x86 subsystem, introduce . It is generated by the x86-cpuid-db project and includes detailed C99 bitfield listings for all publicly known CPUID leaves. Add the header to MAINTAINERS x86 CPUID database entry. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db/-/blob/v2.4/CHANGELOG.r= st --- MAINTAINERS | 1 + arch/x86/include/asm/cpuid/leaf_types.h | 2055 +++++++++++++++++++++++ 2 files changed, 2056 insertions(+) create mode 100644 arch/x86/include/asm/cpuid/leaf_types.h diff --git a/MAINTAINERS b/MAINTAINERS index eecc41c39a9c..d99c4d4e8f62 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -26716,6 +26716,7 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org +F: arch/x86/include/asm/cpuid/leaf_types.h F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE diff --git a/arch/x86/include/asm/cpuid/leaf_types.h b/arch/x86/include/asm= /cpuid/leaf_types.h new file mode 100644 index 000000000000..0af2f67aee40 --- /dev/null +++ b/arch/x86/include/asm/cpuid/leaf_types.h @@ -0,0 +1,2055 @@ +/* SPDX-License-Identifier: MIT */ +/* Generator: x86-cpuid-db v2.4 */ + +/* + * Auto-generated file. + * Please submit all updates and bugfixes to https://x86-cpuid.org + */ + +#ifndef _ASM_X86_CPUID_LEAVES +#define _ASM_X86_CPUID_LEAVES + +#include + +/* + * Leaf 0x0 + * Maximum standard leaf number + CPU vendor string + */ + +struct leaf_0x0_0 { + // eax + u32 max_std_leaf : 32; // Highest standard CPUID leaf supported + // ebx + u32 cpu_vendorid_0 : 32; // CPU vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x1 + * CPU FMS (Family/Model/Stepping) + standard feature flags + */ + +struct leaf_0x1_0 { + // eax + u32 stepping : 4, // Stepping ID + base_model : 4, // Base CPU model ID + base_family_id : 4, // Base CPU family ID + cpu_type : 2, // CPU type + : 2, // Reserved + ext_model : 4, // Extended CPU model ID + ext_family : 8, // Extended CPU family ID + : 4; // Reserved + // ebx + u32 brand_id : 8, // Brand index + clflush_size : 8, // CLFLUSH instruction cache line size + n_logical_cpu : 8, // Logical CPU count + local_apic_id : 8; // Initial local APIC physical ID + // ecx + u32 sse3 : 1, // Streaming SIMD Extensions 3 (SSE3) + pclmulqdq : 1, // PCLMULQDQ instruction support + dtes64 : 1, // 64-bit DS save area + monitor : 1, // MONITOR/MWAIT support + dscpl : 1, // CPL Qualified Debug Store + vmx : 1, // Virtual Machine Extensions + smx : 1, // Safer Mode Extensions + est : 1, // Enhanced Intel SpeedStep + tm2 : 1, // Thermal Monitor 2 + ssse3 : 1, // Supplemental SSE3 + cntxt_id : 1, // L1 Context ID + sdbg : 1, // Silicon Debug + fma : 1, // FMA extensions using YMM state + cx16 : 1, // CMPXCHG16B instruction support + xtpr_update : 1, // xTPR Update Control + pdcm : 1, // Perfmon and Debug Capability + : 1, // Reserved + pcid : 1, // Process-context identifiers + dca : 1, // Direct Cache Access + sse4_1 : 1, // SSE4.1 + sse4_2 : 1, // SSE4.2 + x2apic : 1, // X2APIC support + movbe : 1, // MOVBE instruction support + popcnt : 1, // POPCNT instruction support + tsc_deadline_timer : 1, // APIC timer one-shot operation + aes : 1, // AES instructions + xsave : 1, // XSAVE (and related instructions) support + osxsave : 1, // XSAVE (and related instructions) are enabled by OS + avx : 1, // AVX instructions support + f16c : 1, // Half-precision floating-point conversion support + rdrand : 1, // RDRAND instruction support + guest_status : 1; // System is running as guest; (para-)virtualized s= ystem + // edx + u32 fpu : 1, // Floating-Point Unit on-chip (x87) + vme : 1, // Virtual-8086 Mode Extensions + de : 1, // Debugging Extensions + pse : 1, // Page Size Extension + tsc : 1, // Time Stamp Counter + msr : 1, // Model-Specific Registers (RDMSR and WRMSR support) + pae : 1, // Physical Address Extensions + mce : 1, // Machine Check Exception + cx8 : 1, // CMPXCHG8B instruction + apic : 1, // APIC on-chip + : 1, // Reserved + sep : 1, // SYSENTER, SYSEXIT, and associated MSRs + mtrr : 1, // Memory Type Range Registers + pge : 1, // Page Global Extensions + mca : 1, // Machine Check Architecture + cmov : 1, // Conditional Move Instruction + pat : 1, // Page Attribute Table + pse36 : 1, // Page Size Extension (36-bit) + psn : 1, // Processor Serial Number + clflush : 1, // CLFLUSH instruction + : 1, // Reserved + ds : 1, // Debug Store + acpi : 1, // Thermal monitor and clock control + mmx : 1, // MMX instructions + fxsr : 1, // FXSAVE and FXRSTOR instructions + sse : 1, // SSE instructions + sse2 : 1, // SSE2 instructions + selfsnoop : 1, // Self Snoop + htt : 1, // Hyper-threading + tm : 1, // Thermal Monitor + ia64 : 1, // Legacy IA-64 (Itanium) support bit, now reserved + pbe : 1; // Pending Break Enable +}; + +/* + * Leaf 0x2 + * Intel cache and TLB information one-byte descriptors + */ + +struct leaf_0x2_0 { + // eax + u32 iteration_count : 8, // Number of times this leaf must be queried + desc1 : 8, // Descriptor #1 + desc2 : 8, // Descriptor #2 + desc3 : 7, // Descriptor #3 + eax_invalid : 1; // Descriptors 1-3 are invalid if set + // ebx + u32 desc4 : 8, // Descriptor #4 + desc5 : 8, // Descriptor #5 + desc6 : 8, // Descriptor #6 + desc7 : 7, // Descriptor #7 + ebx_invalid : 1; // Descriptors 4-7 are invalid if set + // ecx + u32 desc8 : 8, // Descriptor #8 + desc9 : 8, // Descriptor #9 + desc10 : 8, // Descriptor #10 + desc11 : 7, // Descriptor #11 + ecx_invalid : 1; // Descriptors 8-11 are invalid if set + // edx + u32 desc12 : 8, // Descriptor #12 + desc13 : 8, // Descriptor #13 + desc14 : 8, // Descriptor #14 + desc15 : 7, // Descriptor #15 + edx_invalid : 1; // Descriptors 12-15 are invalid if set +}; + +/* + * Leaf 0x4 + * Intel deterministic cache parameters + */ + +struct leaf_0x4_0 { + // eax + u32 cache_type : 5, // Cache type field + cache_level : 3, // Cache level (1-based) + cache_self_init : 1, // Self-initializing cache level + fully_associative : 1, // Fully-associative cache + : 4, // Reserved + num_threads_sharing : 12, // Number logical CPUs sharing this cache + num_cores_on_die : 6; // Number of cores in the physical package + // ebx + u32 cache_linesize : 12, // System coherency line size (0-based) + cache_npartitions : 10, // Physical line partitions (0-based) + cache_nways : 10; // Ways of associativity (0-based) + // ecx + u32 cache_nsets : 31, // Cache number of sets (0-based) + : 1; // Reserved + // edx + u32 wbinvd_rll_no_guarantee : 1, // WBINVD/INVD not guaranteed for Remo= te Lower-Level caches + ll_inclusive : 1, // Cache is inclusive of Lower-Level caches + complex_indexing : 1, // Not a direct-mapped cache (complex function) + : 29; // Reserved +}; + +/* + * Leaf 0x5 + * MONITOR/MWAIT instructions enumeration + */ + +struct leaf_0x5_0 { + // eax + u32 min_mon_size : 16, // Smallest monitor-line size, in bytes + : 16; // Reserved + // ebx + u32 max_mon_size : 16, // Largest monitor-line size, in bytes + : 16; // Reserved + // ecx + u32 mwait_ext : 1, // Enumeration of MONITOR/MWAIT extensions is suppo= rted + mwait_irq_break : 1, // Interrupts as a break-event for MWAIT is supp= orted + : 30; // Reserved + // edx + u32 n_c0_substates : 4, // Number of C0 sub C-states supported using M= WAIT + n_c1_substates : 4, // Number of C1 sub C-states supported using MWAIT + n_c2_substates : 4, // Number of C2 sub C-states supported using MWAIT + n_c3_substates : 4, // Number of C3 sub C-states supported using MWAIT + n_c4_substates : 4, // Number of C4 sub C-states supported using MWAIT + n_c5_substates : 4, // Number of C5 sub C-states supported using MWAIT + n_c6_substates : 4, // Number of C6 sub C-states supported using MWAIT + n_c7_substates : 4; // Number of C7 sub C-states supported using MWAIT +}; + +/* + * Leaf 0x6 + * Thermal and Power Management enumeration + */ + +struct leaf_0x6_0 { + // eax + u32 digital_temp : 1, // Digital temperature sensor + turbo_boost : 1, // Intel Turbo Boost + lapic_timer_always_on : 1, // Always-Running APIC Timer (not affected = by p-state) + : 1, // Reserved + power_limit_event : 1, // Power Limit Notification (PLN) event + ecmd : 1, // Clock modulation duty cycle extension + package_thermal : 1, // Package thermal management + hwp_base_regs : 1, // HWP (Hardware P-states) base registers are supp= orted + hwp_notify : 1, // HWP notification (IA32_HWP_INTERRUPT MSR) + hwp_activity_window : 1, // HWP activity window (IA32_HWP_REQUEST[bits= 41:32]) supported + hwp_energy_perf_pr : 1, // HWP Energy Performance Preference + hwp_package_req : 1, // HWP Package Level Request + : 1, // Reserved + hdc_base_regs : 1, // HDC base registers are supported + turbo_boost_3_0 : 1, // Intel Turbo Boost Max 3.0 + hwp_capabilities : 1, // HWP Highest Performance change + hwp_peci_override : 1, // HWP PECI override + hwp_flexible : 1, // Flexible HWP + hwp_fast : 1, // IA32_HWP_REQUEST MSR fast access mode + hw_feedback : 1, // HW_FEEDBACK MSRs supported + hwp_ignore_idle : 1, // Ignoring idle logical CPU HWP req is supported + : 2, // Reserved + thread_director : 1, // Intel thread director support + therm_interrupt_bit25 : 1, // IA32_THERM_INTERRUPT MSR bit 25 is suppo= rted + : 7; // Reserved + // ebx + u32 n_therm_thresholds : 4, // Digital thermometer thresholds + : 28; // Reserved + // ecx + u32 aperf_mperf : 1, // MPERF/APERF MSRs (effective frequency interfac= e) + : 2, // Reserved + energy_perf_bias : 1, // IA32_ENERGY_PERF_BIAS MSR support + : 4, // Reserved + thrd_director_nclasses : 8, // Number of classes, Intel thread director + : 16; // Reserved + // edx + u32 perfcap_reporting : 1, // Performance capability reporting + encap_reporting : 1, // Energy efficiency capability reporting + : 6, // Reserved + feedback_sz : 4, // Feedback interface structure size, in 4K pages + : 4, // Reserved + this_lcpu_hwfdbk_idx : 16; // This logical CPU hardware feedback interf= ace index +}; + +/* + * Leaf 0x7 + * Extended CPU features enumeration + */ + +struct leaf_0x7_0 { + // eax + u32 leaf7_n_subleaves : 32; // Number of leaf 0x7 subleaves + // ebx + u32 fsgsbase : 1, // FSBASE/GSBASE read/write support + tsc_adjust : 1, // IA32_TSC_ADJUST MSR supported + sgx : 1, // Intel SGX (Software Guard Extensions) + bmi1 : 1, // Bit manipulation extensions group 1 + hle : 1, // Hardware Lock Elision + avx2 : 1, // AVX2 instruction set + fdp_excptn_only : 1, // FPU Data Pointer updated only on x87 exceptio= ns + smep : 1, // Supervisor Mode Execution Protection + bmi2 : 1, // Bit manipulation extensions group 2 + erms : 1, // Enhanced REP MOVSB/STOSB + invpcid : 1, // INVPCID instruction (Invalidate Processor Context ID) + rtm : 1, // Intel restricted transactional memory + pqm : 1, // Intel RDT-CMT / AMD Platform-QoS cache monitoring + zero_fcs_fds : 1, // Deprecated FPU CS/DS (stored as zero) + mpx : 1, // Intel memory protection extensions + rdt_a : 1, // Intel RDT / AMD Platform-QoS Enforcement + avx512f : 1, // AVX-512 foundation instructions + avx512dq : 1, // AVX-512 double/quadword instructions + rdseed : 1, // RDSEED instruction + adx : 1, // ADCX/ADOX instructions + smap : 1, // Supervisor mode access prevention + avx512ifma : 1, // AVX-512 integer fused multiply add + : 1, // Reserved + clflushopt : 1, // CLFLUSHOPT instruction + clwb : 1, // CLWB instruction + intel_pt : 1, // Intel processor trace + avx512pf : 1, // AVX-512 prefetch instructions + avx512er : 1, // AVX-512 exponent/reciprocal instructions + avx512cd : 1, // AVX-512 conflict detection instructions + sha : 1, // SHA/SHA256 instructions + avx512bw : 1, // AVX-512 byte/word instructions + avx512vl : 1; // AVX-512 VL (128/256 vector length) extensions + // ecx + u32 prefetchwt1 : 1, // PREFETCHWT1 (Intel Xeon Phi only) + avx512vbmi : 1, // AVX-512 Vector byte manipulation instructions + umip : 1, // User mode instruction protection + pku : 1, // Protection keys for user-space + ospke : 1, // OS protection keys enable + waitpkg : 1, // WAITPKG instructions + avx512_vbmi2 : 1, // AVX-512 vector byte manipulation instructions gr= oup 2 + cet_ss : 1, // CET shadow stack features + gfni : 1, // Galois field new instructions + vaes : 1, // Vector AES instructions + vpclmulqdq : 1, // VPCLMULQDQ 256-bit instruction support + avx512_vnni : 1, // Vector neural network instructions + avx512_bitalg : 1, // AVX-512 bitwise algorithms + tme : 1, // Intel total memory encryption + avx512_vpopcntdq : 1, // AVX-512: POPCNT for vectors of DWORD/QWORD + : 1, // Reserved + la57 : 1, // 57-bit linear addresses (five-level paging) + mawau_val_lm : 5, // BNDLDX/BNDSTX MAWAU value in 64-bit mode + rdpid : 1, // RDPID instruction + key_locker : 1, // Intel key locker support + bus_lock_detect : 1, // OS bus-lock detection + cldemote : 1, // CLDEMOTE instruction + : 1, // Reserved + movdiri : 1, // MOVDIRI instruction + movdir64b : 1, // MOVDIR64B instruction + enqcmd : 1, // Enqueue stores supported (ENQCMD{,S}) + sgx_lc : 1, // Intel SGX launch configuration + pks : 1; // Protection keys for supervisor-mode pages + // edx + u32 : 1, // Reserved + sgx_keys : 1, // Intel SGX attestation services + avx512_4vnniw : 1, // AVX-512 neural network instructions + avx512_4fmaps : 1, // AVX-512 multiply accumulation single precision + fsrm : 1, // Fast short REP MOV + uintr : 1, // CPU supports user interrupts + : 2, // Reserved + avx512_vp2intersect : 1, // VP2INTERSECT{D,Q} instructions + srdbs_ctrl : 1, // SRBDS mitigation MSR available + md_clear : 1, // VERW MD_CLEAR microcode support + rtm_always_abort : 1, // XBEGIN (RTM transaction) always aborts + : 1, // Reserved + tsx_force_abort : 1, // MSR TSX_FORCE_ABORT, RTM_ABORT bit, supported + serialize : 1, // SERIALIZE instruction + hybrid_cpu : 1, // The CPU is identified as a 'hybrid part' + tsxldtrk : 1, // TSX suspend/resume load address tracking + : 1, // Reserved + pconfig : 1, // PCONFIG instruction + arch_lbr : 1, // Intel architectural LBRs + cet_ibt : 1, // CET indirect branch tracking + : 1, // Reserved + amx_bf16 : 1, // AMX-BF16: tile bfloat16 support + avx512_fp16 : 1, // AVX-512 FP16 instructions + amx_tile : 1, // AMX-TILE: tile architecture support + amx_int8 : 1, // AMX-INT8: tile 8-bit integer support + spec_ctrl : 1, // Speculation Control (IBRS/IBPB: indirect branch res= trictions) + intel_stibp : 1, // Single thread indirect branch predictors + flush_l1d : 1, // FLUSH L1D cache: IA32_FLUSH_CMD MSR + arch_capabilities : 1, // Intel IA32_ARCH_CAPABILITIES MSR + core_capabilities : 1, // IA32_CORE_CAPABILITIES MSR + spec_ctrl_ssbd : 1; // Speculative store bypass disable +}; + +struct leaf_0x7_1 { + // eax + u32 : 4, // Reserved + avx_vnni : 1, // AVX-VNNI instructions + avx512_bf16 : 1, // AVX-512 bfloat16 instructions + lass : 1, // Linear address space separation + cmpccxadd : 1, // CMPccXADD instructions + arch_perfmon_ext : 1, // ArchPerfmonExt: leaf 0x23 is supported + : 1, // Reserved + fzrm : 1, // Fast zero-length REP MOVSB + fsrs : 1, // Fast short REP STOSB + fsrc : 1, // Fast Short REP CMPSB/SCASB + : 4, // Reserved + fred : 1, // FRED: Flexible return and event delivery transitions + lkgs : 1, // LKGS: Load 'kernel' (userspace) GS + wrmsrns : 1, // WRMSRNS instruction (WRMSR-non-serializing) + nmi_src : 1, // NMI-source reporting with FRED event data + amx_fp16 : 1, // AMX-FP16: FP16 tile operations + hreset : 1, // History reset support + avx_ifma : 1, // Integer fused multiply add + : 2, // Reserved + lam : 1, // Linear address masking + rd_wr_msrlist : 1, // RDMSRLIST/WRMSRLIST instructions + : 4; // Reserved + // ebx + u32 intel_ppin : 1, // Protected processor inventory number (PPIN{,_CT= L} MSRs) + : 31; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 4, // Reserved + avx_vnni_int8 : 1, // AVX-VNNI-INT8 instructions + avx_ne_convert : 1, // AVX-NE-CONVERT instructions + : 2, // Reserved + amx_complex : 1, // AMX-COMPLEX instructions (starting from Granite R= apids) + : 5, // Reserved + prefetchit_0_1 : 1, // PREFETCHIT0/1 instructions + : 3, // Reserved + cet_sss : 1, // CET supervisor shadow stacks safe to use + : 13; // Reserved +}; + +struct leaf_0x7_2 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 intel_psfd : 1, // Intel predictive store forward disable + ipred_ctrl : 1, // MSR bits IA32_SPEC_CTRL.IPRED_DIS_{U,S} + rrsba_ctrl : 1, // MSR bits IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + ddp_ctrl : 1, // MSR bit IA32_SPEC_CTRL.DDPD_U + bhi_ctrl : 1, // MSR bit IA32_SPEC_CTRL.BHI_DIS_S + mcdt_no : 1, // MCDT mitigation not needed + uclock_disable : 1, // UC-lock disable is supported + : 25; // Reserved +}; + +/* + * Leaf 0x9 + * Intel DCA (Direct Cache Access) enumeration + */ + +struct leaf_0x9_0 { + // eax + u32 dca_enabled_in_bios : 1, // DCA is enabled in BIOS + : 31; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xa + * Intel PMU (Performance Monitoring Unit) enumeration + */ + +struct leaf_0xa_0 { + // eax + u32 pmu_version : 8, // Performance monitoring unit version ID + pmu_n_gcounters : 8, // Number of general PMU counters per logical CPU + pmu_gcounters_nbits : 8, // Bitwidth of PMU general counters + pmu_cpuid_ebx_bits : 8; // Length of leaf 0xa EBX bit vector + // ebx + u32 no_core_cycle_evt : 1, // Core cycle event not available + no_insn_retired_evt : 1, // Instruction retired event not available + no_refcycle_evt : 1, // Reference cycles event not available + no_llc_ref_evt : 1, // LLC-reference event not available + no_llc_miss_evt : 1, // LLC-misses event not available + no_br_insn_ret_evt : 1, // Branch instruction retired event not availa= ble + no_br_mispredict_evt : 1, // Branch mispredict retired event not avail= able + no_td_slots_evt : 1, // Topdown slots event not available + : 24; // Reserved + // ecx + u32 pmu_fcounters_bitmap : 32; // Fixed-function PMU counters support bi= tmap + // edx + u32 pmu_n_fcounters : 5, // Number of fixed PMU counters + pmu_fcounters_nbits : 8, // Bitwidth of PMU fixed counters + : 2, // Reserved + anythread_depr : 1, // AnyThread deprecation + : 16; // Reserved +}; + +/* + * Leaf 0xb + * CPUs v1 extended topology enumeration + */ + +struct leaf_0xb_0 { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 27; // Reserved + // ebx + u32 domain_lcpus_count : 16, // Logical CPUs count across all instances = of this domain + : 16; // Reserved + // ecx + u32 domain_nr : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +/* + * Leaf 0xd + * Processor extended state enumeration + */ + +struct leaf_0xd_0 { + // eax + u32 xcr0_x87 : 1, // XCR0.X87 (bit 0) supported + xcr0_sse : 1, // XCR0.SEE (bit 1) supported + xcr0_avx : 1, // XCR0.AVX (bit 2) supported + xcr0_mpx_bndregs : 1, // XCR0.BNDREGS (bit 3) supported (MPX BND0-BND3= registers) + xcr0_mpx_bndcsr : 1, // XCR0.BNDCSR (bit 4) supported (MPX BNDCFGU/BN= DSTATUS registers) + xcr0_avx512_opmask : 1, // XCR0.OPMASK (bit 5) supported (AVX-512 k0-k= 7 registers) + xcr0_avx512_zmm_hi256 : 1, // XCR0.ZMM_Hi256 (bit 6) supported (AVX-51= 2 ZMM0->ZMM7/15 registers) + xcr0_avx512_hi16_zmm : 1, // XCR0.HI16_ZMM (bit 7) supported (AVX-512 = ZMM16->ZMM31 registers) + : 1, // Reserved + xcr0_pkru : 1, // XCR0.PKRU (bit 9) supported (XSAVE PKRU registers) + : 1, // Reserved + xcr0_cet_u : 1, // XCR0.CET_U (bit 11) supported (CET user state) + xcr0_cet_s : 1, // XCR0.CET_S (bit 12) supported (CET supervisor stat= e) + : 4, // Reserved + xcr0_tileconfig : 1, // XCR0.TILECONFIG (bit 17) supported (AMX can m= anage TILECONFIG) + xcr0_tiledata : 1, // XCR0.TILEDATA (bit 18) supported (AMX can manag= e TILEDATA) + : 13; // Reserved + // ebx + u32 xsave_sz_xcr0_enabled : 32; // XSAVE/XRSTOR area byte size, for XCR0= enabled features + // ecx + u32 xsave_sz_max : 32; // XSAVE/XRSTOR area max byte size, all CPU feat= ures + // edx + u32 : 30, // Reserved + xcr0_lwp : 1, // AMD XCR0.LWP (bit 62) supported (Light-weight Profil= ing) + : 1; // Reserved +}; + +struct leaf_0xd_1 { + // eax + u32 xsaveopt : 1, // XSAVEOPT instruction + xsavec : 1, // XSAVEC instruction + xgetbv1 : 1, // XGETBV instruction with ECX =3D 1 + xsaves : 1, // XSAVES/XRSTORS instructions (and XSS MSR) + xfd : 1, // Extended feature disable support + : 27; // Reserved + // ebx + u32 xsave_sz_xcr0_xmms_enabled : 32; // XSAVE area size, all XCR0 and XMM= S features enabled + // ecx + u32 : 8, // Reserved + xss_pt : 1, // PT state, supported + : 1, // Reserved + xss_pasid : 1, // PASID state, supported + xss_cet_u : 1, // CET user state, supported + xss_cet_p : 1, // CET supervisor state, supported + xss_hdc : 1, // HDC state, supported + xss_uintr : 1, // UINTR state, supported + xss_lbr : 1, // LBR state, supported + xss_hwp : 1, // HWP state, supported + : 15; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0xd_2 { + // eax + u32 xsave_sz : 32; // Size of save area for subleaf-N feature, in bytes + // ebx + u32 xsave_offset : 32; // Offset of save area for subleaf-N feature, in= bytes + // ecx + u32 is_xss_bit : 1, // Subleaf N describes an XSS bit, otherwise XCR0 = bit + compacted_xsave_64byte_aligned : 1, // When compacted, subleaf-N featur= e XSAVE area is 64-byte aligned + : 30; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xf + * Intel RDT / AMD PQoS resource monitoring + */ + +struct leaf_0xf_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 core_rmid_max : 32; // RMID max, within this core, all types (0-bas= ed) + // ecx + u32 : 32; // Reserved + // edx + u32 : 1, // Reserved + llc_qos_mon : 1, // LLC QoS-monitoring supported + : 30; // Reserved +}; + +struct leaf_0xf_1 { + // eax + u32 l3c_qm_bitwidth : 8, // L3 QoS-monitoring counter bitwidth (24-bas= ed) + l3c_qm_overflow_bit : 1, // QM_CTR MSR bit 61 is an overflow bit + : 23; // Reserved + // ebx + u32 l3c_qm_conver_factor : 32; // QM_CTR MSR conversion factor to bytes + // ecx + u32 l3c_qm_rmid_max : 32; // L3 QoS-monitoring max RMID + // edx + u32 l3c_qm_occupancy : 1, // L3 QoS occupancy monitoring supported + l3c_qm_mbm_total : 1, // L3 QoS total bandwidth monitoring supported + l3c_qm_mbm_local : 1, // L3 QoS local bandwidth monitoring supported + : 29; // Reserved +}; + +/* + * Leaf 0x10 + * Intel RDT / AMD PQoS allocation enumeration + */ + +struct leaf_0x10_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 1, // Reserved + cat_l3 : 1, // L3 Cache Allocation Technology supported + cat_l2 : 1, // L2 Cache Allocation Technology supported + mba : 1, // Memory Bandwidth Allocation supported + : 28; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x10_1 { + // eax + u32 cat_cbm_len : 5, // L3/L2_CAT capacity bitmask length, minus-one n= otation + : 27; // Reserved + // ebx + u32 cat_units_bitmap : 32; // L3/L2_CAT bitmap of allocation units + // ecx + u32 : 1, // Reserved + l3_cat_cos_infreq_updates : 1, // L3_CAT COS updates should be infreque= nt + cat_cdp_supported : 1, // L3/L2_CAT CDP (Code and Data Prioritization) + cat_sparse_1s : 1, // L3/L2_CAT non-contiguous 1s value supported + : 28; // Reserved + // edx + u32 cat_cos_max : 16, // L3/L2_CAT max COS (Class of Service) supported + : 16; // Reserved +}; + +struct leaf_0x10_3 { + // eax + u32 mba_max_delay : 12, // Max MBA throttling value; minus-one notation + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 mba_per_thread : 1, // Per-thread MBA controls are supported + : 1, // Reserved + mba_delay_linear : 1, // Delay values are linear + : 29; // Reserved + // edx + u32 mba_cos_max : 16, // MBA max Class of Service supported + : 16; // Reserved +}; + +/* + * Leaf 0x12 + * Intel Software Guard Extensions (SGX) enumeration + */ + +struct leaf_0x12_0 { + // eax + u32 sgx1 : 1, // SGX1 leaf functions supported + sgx2 : 1, // SGX2 leaf functions supported + : 3, // Reserved + enclv_leaves : 1, // ENCLV leaves (E{INC,DEC}VIRTCHILD, ESETCONTEXT) = supported + encls_leaves : 1, // ENCLS leaves (ENCLS ETRACKC, ERDINFO, ELDBC, ELD= UC) supported + enclu_everifyreport2 : 1, // ENCLU leaf EVERIFYREPORT2 supported + : 2, // Reserved + encls_eupdatesvn : 1, // ENCLS leaf EUPDATESVN supported + enclu_edeccssa : 1, // ENCLU leaf EDECCSSA supported + : 20; // Reserved + // ebx + u32 miscselect_exinfo : 1, // SSA.MISC frame: reporting #PF and #GP exc= eptions inside enclave supported + miscselect_cpinfo : 1, // SSA.MISC frame: reporting #CP exceptions ins= ide enclave supported + : 30; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 max_enclave_sz_not64 : 8, // Maximum enclave size in non-64-bit mod= e (log2) + max_enclave_sz_64 : 8, // Maximum enclave size in 64-bit mode (log2) + : 16; // Reserved +}; + +struct leaf_0x12_1 { + // eax + u32 secs_attr_init : 1, // ATTRIBUTES.INIT supported (enclave initiali= zed by EINIT) + secs_attr_debug : 1, // ATTRIBUTES.DEBUG supported (enclave permits d= ebugger read/write) + secs_attr_mode64bit : 1, // ATTRIBUTES.MODE64BIT supported (enclave ru= ns in 64-bit mode) + : 1, // Reserved + secs_attr_provisionkey : 1, // ATTRIBUTES.PROVISIONKEY supported (prov= isioning key available) + secs_attr_einittoken_key : 1, // ATTRIBUTES.EINITTOKEN_KEY supported (E= INIT token key available) + secs_attr_cet : 1, // ATTRIBUTES.CET supported (enable CET attributes) + secs_attr_kss : 1, // ATTRIBUTES.KSS supported (Key Separation and Sh= aring enabled) + : 2, // Reserved + secs_attr_aexnotify : 1, // ATTRIBUTES.AEXNOTIFY supported (enclave th= reads may get AEX notifications + : 21; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 xfrm_x87 : 1, // Enclave XFRM.X87 (bit 0) supported + xfrm_sse : 1, // Enclave XFRM.SEE (bit 1) supported + xfrm_avx : 1, // Enclave XFRM.AVX (bit 2) supported + xfrm_mpx_bndregs : 1, // Enclave XFRM.BNDREGS (bit 3) supported (MPX B= ND0-BND3 registers) + xfrm_mpx_bndcsr : 1, // Enclave XFRM.BNDCSR (bit 4) supported (MPX BN= DCFGU/BNDSTATUS registers) + xfrm_avx512_opmask : 1, // Enclave XFRM.OPMASK (bit 5) supported (AVX-= 512 k0-k7 registers) + xfrm_avx512_zmm_hi256 : 1, // Enclave XFRM.ZMM_Hi256 (bit 6) supported= (AVX-512 ZMM0->ZMM7/15 registers) + xfrm_avx512_hi16_zmm : 1, // Enclave XFRM.HI16_ZMM (bit 7) supported (= AVX-512 ZMM16->ZMM31 registers) + : 1, // Reserved + xfrm_pkru : 1, // Enclave XFRM.PKRU (bit 9) supported (XSAVE PKRU reg= isters) + : 7, // Reserved + xfrm_tileconfig : 1, // Enclave XFRM.TILECONFIG (bit 17) supported (A= MX can manage TILECONFIG) + xfrm_tiledata : 1, // Enclave XFRM.TILEDATA (bit 18) supported (AMX c= an manage TILEDATA) + : 13; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x12_2 { + // eax + u32 subleaf_type : 4, // Subleaf type (dictates output layout) + : 8, // Reserved + epc_sec_base_addr_0 : 20; // EPC section base address, bits[12:31] + // ebx + u32 epc_sec_base_addr_1 : 20, // EPC section base address, bits[32:51] + : 12; // Reserved + // ecx + u32 epc_sec_type : 4, // EPC section type / property encoding + : 8, // Reserved + epc_sec_size_0 : 20; // EPC section size, bits[12:31] + // edx + u32 epc_sec_size_1 : 20, // EPC section size, bits[32:51] + : 12; // Reserved +}; + +/* + * Leaf 0x14 + * Intel Processor Trace enumeration + */ + +struct leaf_0x14_0 { + // eax + u32 pt_max_subleaf : 32; // Maximum leaf 0x14 subleaf + // ebx + u32 cr3_filtering : 1, // IA32_RTIT_CR3_MATCH is accessible + psb_cyc : 1, // Configurable PSB and cycle-accurate mode + ip_filtering : 1, // IP/TraceStop filtering; Warm-reset PT MSRs prese= rvation + mtc_timing : 1, // MTC timing packet; COFI-based packets suppression + ptwrite : 1, // PTWRITE support + power_event_trace : 1, // Power Event Trace support + psb_pmi_preserve : 1, // PSB and PMI preservation support + event_trace : 1, // Event Trace packet generation through IA32_RTIT_C= TL.EventEn + tnt_disable : 1, // TNT packet generation disable through IA32_RTIT_C= TL.DisTNT + : 23; // Reserved + // ecx + u32 topa_output : 1, // ToPA output scheme support + topa_multiple_entries : 1, // ToPA tables can hold multiple entries + single_range_output : 1, // Single-range output scheme supported + trance_transport_output : 1, // Trace Transport subsystem output suppo= rt + : 27, // Reserved + ip_payloads_lip : 1; // IP payloads have LIP values (CS base included) + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x14_1 { + // eax + u32 num_address_ranges : 3, // Filtering number of configurable Address= Ranges + : 13, // Reserved + mtc_periods_bmp : 16; // Bitmap of supported MTC period encodings + // ebx + u32 cycle_thresholds_bmp : 16, // Bitmap of supported Cycle Threshold en= codings + psb_periods_bmp : 16; // Bitmap of supported Configurable PSB frequenc= y encodings + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x15 + * Intel TSC (Time Stamp Counter) enumeration + */ + +struct leaf_0x15_0 { + // eax + u32 tsc_denominator : 32; // Denominator of the TSC/'core crystal clock= ' ratio + // ebx + u32 tsc_numerator : 32; // Numerator of the TSC/'core crystal clock' ra= tio + // ecx + u32 cpu_crystal_hz : 32; // Core crystal clock nominal frequency, in Hz + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x16 + * Intel processor frequency enumeration + */ + +struct leaf_0x16_0 { + // eax + u32 cpu_base_mhz : 16, // Processor base frequency, in MHz + : 16; // Reserved + // ebx + u32 cpu_max_mhz : 16, // Processor max frequency, in MHz + : 16; // Reserved + // ecx + u32 bus_mhz : 16, // Bus reference frequency, in MHz + : 16; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x17 + * Intel SoC vendor attributes enumeration + */ + +struct leaf_0x17_0 { + // eax + u32 soc_max_subleaf : 32; // Maximum leaf 0x17 subleaf + // ebx + u32 soc_vendor_id : 16, // SoC vendor ID + is_vendor_scheme : 1, // Assigned by industry enumeration scheme (not = Intel) + : 15; // Reserved + // ecx + u32 soc_proj_id : 32; // SoC project ID, assigned by vendor + // edx + u32 soc_stepping_id : 32; // Soc project stepping ID, assigned by vendor +}; + +struct leaf_0x17_1 { + // eax + u32 vendor_brand_a : 32; // Vendor Brand ID string, bytes subleaf_nr * = (0 -> 3) + // ebx + u32 vendor_brand_b : 32; // Vendor Brand ID string, bytes subleaf_nr * = (4 -> 7) + // ecx + u32 vendor_brand_c : 32; // Vendor Brand ID string, bytes subleaf_nr * = (8 -> 11) + // edx + u32 vendor_brand_d : 32; // Vendor Brand ID string, bytes subleaf_nr * = (12 -> 15) +}; + +/* + * Leaf 0x18 + * Intel determenestic address translation (TLB) parameters + */ + +struct leaf_0x18_0 { + // eax + u32 tlb_max_subleaf : 32; // Maximum leaf 0x18 subleaf + // ebx + u32 tlb_4k_page : 1, // TLB 4KB-page entries supported + tlb_2m_page : 1, // TLB 2MB-page entries supported + tlb_4m_page : 1, // TLB 4MB-page entries supported + tlb_1g_page : 1, // TLB 1GB-page entries supported + : 4, // Reserved + hard_partitioning : 3, // (Hard/Soft) partitioning between logical CPU= s sharing this structure + : 5, // Reserved + n_way_associative : 16; // Ways of associativity + // ecx + u32 n_sets : 32; // Number of sets + // edx + u32 tlb_type : 5, // Translation cache type (TLB type) + tlb_cache_level : 3, // Translation cache level (1-based) + is_fully_associative : 1, // Fully-associative structure + : 5, // Reserved + tlb_max_addressible_ids : 12, // Max number of addressable IDs for logi= cal CPUs sharing this TLB - 1 + : 6; // Reserved +}; + +/* + * Leaf 0x19 + * Intel Key Locker enumeration + */ + +struct leaf_0x19_0 { + // eax + u32 kl_cpl0_only : 1, // CPL0-only key Locker restriction supported + kl_no_encrypt : 1, // No-encrypt key locker restriction supported + kl_no_decrypt : 1, // No-decrypt key locker restriction supported + : 29; // Reserved + // ebx + u32 aes_keylocker : 1, // AES key locker instructions supported + : 1, // Reserved + aes_keylocker_wide : 1, // AES wide key locker instructions supported + : 1, // Reserved + kl_msr_iwkey : 1, // Key locker MSRs and IWKEY backups supported + : 27; // Reserved + // ecx + u32 loadiwkey_no_backup : 1, // LOADIWKEY NoBackup parameter supported + iwkey_rand : 1, // IWKEY randomization (KeySource encoding 1) support= ed + : 30; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1a + * Intel hybrid CPUs identification (e.g. Atom, Core) + */ + +struct leaf_0x1a_0 { + // eax + u32 core_native_model : 24, // This core's native model ID + core_type : 8; // This core's type + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1b + * Intel PCONFIG (Platform configuration) enumeration + */ + +struct leaf_0x1b_0 { + // eax + u32 pconfig_subleaf_type : 12, // CPUID 0x1b subleaf type + : 20; // Reserved + // ebx + u32 pconfig_target_id_x : 32; // A supported PCONFIG target ID + // ecx + u32 pconfig_target_id_y : 32; // A supported PCONFIG target ID + // edx + u32 pconfig_target_id_z : 32; // A supported PCONFIG target ID +}; + +/* + * Leaf 0x1c + * Intel LBR (Last Branch Record) enumeration + */ + +struct leaf_0x1c_0 { + // eax + u32 lbr_depth_8 : 1, // Max stack depth (number of LBR entries) =3D 8 + lbr_depth_16 : 1, // Max stack depth (number of LBR entries) =3D 16 + lbr_depth_24 : 1, // Max stack depth (number of LBR entries) =3D 24 + lbr_depth_32 : 1, // Max stack depth (number of LBR entries) =3D 32 + lbr_depth_40 : 1, // Max stack depth (number of LBR entries) =3D 40 + lbr_depth_48 : 1, // Max stack depth (number of LBR entries) =3D 48 + lbr_depth_56 : 1, // Max stack depth (number of LBR entries) =3D 56 + lbr_depth_64 : 1, // Max stack depth (number of LBR entries) =3D 64 + : 22, // Reserved + lbr_deep_c_reset : 1, // LBRs maybe cleared on MWAIT C-state > C1 + lbr_ip_is_lip : 1; // LBR IP contain Last IP, otherwise effective IP + // ebx + u32 lbr_cpl : 1, // CPL filtering (non-zero IA32_LBR_CTL[2:1]) suppor= ted + lbr_branch_filter : 1, // Branch filtering (non-zero IA32_LBR_CTL[22:1= 6]) supported + lbr_call_stack : 1, // Call-stack mode (IA32_LBR_CTL[3] =3D 1) suppor= ted + : 29; // Reserved + // ecx + u32 lbr_mispredict : 1, // Branch misprediction bit supported (IA32_LB= R_x_INFO[63]) + lbr_timed_lbr : 1, // Timed LBRs (CPU cycles since last LBR entry) su= pported + lbr_branch_type : 1, // Branch type field (IA32_LBR_INFO_x[59:56]) su= pported + : 13, // Reserved + lbr_events_gpc_bmp : 4, // LBR PMU-events logging support; bitmap for = first 4 GP (general-purpose) Counters + : 12; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1d + * Intel AMX (Advanced Matrix Extensions) tile information + */ + +struct leaf_0x1d_0 { + // eax + u32 amx_max_palette : 32; // Highest palette ID / subleaf ID + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x1d_1 { + // eax + u32 amx_palette_size : 16, // AMX palette total tiles size, in bytes + amx_tile_size : 16; // AMX single tile's size, in bytes + // ebx + u32 amx_tile_row_size : 16, // AMX tile single row's size, in bytes + amx_palette_nr_tiles : 16; // AMX palette number of tiles + // ecx + u32 amx_tile_nr_rows : 16, // AMX tile max number of rows + : 16; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1e + * Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration + */ + +struct leaf_0x1e_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 tmul_maxk : 8, // TMUL unit maximum height, K (rows or columns) + tmul_maxn : 16, // TMUL unit maximum SIMD dimension, N (column bytes) + : 8; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x1f + * Intel extended topology enumeration v2 + */ + +struct leaf_0x1f_0 { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 27; // Reserved + // ebx + u32 domain_lcpus_count : 16, // Logical CPUs count across all instances = of this domain + : 16; // Reserved + // ecx + u32 domain_level : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +/* + * Leaf 0x20 + * Intel HRESET (History Reset) enumeration + */ + +struct leaf_0x20_0 { + // eax + u32 hreset_nr_subleaves : 32; // CPUID 0x20 max subleaf + 1 + // ebx + u32 hreset_thread_director : 1, // HRESET of Intel thread director is s= upported + : 31; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x21 + * Intel TD (Trust Domain) guest execution environment enumeration + */ + +struct leaf_0x21_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 tdx_vendorid_0 : 32; // TDX vendor ID string bytes 0 - 3 + // ecx + u32 tdx_vendorid_2 : 32; // CPU vendor ID string bytes 8 - 11 + // edx + u32 tdx_vendorid_1 : 32; // CPU vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x23 + * Intel Architectural Performance Monitoring Extended (ArchPerfmonExt) + */ + +struct leaf_0x23_0 { + // eax + u32 : 1, // Reserved + subleaf_1_counters : 1, // Subleaf 1, PMU counters bitmaps, is valid + : 1, // Reserved + subleaf_3_events : 1, // Subleaf 3, PMU events bitmaps, is valid + : 28; // Reserved + // ebx + u32 unitmask2 : 1, // IA32_PERFEVTSELx MSRs UnitMask2 is supported + zbit : 1, // IA32_PERFEVTSELx MSRs Z-bit is supported + : 30; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_1 { + // eax + u32 pmu_gp_counters_bitmap : 32; // General-purpose PMU counters bitmap + // ebx + u32 pmu_f_counters_bitmap : 32; // Fixed PMU counters bitmap + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x23_3 { + // eax + u32 core_cycles_evt : 1, // Core cycles event supported + insn_retired_evt : 1, // Instructions retired event supported + ref_cycles_evt : 1, // Reference cycles event supported + llc_refs_evt : 1, // Last-level cache references event supported + llc_misses_evt : 1, // Last-level cache misses event supported + br_insn_ret_evt : 1, // Branch instruction retired event supported + br_mispr_evt : 1, // Branch mispredict retired event supported + td_slots_evt : 1, // Topdown slots event supported + td_backend_bound_evt : 1, // Topdown backend bound event supported + td_bad_spec_evt : 1, // Topdown bad speculation event supported + td_frontend_bound_evt : 1, // Topdown frontend bound event supported + td_retiring_evt : 1, // Topdown retiring event support + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x40000000 + * Maximum hypervisor standard leaf + hypervisor vendor string + */ + +struct leaf_0x40000000_0 { + // eax + u32 max_hyp_leaf : 32; // Maximum hypervisor standard leaf number + // ebx + u32 hypervisor_id_0 : 32; // Hypervisor ID string bytes 0 - 3 + // ecx + u32 hypervisor_id_1 : 32; // Hypervisor ID string bytes 4 - 7 + // edx + u32 hypervisor_id_2 : 32; // Hypervisor ID string bytes 8 - 11 +}; + +/* + * Leaf 0x80000000 + * Maximum extended leaf number + AMD/Transmeta CPU vendor string + */ + +struct leaf_0x80000000_0 { + // eax + u32 max_ext_leaf : 32; // Maximum extended CPUID leaf supported + // ebx + u32 cpu_vendorid_0 : 32; // Vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // Vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // Vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x80000001 + * Extended CPU feature identifiers + */ + +struct leaf_0x80000001_0 { + // eax + u32 e_stepping_id : 4, // Stepping ID + e_base_model : 4, // Base processor model + e_base_family : 4, // Base processor family + e_base_type : 2, // Base processor type (Transmeta) + : 2, // Reserved + e_ext_model : 4, // Extended processor model + e_ext_family : 8, // Extended processor family + : 4; // Reserved + // ebx + u32 brand_id : 16, // Brand ID + : 12, // Reserved + pkg_type : 4; // Package type + // ecx + u32 lahf_lm : 1, // LAHF and SAHF in 64-bit mode + cmp_legacy : 1, // Multi-processing legacy mode (No HT) + svm : 1, // Secure Virtual Machine + extapic : 1, // Extended APIC space + cr8_legacy : 1, // LOCK MOV CR0 means MOV CR8 + lzcnt_abm : 1, // LZCNT advanced bit manipulation + sse4a : 1, // SSE4A support + misaligned_sse : 1, // Misaligned SSE mode + _3dnow_prefetch : 1, // 3DNow PREFETCH/PREFETCHW support + osvw : 1, // OS visible workaround + ibs : 1, // Instruction based sampling + xop : 1, // XOP: extended operation (AVX instructions) + skinit : 1, // SKINIT/STGI support + wdt : 1, // Watchdog timer support + : 1, // Reserved + lwp : 1, // Lightweight profiling + fma4 : 1, // 4-operand FMA instruction + tce : 1, // Translation cache extension + : 1, // Reserved + nodeid_msr : 1, // NodeId MSR (0xc001100c) + : 1, // Reserved + tbm : 1, // Trailing bit manipulations + topoext : 1, // Topology Extensions (leaf 0x8000001d) + perfctr_core : 1, // Core performance counter extensions + perfctr_nb : 1, // NB/DF performance counter extensions + : 1, // Reserved + data_bp_ext : 1, // Data access breakpoint extension + perf_tsc : 1, // Performance time-stamp counter + perfctr_llc : 1, // LLC (L3) performance counter extensions + mwaitx : 1, // MWAITX/MONITORX support + addr_mask_ext : 1, // Breakpoint address mask extension (to bit 31) + : 1; // Reserved + // edx + u32 e_fpu : 1, // Floating-Point Unit on-chip (x87) + e_vme : 1, // Virtual-8086 Mode Extensions + e_de : 1, // Debugging Extensions + e_pse : 1, // Page Size Extension + e_tsc : 1, // Time Stamp Counter + e_msr : 1, // Model-Specific Registers (RDMSR and WRMSR support) + pae : 1, // Physical Address Extensions + mce : 1, // Machine Check Exception + cx8 : 1, // CMPXCHG8B instruction + apic : 1, // APIC on-chip + : 1, // Reserved + syscall : 1, // SYSCALL and SYSRET instructions + mtrr : 1, // Memory Type Range Registers + pge : 1, // Page Global Extensions + mca : 1, // Machine Check Architecture + cmov : 1, // Conditional Move Instruction + pat : 1, // Page Attribute Table + pse36 : 1, // Page Size Extension (36-bit) + : 1, // Reserved + obsolete_mp_bit : 1, // Out-of-spec AMD Multiprocessing bit + nx : 1, // No-execute page protection + : 1, // Reserved + mmxext : 1, // AMD MMX extensions + e_mmx : 1, // MMX instructions + e_fxsr : 1, // FXSAVE and FXRSTOR instructions + fxsr_opt : 1, // FXSAVE and FXRSTOR optimizations + page1gb : 1, // 1-GB large page support + rdtscp : 1, // RDTSCP instruction + : 1, // Reserved + lm : 1, // Long mode (x86-64, 64-bit support) + _3dnowext : 1, // AMD 3DNow extensions + _3dnow : 1; // 3DNow instructions +}; + +/* + * Leaf 0x80000002 + * CPU brand ID string, bytes 0 - 15 + */ + +struct leaf_0x80000002_0 { + // eax + u32 cpu_brandid_0 : 32; // CPU brand ID string, bytes 0 - 3 + // ebx + u32 cpu_brandid_1 : 32; // CPU brand ID string, bytes 4 - 7 + // ecx + u32 cpu_brandid_2 : 32; // CPU brand ID string, bytes 8 - 11 + // edx + u32 cpu_brandid_3 : 32; // CPU brand ID string, bytes 12 - 15 +}; + +/* + * Leaf 0x80000003 + * CPU brand ID string, bytes 16 - 31 + */ + +struct leaf_0x80000003_0 { + // eax + u32 cpu_brandid_4 : 32; // CPU brand ID string bytes, 16 - 19 + // ebx + u32 cpu_brandid_5 : 32; // CPU brand ID string bytes, 20 - 23 + // ecx + u32 cpu_brandid_6 : 32; // CPU brand ID string bytes, 24 - 27 + // edx + u32 cpu_brandid_7 : 32; // CPU brand ID string bytes, 28 - 31 +}; + +/* + * Leaf 0x80000004 + * CPU brand ID string, bytes 32 - 47 + */ + +struct leaf_0x80000004_0 { + // eax + u32 cpu_brandid_8 : 32; // CPU brand ID string, bytes 32 - 35 + // ebx + u32 cpu_brandid_9 : 32; // CPU brand ID string, bytes 36 - 39 + // ecx + u32 cpu_brandid_10 : 32; // CPU brand ID string, bytes 40 - 43 + // edx + u32 cpu_brandid_11 : 32; // CPU brand ID string, bytes 44 - 47 +}; + +/* + * Leaf 0x80000005 + * AMD/Transmeta L1 cache and L1 TLB enumeration + */ + +struct leaf_0x80000005_0 { + // eax + u32 l1_itlb_2m_4m_nentries : 8, // L1 ITLB #entries, 2M and 4M pages + l1_itlb_2m_4m_assoc : 8, // L1 ITLB associativity, 2M and 4M pages + l1_dtlb_2m_4m_nentries : 8, // L1 DTLB #entries, 2M and 4M pages + l1_dtlb_2m_4m_assoc : 8; // L1 DTLB associativity, 2M and 4M pages + // ebx + u32 l1_itlb_4k_nentries : 8, // L1 ITLB #entries, 4K pages + l1_itlb_4k_assoc : 8, // L1 ITLB associativity, 4K pages + l1_dtlb_4k_nentries : 8, // L1 DTLB #entries, 4K pages + l1_dtlb_4k_assoc : 8; // L1 DTLB associativity, 4K pages + // ecx + u32 l1_dcache_line_size : 8, // L1 dcache line size, in bytes + l1_dcache_nlines : 8, // L1 dcache lines per tag + l1_dcache_assoc : 8, // L1 dcache associativity + l1_dcache_size_kb : 8; // L1 dcache size, in KB + // edx + u32 l1_icache_line_size : 8, // L1 icache line size, in bytes + l1_icache_nlines : 8, // L1 icache lines per tag + l1_icache_assoc : 8, // L1 icache associativity + l1_icache_size_kb : 8; // L1 icache size, in KB +}; + +/* + * Leaf 0x80000006 + * (Mostly AMD) L2 TLB, L2 cache, and L3 cache enumeration + */ + +struct leaf_0x80000006_0 { + // eax + u32 l2_itlb_2m_4m_nentries : 12, // L2 iTLB #entries, 2M and 4M pages + l2_itlb_2m_4m_assoc : 4, // L2 iTLB associativity, 2M and 4M pages + l2_dtlb_2m_4m_nentries : 12, // L2 dTLB #entries, 2M and 4M pages + l2_dtlb_2m_4m_assoc : 4; // L2 dTLB associativity, 2M and 4M pages + // ebx + u32 l2_itlb_4k_nentries : 12, // L2 iTLB #entries, 4K pages + l2_itlb_4k_assoc : 4, // L2 iTLB associativity, 4K pages + l2_dtlb_4k_nentries : 12, // L2 dTLB #entries, 4K pages + l2_dtlb_4k_assoc : 4; // L2 dTLB associativity, 4K pages + // ecx + u32 l2_line_size : 8, // L2 cache line size, in bytes + l2_nlines : 4, // L2 cache number of lines per tag + l2_assoc : 4, // L2 cache associativity + l2_size_kb : 16; // L2 cache size, in KB + // edx + u32 l3_line_size : 8, // L3 cache line size, in bytes + l3_nlines : 4, // L3 cache number of lines per tag + l3_assoc : 4, // L3 cache associativity + : 2, // Reserved + l3_size_range : 14; // L3 cache size range +}; + +/* + * Leaf 0x80000007 + * CPU power management (mostly AMD) and AMD RAS enumeration + */ + +struct leaf_0x80000007_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 mca_overflow_recovery : 1, // MCA overflow conditions not fatal + succor : 1, // Software containment of uncorrectable errors + hw_assert : 1, // Hardware assert MSRs + scalable_mca : 1, // Scalable MCA (MCAX MSRs) + : 28; // Reserved + // ecx + u32 cpu_pwr_sample_ratio : 32; // CPU power sample time ratio + // edx + u32 digital_temp : 1, // Digital temperature sensor + powernow_freq_id : 1, // PowerNOW! frequency scaling + powernow_volt_id : 1, // PowerNOW! voltage scaling + thermal_trip : 1, // THERMTRIP (Thermal Trip) + hw_thermal_control : 1, // Hardware thermal control + sw_thermal_control : 1, // Software thermal control + _100mhz_steps : 1, // 100 MHz multiplier control + hw_pstate : 1, // Hardware P-state control + constant_tsc : 1, // TSC ticks at constant rate across all P and C st= ates + core_perf_boost : 1, // Core performance boost + eff_freq_ro : 1, // Read-only effective frequency interface + proc_feedback : 1, // Processor feedback interface (deprecated) + proc_power_reporting : 1, // Processor power reporting interface + connected_standby : 1, // CPU Connected Standby support + rapl_interface : 1, // Runtime Average Power Limit interface + : 17; // Reserved +}; + +/* + * Leaf 0x80000008 + * CPU capacity parameters and extended feature flags (mostly AMD) + */ + +struct leaf_0x80000008_0 { + // eax + u32 phys_addr_bits : 8, // Max physical address bits + virt_addr_bits : 8, // Max virtual address bits + guest_phys_addr_bits : 8, // Max nested-paging guest physical address = bits + : 8; // Reserved + // ebx + u32 clzero : 1, // CLZERO supported + insn_retired_perf : 1, // Instruction retired counter MSR + xsave_err_ptr : 1, // XSAVE/XRSTOR always saves/restores FPU error po= inters + invlpgb : 1, // INVLPGB broadcasts a TLB invalidate to all threads + rdpru : 1, // RDPRU (Read Processor Register at User level) supported + : 1, // Reserved + mba : 1, // Memory Bandwidth Allocation (AMD bit) + : 1, // Reserved + mcommit : 1, // MCOMMIT (Memory commit) supported + wbnoinvd : 1, // WBNOINVD supported + : 2, // Reserved + ibpb : 1, // Indirect Branch Prediction Barrier + wbinvd_int : 1, // Interruptible WBINVD/WBNOINVD + ibrs : 1, // Indirect Branch Restricted Speculation + stibp : 1, // Single Thread Indirect Branch Prediction mode + ibrs_always_on : 1, // IBRS always-on preferred + stibp_always_on : 1, // STIBP always-on preferred + ibrs_fast : 1, // IBRS is preferred over software solution + ibrs_same_mode : 1, // IBRS provides same mode protection + no_efer_lmsle : 1, // EFER[LMSLE] bit (Long-Mode Segment Limit Enable= ) unsupported + tlb_flush_nested : 1, // INVLPGB RAX[5] bit can be set (nested transla= tions) + : 1, // Reserved + amd_ppin : 1, // Protected Processor Inventory Number + amd_ssbd : 1, // Speculative Store Bypass Disable + virt_ssbd : 1, // virtualized SSBD (Speculative Store Bypass Disable) + amd_ssb_no : 1, // SSBD is not needed (fixed in hardware) + cppc : 1, // Collaborative Processor Performance Control + amd_psfd : 1, // Predictive Store Forward Disable + btc_no : 1, // CPU not affected by Branch Type Confusion + ibpb_ret : 1, // IBPB clears RSB/RAS too + branch_sampling : 1; // Branch Sampling supported + // ecx + u32 cpu_nthreads : 8, // Number of physical threads - 1 + : 4, // Reserved + apicid_coreid_len : 4, // Number of thread core ID bits (shift) in API= C ID + perf_tsc_len : 2, // Performance time-stamp counter size + : 14; // Reserved + // edx + u32 invlpgb_max_pages : 16, // INVLPGB maximum page count + rdpru_max_reg_id : 16; // RDPRU max register ID (ECX input) +}; + +/* + * Leaf 0x8000000a + * AMD SVM (Secure Virtual Machine) enumeration + */ + +struct leaf_0x8000000a_0 { + // eax + u32 svm_version : 8, // SVM revision number + : 24; // Reserved + // ebx + u32 svm_nasid : 32; // Number of address space identifiers (ASID) + // ecx + u32 : 32; // Reserved + // edx + u32 nested_pt : 1, // Nested paging + lbr_virt : 1, // LBR virtualization + svm_lock : 1, // SVM lock + nrip_save : 1, // NRIP save support on #VMEXIT + tsc_rate_msr : 1, // MSR based TSC rate control + vmcb_clean : 1, // VMCB clean bits support + flush_by_asid : 1, // Flush by ASID + Extended VMCB TLB_Control + decode_assists : 1, // Decode Assists support + : 2, // Reserved + pause_filter : 1, // Pause intercept filter + : 1, // Reserved + pf_threshold : 1, // Pause filter threshold + avic : 1, // Advanced virtual interrupt controller + : 1, // Reserved + v_vmsave_vmload : 1, // Virtual VMSAVE/VMLOAD (nested virtualization) + v_gif : 1, // Virtualize the Global Interrupt Flag + gmet : 1, // Guest mode execution trap + x2avic : 1, // Virtual x2APIC + sss_check : 1, // Supervisor Shadow Stack restrictions + v_spec_ctrl : 1, // Virtual SPEC_CTRL + ro_gpt : 1, // Read-Only guest page table support + : 1, // Reserved + h_mce_override : 1, // Host MCE override + tlbsync_int : 1, // TLBSYNC intercept + INVLPGB/TLBSYNC in VMCB + nmi_virt : 1, // NMI virtualization + ibs_virt : 1, // IBS Virtualization + ext_lvt_off_chg : 1, // Extended LVT offset fault change + svme_addr_chk : 1, // Guest SVME address check + : 3; // Reserved +}; + +/* + * Leaf 0x80000019 + * AMD TLB 1G-pages enumeration + */ + +struct leaf_0x80000019_0 { + // eax + u32 l1_itlb_1g_nentries : 12, // L1 iTLB #entries, 1G pages + l1_itlb_1g_assoc : 4, // L1 iTLB associativity, 1G pages + l1_dtlb_1g_nentries : 12, // L1 dTLB #entries, 1G pages + l1_dtlb_1g_assoc : 4; // L1 dTLB associativity, 1G pages + // ebx + u32 l2_itlb_1g_nentries : 12, // L2 iTLB #entries, 1G pages + l2_itlb_1g_assoc : 4, // L2 iTLB associativity, 1G pages + l2_dtlb_1g_nentries : 12, // L2 dTLB #entries, 1G pages + l2_dtlb_1g_assoc : 4; // L2 dTLB associativity, 1G pages + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001a + * AMD instruction optimizations enumeration + */ + +struct leaf_0x8000001a_0 { + // eax + u32 fp_128 : 1, // Internal FP/SIMD exec data path is 128-bits wide + movu_preferred : 1, // SSE: MOVU* better than MOVL*/MOVH* + fp_256 : 1, // internal FP/SSE exec data path is 256-bits wide + : 29; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001b + * AMD IBS (Instruction-Based Sampling) enumeration + */ + +struct leaf_0x8000001b_0 { + // eax + u32 ibs_flags_valid : 1, // IBS feature flags valid + ibs_fetch_sampling : 1, // IBS fetch sampling supported + ibs_op_sampling : 1, // IBS execution sampling supported + ibs_rdwr_op_counter : 1, // IBS read/write of op counter supported + ibs_op_count : 1, // IBS OP counting mode supported + ibs_branch_target : 1, // IBS branch target address reporting supported + ibs_op_counters_ext : 1, // IBS IbsOpCurCnt/IbsOpMaxCnt extend by 7 bi= ts + ibs_rip_invalid_chk : 1, // IBS invalid RIP indication supported + ibs_op_branch_fuse : 1, // IBS fused branch micro-op indication suppor= ted + ibs_fetch_ctl_ext : 1, // IBS Fetch Control Extended MSR (0xc001103c) = supported + ibs_op_data_4 : 1, // IBS op data 4 MSR supported + ibs_l3_miss_filter : 1, // IBS L3-miss filtering supported (Zen4+) + : 20; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001c + * AMD LWP (Lightweight Profiling) + */ + +struct leaf_0x8000001c_0 { + // eax + u32 os_lwp_avail : 1, // LWP is available to application programs (sup= ported by OS) + os_lpwval : 1, // LWPVAL instruction is supported by OS + os_lwp_ire : 1, // Instructions Retired Event is supported by OS + os_lwp_bre : 1, // Branch Retired Event is supported by OS + os_lwp_dme : 1, // Dcache Miss Event is supported by OS + os_lwp_cnh : 1, // CPU Clocks Not Halted event is supported by OS + os_lwp_rnh : 1, // CPU Reference clocks Not Halted event is supported= by OS + : 22, // Reserved + os_lwp_cont : 1, // LWP sampling in continuous mode is supported by OS + os_lwp_ptsc : 1, // Performance Time Stamp Counter in event records i= s supported by OS + os_lwp_int : 1; // Interrupt on threshold overflow is supported by OS + // ebx + u32 lwp_lwpcb_sz : 8, // LWP Control Block size, in quadwords + lwp_event_sz : 8, // LWP event record size, in bytes + lwp_max_events : 8, // LWP max supported EventID value (EventID 255 n= ot included) + lwp_event_offset : 8; // LWP events area offset in the LWP Control Blo= ck + // ecx + u32 lwp_latency_max : 5, // Number of bits in cache latency counters (= 10 to 31) + lwp_data_adddr : 1, // Cache miss events report the data address of t= he reference + lwp_latency_rnd : 3, // Amount by which cache latency is rounded + lwp_version : 7, // LWP implementation version + lwp_buf_min_sz : 8, // LWP event ring buffer min size, in units of 32= event records + : 4, // Reserved + lwp_branch_predict : 1, // Branches Retired events can be filtered + lwp_ip_filtering : 1, // IP filtering (IPI, IPF, BaseIP, and LimitIP @= LWPCP) supported + lwp_cache_levels : 1, // Cache-related events can be filtered by cache= level + lwp_cache_latency : 1; // Cache-related events can be filtered by late= ncy + // edx + u32 hw_lwp_avail : 1, // LWP is available in hardware + hw_lpwval : 1, // LWPVAL instruction is available in hardware + hw_lwp_ire : 1, // Instructions Retired Event is available in hardware + hw_lwp_bre : 1, // Branch Retired Event is available in hardware + hw_lwp_dme : 1, // Dcache Miss Event is available in hardware + hw_lwp_cnh : 1, // Clocks Not Halted event is available in hardware + hw_lwp_rnh : 1, // Reference clocks Not Halted event is available in = hardware + : 22, // Reserved + hw_lwp_cont : 1, // LWP sampling in continuous mode is available in h= ardware + hw_lwp_ptsc : 1, // Performance Time Stamp Counter in event records i= s available in hardware + hw_lwp_int : 1; // Interrupt on threshold overflow is available in ha= rdware +}; + +/* + * Leaf 0x8000001d + * AMD deterministic cache parameters + */ + +struct leaf_0x8000001d_0 { + // eax + u32 cache_type : 5, // Cache type field + cache_level : 3, // Cache level (1-based) + cache_self_init : 1, // Self-initializing cache level + fully_associative : 1, // Fully-associative cache + : 4, // Reserved + num_threads_sharing : 12, // Number of logical CPUs sharing cache + : 6; // Reserved + // ebx + u32 cache_linesize : 12, // System coherency line size (0-based) + cache_npartitions : 10, // Physical line partitions (0-based) + cache_nways : 10; // Ways of associativity (0-based) + // ecx + u32 cache_nsets : 31, // Cache number of sets (0-based) + : 1; // Reserved + // edx + u32 wbinvd_rll_no_guarantee : 1, // WBINVD/INVD not guaranteed for Remo= te Lower-Level caches + ll_inclusive : 1, // Cache is inclusive of Lower-Level caches + : 30; // Reserved +}; + +/* + * Leaf 0x8000001e + * AMD CPU topology enumeration + */ + +struct leaf_0x8000001e_0 { + // eax + u32 ext_apic_id : 32; // Extended APIC ID + // ebx + u32 core_id : 8, // Unique per-socket logical core unit ID + core_nthreas : 8, // #Threads per core (zero-based) + : 16; // Reserved + // ecx + u32 node_id : 8, // Node (die) ID of invoking logical CPU + nnodes_per_socket : 3, // #nodes in invoking logical CPU's package/soc= ket + : 21; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x8000001f + * AMD encrypted memory capabilities enumeration (SME/SEV) + */ + +struct leaf_0x8000001f_0 { + // eax + u32 sme : 1, // Secure Memory Encryption supported + sev : 1, // Secure Encrypted Virtualization supported + vm_page_flush : 1, // VM Page Flush MSR (0xc001011e) available + sev_encrypted_state : 1, // SEV Encrypted State supported + sev_nested_paging : 1, // SEV secure nested paging supported + vm_permission_levels : 1, // VMPL supported + rpmquery : 1, // RPMQUERY instruction supported + vmpl_sss : 1, // VMPL supervisor shadow stack supported + secure_tsc : 1, // Secure TSC supported + virt_tsc_aux : 1, // Hardware virtualizes TSC_AUX + sme_coherent : 1, // Cache coherency is enforced across encryption do= mains + req_64bit_hypervisor : 1, // SEV guest mandates 64-bit hypervisor + restricted_injection : 1, // Restricted Injection supported + alternate_injection : 1, // Alternate Injection supported + debug_swap : 1, // SEV-ES: full debug state swap is supported + disallow_host_ibs : 1, // SEV-ES: Disallowing IBS use by the host is s= upported + virt_transparent_enc : 1, // Virtual Transparent Encryption + vmgexit_paremeter : 1, // VmgexitParameter is supported in SEV_FEATURES + virt_tom_msr : 1, // Virtual TOM MSR is supported + virt_ibs : 1, // IBS state virtualization is supported for SEV-ES gue= sts + : 4, // Reserved + vmsa_reg_protection : 1, // VMSA register protection is supported + smt_protection : 1, // SMT protection is supported + : 2, // Reserved + svsm_page_msr : 1, // SVSM communication page MSR (0xc001f000) is sup= ported + nested_virt_snp_msr : 1, // VIRT_RMPUPDATE/VIRT_PSMASH MSRs are suppor= ted + : 2; // Reserved + // ebx + u32 pte_cbit_pos : 6, // PTE bit number used to enable memory encrypti= on + phys_addr_reduction_nbits : 6, // Reduction of phys address space when = encryption is enabled, in bits + vmpl_count : 4, // Number of VM permission levels (VMPL) supported + : 16; // Reserved + // ecx + u32 enc_guests_max : 32; // Max supported number of simultaneous encryp= ted guests + // edx + u32 min_sev_asid_no_sev_es : 32; // Minimum ASID for SEV-enabled SEV-ES-= disabled guest +}; + +/* + * Leaf 0x80000020 + * AMD Platform QoS extended feature IDs + */ + +struct leaf_0x80000020_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 1, // Reserved + mba : 1, // Memory Bandwidth Allocation support + smba : 1, // Slow Memory Bandwidth Allocation support + bmec : 1, // Bandwidth Monitoring Event Configuration support + l3rr : 1, // L3 Range Reservation support + abmc : 1, // Assignable Bandwidth Monitoring Counters + sdciae : 1, // Smart Data Cache Injection (SDCI) Allocation Enforcem= ent + : 25; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +struct leaf_0x80000020_1 { + // eax + u32 mba_limit_len : 32; // MBA enforcement limit size + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 mba_cos_max : 32; // MBA max Class of Service number (zero-based) +}; + +struct leaf_0x80000020_2 { + // eax + u32 smba_limit_len : 32; // SMBA enforcement limit size + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 smba_cos_max : 32; // SMBA max Class of Service number (zero-based) +}; + +struct leaf_0x80000020_3 { + // eax + u32 : 32; // Reserved + // ebx + u32 bmec_num_events : 8, // BMEC number of bandwidth events available + : 24; // Reserved + // ecx + u32 bmec_local_reads : 1, // Local NUMA reads can be tracked + bmec_remote_reads : 1, // Remote NUMA reads can be tracked + bmec_local_nontemp_wr : 1, // Local NUMA non-temporal writes can be tr= acked + bmec_remote_nontemp_wr : 1, // Remote NUMA non-temporal writes can be = tracked + bmec_local_slow_mem_rd : 1, // Local NUMA slow-memory reads can be tra= cked + bmec_remote_slow_mem_rd : 1, // Remote NUMA slow-memory reads can be t= racked + bmec_all_dirty_victims : 1, // Dirty QoS victims to all types of memor= y can be tracked + : 25; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000021 + * AMD extended features enumeration 2 + */ + +struct leaf_0x80000021_0 { + // eax + u32 no_nested_data_bp : 1, // No nested data breakpoints + fsgs_non_serializing : 1, // WRMSR to {FS,GS,KERNEL_GS}_BASE is non-se= rializing + lfence_serializing : 1, // LFENCE always serializing / synchronizes RD= TSC + smm_page_cfg_lock : 1, // SMM paging configuration lock + : 2, // Reserved + null_sel_clr_base : 1, // Null selector clears base + upper_addr_ignore : 1, // EFER MSR Upper Address Ignore + auto_ibrs : 1, // EFER MSR Automatic IBRS + no_smm_ctl_msr : 1, // SMM_CTL MSR (0xc0010116) is not available + fsrs : 1, // Fast Short Rep STOSB + fsrc : 1, // Fast Short Rep CMPSB + : 1, // Reserved + prefetch_ctl_msr : 1, // Prefetch control MSR is available + : 2, // Reserved + opcode_reclaim : 1, // Reserves opcode space + user_cpuid_disable : 1, // #GP when executing CPUID at CPL > 0 is supp= orted + epsf : 1, // Enhanced Predictive Store Forwarding + : 3, // Reserved + wl_feedback : 1, // Workload-based heuristic feedback to OS + : 1, // Reserved + eraps : 1, // Enhanced Return Address Predictor Security + : 2, // Reserved + sbpb : 1, // Selective Branch Predictor Barrier + ibpb_brtype : 1, // Branch predictions flushed from CPU branch predic= tor + srso_no : 1, // CPU is not subject to the SRSO vulnerability + srso_uk_no : 1, // CPU is not vulnerable to SRSO at user-kernel bound= ary + srso_msr_fix : 1; // Software may use MSR BP_CFG[BpSpecReduce] to mit= igate SRSO + // ebx + u32 microcode_patch_size : 16, // Size of microcode patch, in 16-byte un= its + rap_size : 8, // Return Address Predictor size + : 8; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000022 + * AMD Performance Monitoring v2 enumeration + */ + +struct leaf_0x80000022_0 { + // eax + u32 perfmon_v2 : 1, // Performance monitoring v2 supported + lbr_v2 : 1, // Last Branch Record v2 extensions (LBR Stack) + lbr_pmc_freeze : 1, // Freezing core performance counters / LBR Stack= supported + : 29; // Reserved + // ebx + u32 n_pmc_core : 4, // Number of core performance counters + lbr_v2_stack_size : 6, // Number of available LBR stack entries + n_pmc_northbridge : 6, // Number of available northbridge (data fabric= ) performance counters + n_pmc_umc : 6, // Number of available UMC performance counters + : 10; // Reserved + // ecx + u32 active_umc_bitmask : 32; // Active UMCs bitmask + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000023 + * AMD Secure Multi-key Encryption enumeration + */ + +struct leaf_0x80000023_0 { + // eax + u32 mem_hmk_mode : 1, // MEM-HMK encryption mode is supported + : 31; // Reserved + // ebx + u32 mem_hmk_avail_keys : 16, // MEM-HMK mode: total number of available = encryption keys + : 16; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80000026 + * AMD extended topology enumeration v2 + */ + +struct leaf_0x80000026_0 { + // eax + u32 x2apic_id_shift : 5, // Bit width of this level (previous levels i= nclusive) + : 24, // Reserved + core_has_pwreff_ranking : 1, // This core has a power efficiency ranki= ng + domain_has_hybrid_cores : 1, // This domain level has hybrid (E, P) co= res + domain_core_count_asymm : 1; // The 'Core' domain has asymmetric cores= count + // ebx + u32 domain_lcpus_count : 16, // Number of logical CPUs at this domain in= stance + core_pwreff_ranking : 8, // This core's static power efficiency ranking + core_native_model_id : 4, // This core's native model ID + core_type : 4; // This core's type + // ecx + u32 domain_level : 8, // This domain level (subleaf ID) + domain_type : 8, // This domain type + : 16; // Reserved + // edx + u32 x2apic_id : 32; // x2APIC ID of current logical CPU +}; + +/* + * Leaf 0x80860000 + * Maximum Transmeta leaf number + CPU vendor ID string + */ + +struct leaf_0x80860000_0 { + // eax + u32 max_tra_leaf : 32; // Maximum supported Transmeta leaf number + // ebx + u32 cpu_vendorid_0 : 32; // Transmeta Vendor ID string bytes 0 - 3 + // ecx + u32 cpu_vendorid_2 : 32; // Transmeta Vendor ID string bytes 8 - 11 + // edx + u32 cpu_vendorid_1 : 32; // Transmeta Vendor ID string bytes 4 - 7 +}; + +/* + * Leaf 0x80860001 + * Transmeta extended CPU information + */ + +struct leaf_0x80860001_0 { + // eax + u32 stepping : 4, // Stepping ID + base_model : 4, // Base CPU model ID + base_family_id : 4, // Base CPU family ID + cpu_type : 2, // CPU type + : 18; // Reserved + // ebx + u32 cpu_rev_mask_minor : 8, // CPU revision ID, mask minor + cpu_rev_mask_major : 8, // CPU revision ID, mask major + cpu_rev_minor : 8, // CPU revision ID, minor + cpu_rev_major : 8; // CPU revision ID, major + // ecx + u32 cpu_base_mhz : 32; // CPU nominal frequency, in MHz + // edx + u32 recovery : 1, // Recovery CMS is active (after bad flush) + longrun : 1, // LongRun power management capabilities + : 1, // Reserved + lrti : 1, // LongRun Table Interface + : 28; // Reserved +}; + +/* + * Leaf 0x80860002 + * Transmeta Code Morphing Software (CMS) enumeration + */ + +struct leaf_0x80860002_0 { + // eax + u32 cpu_rev_id : 32; // CPU revision ID + // ebx + u32 cms_rev_mask_2 : 8, // CMS revision ID, mask component 2 + cms_rev_mask_1 : 8, // CMS revision ID, mask component 1 + cms_rev_minor : 8, // CMS revision ID, minor + cms_rev_major : 8; // CMS revision ID, major + // ecx + u32 cms_rev_mask_3 : 32; // CMS revision ID, mask component 3 + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0x80860003 + * Transmeta CPU information string, bytes 0 - 15 + */ + +struct leaf_0x80860003_0 { + // eax + u32 cpu_info_0 : 32; // CPU info string bytes 0 - 3 + // ebx + u32 cpu_info_1 : 32; // CPU info string bytes 4 - 7 + // ecx + u32 cpu_info_2 : 32; // CPU info string bytes 8 - 11 + // edx + u32 cpu_info_3 : 32; // CPU info string bytes 12 - 15 +}; + +/* + * Leaf 0x80860004 + * Transmeta CPU information string, bytes 16 - 31 + */ + +struct leaf_0x80860004_0 { + // eax + u32 cpu_info_4 : 32; // CPU info string bytes 16 - 19 + // ebx + u32 cpu_info_5 : 32; // CPU info string bytes 20 - 23 + // ecx + u32 cpu_info_6 : 32; // CPU info string bytes 24 - 27 + // edx + u32 cpu_info_7 : 32; // CPU info string bytes 28 - 31 +}; + +/* + * Leaf 0x80860005 + * Transmeta CPU information string, bytes 32 - 47 + */ + +struct leaf_0x80860005_0 { + // eax + u32 cpu_info_8 : 32; // CPU info string bytes 32 - 35 + // ebx + u32 cpu_info_9 : 32; // CPU info string bytes 36 - 39 + // ecx + u32 cpu_info_10 : 32; // CPU info string bytes 40 - 43 + // edx + u32 cpu_info_11 : 32; // CPU info string bytes 44 - 47 +}; + +/* + * Leaf 0x80860006 + * Transmeta CPU information string, bytes 48 - 63 + */ + +struct leaf_0x80860006_0 { + // eax + u32 cpu_info_12 : 32; // CPU info string bytes 48 - 51 + // ebx + u32 cpu_info_13 : 32; // CPU info string bytes 52 - 55 + // ecx + u32 cpu_info_14 : 32; // CPU info string bytes 56 - 59 + // edx + u32 cpu_info_15 : 32; // CPU info string bytes 60 - 63 +}; + +/* + * Leaf 0x80860007 + * Transmeta live CPU information + */ + +struct leaf_0x80860007_0 { + // eax + u32 cpu_cur_mhz : 32; // Current CPU frequency, in MHz + // ebx + u32 cpu_cur_voltage : 32; // Current CPU voltage, in millivolts + // ecx + u32 cpu_cur_perf_pctg : 32; // Current CPU performance percentage, 0 - 1= 00 + // edx + u32 cpu_cur_gate_delay : 32; // Current CPU gate delay, in femtoseconds +}; + +/* + * Leaf 0xc0000000 + * Maximum Centaur/Zhaoxin leaf number + */ + +struct leaf_0xc0000000_0 { + // eax + u32 max_cntr_leaf : 32; // Maximum Centaur/Zhaoxin leaf number + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 : 32; // Reserved +}; + +/* + * Leaf 0xc0000001 + * Centaur/Zhaoxin extended CPU features + */ + +struct leaf_0xc0000001_0 { + // eax + u32 : 32; // Reserved + // ebx + u32 : 32; // Reserved + // ecx + u32 : 32; // Reserved + // edx + u32 ccs_sm2 : 1, // CCS SM2 instructions + ccs_sm2_en : 1, // CCS SM2 enabled + rng : 1, // Random Number Generator + rng_en : 1, // RNG enabled + ccs_sm3_sm4 : 1, // CCS SM3 and SM4 instructions + ccs_sm3_sm4_en : 1, // CCS SM3/SM4 enabled + ace : 1, // Advanced Cryptography Engine + ace_en : 1, // ACE enabled + ace2 : 1, // Advanced Cryptography Engine v2 + ace2_en : 1, // ACE v2 enabled + phe : 1, // PadLock Hash Engine + phe_en : 1, // PHE enabled + pmm : 1, // PadLock Montgomery Multiplier + pmm_en : 1, // PMM enabled + : 2, // Reserved + parallax : 1, // Parallax auto adjust processor voltage + parallax_en : 1, // Parallax enabled + : 2, // Reserved + tm3 : 1, // Thermal Monitor v3 + tm3_en : 1, // TM v3 enabled + : 3, // Reserved + phe2 : 1, // PadLock Hash Engine v2 (SHA384/SHA512) + phe2_en : 1, // PHE v2 enabled + rsa : 1, // RSA instructions (XMODEXP/MONTMUL2) + rsa_en : 1, // RSA instructions enabled + : 3; // Reserved +}; + +#endif /* _ASM_X86_CPUID_LEAVES */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BF9C027C14E for ; Thu, 5 Jun 2025 19:24:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151466; cv=none; b=ha2Aty56eEezFHxWOANNJan4/aBb4tLuirEKwY5db2Hr4wUMOPbgpM9CF4Y07bY46M1QBAxzQIVa7QavtOvJq0ahaGQRl5ac+xHnO8hoc/E1HlqJPp8B/+nCsjgZWvjfUO3sGe7ywSP7QGYY/3gQFc5GYwlidVUCJ7hVobt7W+A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151466; c=relaxed/simple; bh=7qlYrd8ADkiSEKc+gzHN8gdQbL+o5MjgLp2U/du+a8Y=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=D/fNAodCXUsG/kRecwHXcRJlHcrGEc+a+WULni/fFj4TYb19+8mxF4tolbrdswm/nq3kkbdRViJGliFvgcryLoyMrSOmgGf3jktIu9H1KKNCTM+Z7i+EJYDlTlgIaWfCRXl/cjzAxWu0RvpB9yZhbxPC5ARO7Ol3JvgsCp8XSTw= ARC-Authentication-Results: i=1; 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Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 04/27] x86/cpuid: Introduce a centralized CPUID data model Date: Thu, 5 Jun 2025 21:23:33 +0200 Message-ID: <20250605192356.82250-5-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable ** Context The x86-cpuid-db project generates a C header file with full C99 bitfield listings for all known CPUID leaf/subleaf query outputs. That header is now merged by parent commits at , and is in the form: struct leaf_0x0_0 { /* CPUID(0x0), subleaf 0, C99 bitfields */ }; ... struct leaf_0x7_0 { /* CPUID(0x7), subleaf 0, C99 bitfields */ }; struct leaf_0x7_1 { /* CPUID(0x7), subleaf 1, C99 bitfields */ }; ... ** Goal Introduce a structured, size-efficient, per-CPU, CPUID data repository. Use the x86-cpuid-db auto-generated data types, and custom CPUID leaf parsers, to build that repository. Given a leaf, subleaf, and index, provide direct memory access to the parsed and cached per-CPU CPUID output. ** Long-term goal Remove the need for drivers and other areas in the kernel to invoke direct CPUID queries. Only one place in the kernel should be allowed to use the CPUID instruction: the CPUID parser code. ** Implementation Introduce CPUID_LEAF() to build a compact CPUID storage layout in the form: struct leaf_0x0_0 leaf_0x0_0[1]; struct leaf_query_info leaf_0x0_0_info; struct leaf_0x1_0 leaf_0x1_0[1]; struct leaf_query_info leaf_0x0_0_info; struct leaf_0x4_0 leaf_0x4_0[8]; struct leaf_query_info leaf_0x4_0_info; ... where each CPUID leaf 0xN subleaf M query stores its output at the designated leaf_0xN_M[] array and has an associated "CPUID query info" structure. Introduce 'struct cpuid_leaves' to group all the parsed CPUID outputs and their metadata =E2=80=93in the layout above=E2=80=93 in one structure. Def= ine a 'struct cpuid_table' to wrap it, so that global per-table CPUID data can be added later. Embed that 'struct cpuid_table' inside 'struct cpuinfo_x86' to ensure early-boot and per-CPU access through the current CPU's capability structure. Given the data layout above, and assuming a CPU capability structure 'c', a macro can access CPUID(0x7) subleaf 0 parsed query output using the compile time tokenization below: const struct leaf_0x7_0 *l7_0; l7_0 =3D cpuid_subleaf(c, 0x7, 0); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * * &c.cpuid.leaf_0x7_0[0] Similarly, CPUID(0x7) subleaf 1 output can be accessed using the CPP tokenization: const struct leaf_0x7_1 *l7_1; l7_1 =3D cpuid_subleaf(c, 0x7, 1); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94= =80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * * &c.cpuid.leaf_0x7_1[0] which all translate to a single assembly instruction offset calculation. Use an array of CPUID output storage entries for each leaf/subleaf combination to accommodate leaves which produce the same output format for a large subleaf range. This is typical for CPUID leaves enumerating hierarchical objects; e.g. CPUID(0x4) cache topology enumeration, CPUID(0xd) XSAVE enumeration, and CPUID(0x12) SGX Enclave Page Cache enumeration. In the CPUID_LEAF() data layout above, CPUID(0x4) has 8 storage entries to accomodate the suleaves 0 to 7, which all have the same bitfield's output format. With that, CPUID(0x4) subleaves 0->7 can be accessed using the compile time tokenization: const struct leaf_0x4_0 *l4_0, *l4_1, l4_2; l4_0 =3D cpuid_subleaf_index(c, 0x4, 0); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_0[0] l4_1 =3D cpuid_subleaf_index(c, 0x4, 1); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_0[1] l4_2 =3D cpuid_subleaf_index(c, 0x4, 2); | | =E2=94=94=E2=94=80=E2=94=80=E2=94=80= =E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | =E2=94=94=E2=94=80=E2=94=80=E2=94=80=E2= =94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=80=E2=94=90 | * * v &c.cpuid.leaf_0x4_0[2] where the indices 0, 1, 2 above can be provided dynamically. This is by design since call-sites hierarchical CPUID enumeration usually passes the CPUID subleaf enumeration index dynamically; e.g., within a for loop. For each of the CPUID leaf/subleaf output storage entries, attach a 'struct leaf_query_info' leaf_0xN_M_info instance. It is to be filled by the CPUID parsing logic filling the CPUID table(s). For now, this info structure has one element: the number of filled slots by the CPUID paraser in the CPUID leaf/subleaf output storage array. ** Call-site APIs Introduce below APIs for CPUID leaves with static subleaves: cpuid_subleaf(_cpuinfo, _leaf, _subleaf) cpuid_leaf(_cpuinfo, _leaf) cpuid_leaf_regs(_cpuinfo, _leaf) And below APIs for CPUID leaves with dynamic subleaves: cpuid_subleaf_count(_cpuinfo, _leaf) cpuid_subleaf_index(_cpuinfo, _leaf, _idx) cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx) At , add a clear rationale for why call sites should use the above APIs instead of directly invoking CPUID queries. ** Next steps For now, define entries for CPUID(0x0) and CPUID(0x1) in the CPUID table. Generic CPUID parser logic to fill the per-CPU CPUID tables, along with more CPUID leaves support, will be added next. Suggested-by: Thomas Gleixner # CPUID data model Suggested-by: Andrew Cooper # x86-cpuid-db sche= ma Suggested-by: Ingo Molnar # CPUID APIs restructuring Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/874ixernra.ffs@tglx Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db --- arch/x86/include/asm/cpuid/api.h | 254 +++++++++++++++++++++++++++++ arch/x86/include/asm/cpuid/types.h | 104 ++++++++++++ arch/x86/include/asm/processor.h | 1 + 3 files changed, 359 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 2b9750cc8a75..b277c82e062f 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -289,4 +289,258 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) return cpuid_edx(0x80000006); } =20 +/* + * 'struct cpuid_leaves' accessors: + * + * For internal-use by the CPUID parser. These macros do not perform any + * sanity checks. + */ + +/** + * __cpuid_leaves_subleaf_idx() - Get parsed CPUID output (without sanity = checks) + * @_leaves: &struct cpuid_leaves instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * @_idx: @_leaf/@_subleaf CPUID output's storage array index. Check + * __CPUID_LEAF() for info on CPUID output storage arrays indexing. + * + * Returns the parsed CPUID output at @_leaves as a d= ata + * type: 'struct leaf_0xN_M', where 0xN is the token provided at @_leaf, a= nd M + * is token provided at @_subleaf. + */ +#define __cpuid_leaves_subleaf_idx(_leaves, _leaf, _subleaf, _idx) \ + ((_leaves)->leaf_ ## _leaf ## _ ## _subleaf)[_idx] + +/** + * __cpuid_leaves_subleaf_0() - Get parsed CPUID output (without sanity ch= ecks) + * @_leaves: &struct cpuid_leaves instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * + * Like __cpuid_leaves_subleaf_idx(), but with subleaf =3D 0 and index =3D= 0. + */ +#define __cpuid_leaves_subleaf_0(_leaves, _leaf) \ + __cpuid_leaves_subleaf_idx(_leaves, _leaf, 0, 0) + +/** + * __cpuid_leaves_subleaf_info() - Get CPUID query info for @_leaf/@_suble= af + * @_leaves: &struct cpuid_leaves instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * + * Returns a pointer to the &struct leaf_query_info instance associated wi= th + * the given @_leaf/@_subleaf pair at the CPUID @_leaves data repository. = See + * __CPUID_LEAF(). + */ +#define __cpuid_leaves_subleaf_info(_leaves, _leaf, _subleaf) \ + ((_leaves)->leaf_ ## _leaf ## _ ## _subleaf ## _ ## info) + +/* + * 'struct cpuid_table' accessors: + * + * For internal-use by the CPUID parser. These macros perform the necessa= ry + * sanity checks by default. + */ + +/** + * __cpuid_table_subleaf_idx() - Get parsed CPUID output (with sanity chec= ks) + * @_table: &struct cpuid_table instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * @_idx: @_leaf/@_subleaf CPUID query output's storage array index. + * See __CPUID_LEAF(). + * + * Return a pointer to the requested parsed CPUID output at @_table, as a + * data type: 'struct leaf_0xN_M', where 0xN is the t= oken + * provided at @_leaf, and M is the token provided at @_subleaf; e.g. 'str= uct + * leaf_0x7_0'. + * + * Returns NULL if the requested CPUID @_leaf/@_subleaf/@_idx query output= is + * not present at @_table. + */ +#define __cpuid_table_subleaf_idx(_table, _leaf, _subleaf, _idx) \ + (((_idx) >=3D __cpuid_leaves_subleaf_info(&((_table)->leaves), _leaf, _su= bleaf).nr_entries) ? \ + NULL : &__cpuid_leaves_subleaf_idx(&((_table)->leaves), _leaf, _subleaf,= _idx)) + +/** + * __cpuid_table_subleaf() - Get parsed CPUID output (with sanity checks) + * @_table: &struct cpuid_table instance + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * + * Like __cpuid_table_subleaf_idx(), but with CPUID output storage index = =3D 0. + */ +#define __cpuid_table_subleaf(_table, _leaf, _subleaf) \ + __cpuid_table_subleaf_idx(_table, _leaf, _subleaf, 0) + +/* + * External APIs for accessing parsed CPUID data: + * + * Call sites should use below APIs instead of invoking direct CPUID queri= es. + * + * Benefits include: + * + * - Return CPUID output as typed C structures that are auto-generated fro= m a + * centralized database (see data type: 'struct leaf_0xN_M', wh= ere + * 0xN is the token provided at @_leaf, and M is the token provided at + * @_subleaf; e.g. struct leaf_0x7_0. + * + * Returns NULL if the requested CPUID @_leaf/@_subleaf query output is not + * present at the parsed CPUID table inside @_cpuinfo. This can happen if: + * + * - The CPUID table inside @_cpuinfo has not yet been populated. + * - The CPUID table inside @_cpuinfo was populated, but the CPU does not + * implement the requested CPUID @_leaf/@_subleaf combination. + * - The CPUID table inside @_cpuinfo was populated, but the kernel's CPUID + * parser has predetermined that the requested CPUID @_leaf/@_subleaf + * hardware output is invalid or unsupported. + * + * Example usage:: + * + * const struct leaf_0x7_0 *l7_0 =3D cpuid_subleaf(c, 0x7, 0); + * if (!l7_0) { + * // Handle error + * } + * + * const struct leaf_0x7_1 *l7_1 =3D cpuid_subleaf(c, 0x7, 1); + * if (!l7_1) { + * // Handle error + * } + */ +#define cpuid_subleaf(_cpuinfo, _leaf, _subleaf) \ + __cpuid_table_subleaf(&_cpuinfo->cpuid, _leaf, _subleaf) + +/** + * cpuid_leaf() - Access parsed CPUID data + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x0, 0x2, 0x800000= 00 + * + * Similar to cpuid_subleaf(), but with a CPUID subleaf =3D 0. + * + * Example usage:: + * + * const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + * if (!l0) { + * // Handle error + * } + * + * const struct leaf_0x80000000_0 *el0 =3D cpuid_leaf(c, 0x80000000); + * if (!el0) { + * // Handle error + * } + */ +#define cpuid_leaf(_cpuinfo, _leaf) \ + cpuid_subleaf(_cpuinfo, _leaf, 0) + +/** + * cpuid_leaf_regs() - Access parsed CPUID data in raw format + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format + * + * Similar to cpuid_leaf(), but returns a raw 'struct cpuid_regs' pointer = to + * the parsed CPUID data instead of a "typed" pointer. + */ +#define cpuid_leaf_regs(_cpuinfo, _leaf) \ + ((struct cpuid_regs *)(cpuid_leaf(_cpuinfo, _leaf))) + +#define __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf) \ + static_assert(ARRAY_SIZE(_cpuinfo->cpuid.leaves.leaf_ ## _leaf ## _0) > 1= ); + +/** + * cpuid_subleaf_index() - Access parsed CPUID data at runtime subleaf ind= ex + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * @_idx: Index within CPUID(@_leaf) output storage array. It must be + * smaller than "cpuid_subleaf_count(@_cpuinfo, @_leaf)". Unlike + * @_leaf, this value can be provided dynamically. + * + * For a given leaf/subleaf combination, the CPUID table inside @_cpuinfo + * contains an array of CPUID output storage entries. An array of storage + * entries is used to accommodate CPUID leaves which produce the same outp= ut + * format for a large subleaf range. This is common for CPUID hierarchical + * objects enumeration; e.g., CPUID(0x4) and CPUID(0xd). Check CPUID_LEAF= (). + * + * CPUID leaves that are to be accessed using this macro are specified at + * , 'struct cpuid_leaves', with a CPUID_LEAF() count field + * bigger than 1. A build-time error will be generated otherwise. + * + * Example usage:: + * + * const struct leaf_0x4_0 *l4; + * + * for (int i =3D 0; i < cpuid_subleaf_count(c, 0x4); i++) { + * l4 =3D cpuid_subleaf_index(c, 0x4, i); + * if (!l4) { + * // Handle error + * } + * + * // Access CPUID(0x4, i) data; e.g. l4->cache_type + * } + * + * Beside the standard error situations detailed at cpuid_subleaf(), this + * macro will return NULL if @_idx is out of range. + */ +#define cpuid_subleaf_index(_cpuinfo, _leaf, _idx) \ +({ \ + __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf); \ + __cpuid_table_subleaf_idx(&_cpuinfo->cpuid, _leaf, 0, _idx); \ +}) + +/** + * cpuid_subleaf_index_regs() - Access parsed CPUID data at runtime sublea= f index + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * @_idx: Index within CPUID(@_leaf) output storage array. It must be + * smaller than "cpuid_subleaf_count(@_cpuinfo, @_leaf)". + * + * Similar to cpuid_subleaf_index(), but returns a raw 'struct cpuid_regs' + * pointer to the parsed CPUID data, instead of a "typed" + * pointer. + */ +#define cpuid_subleaf_index_regs(_cpuinfo, _leaf, _idx) \ + ((struct cpuid_regs *)cpuid_subleaf_index(_cpuinfo, _leaf, _idx)) + +/** + * cpuid_subleaf_count() - Number of valid (filled) subleaves for @_leaf + * @_cpuinfo: CPU capability structure reference ('struct cpuinfo_x86') + * @_leaf: CPUID leaf, in compile-time 0xN format; e.g. 0x4, 0x8000001d + * + * Return the number of subleaves filled by the CPUID parser for @_leaf. C= heck + * cpuid_subleaf_index(). + * + * CPUID leaves that are to be accessed using this macro are specified at + * , 'struct cpuid_leaves', with a CPUID_LEAF() count field + * bigger than 1. A build-time error will be generated otherwise. + */ +#define cpuid_subleaf_count(_cpuinfo, _leaf) \ +({ \ + __cpuid_assert_leaf_has_dynamic_subleaves(_cpuinfo, _leaf); \ + __cpuid_leaves_subleaf_info(&_cpuinfo->cpuid.leaves, _leaf, 0).nr_entries= ;\ +}) + #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 8a00364b79de..f1b51ba21ca4 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -5,6 +5,8 @@ #include #include =20 +#include + /* * Types for raw CPUID access: */ @@ -124,4 +126,106 @@ extern const struct leaf_0x2_table cpuid_0x2_table[25= 6]; */ #define TLB_0x63_2M_4M_ENTRIES 32 =20 +/* + * Types for centralized CPUID tables: + * + * For internal use by the CPUID parser. + */ + +/** + * struct leaf_query_info - Parse info for a CPUID leaf/subleaf query + * @nr_entries: Number of valid output storage entries filled by the CPUID= parser + * + * In a CPUID table (struct cpuid_leaves), each CPUID leaf/subleaf query o= utput + * storage entry from is paired with a unique instanc= e of + * this type. + */ +struct leaf_query_info { + unsigned int nr_entries; +}; + +/** + * __CPUID_LEAF() - Define CPUID output storage and query info entry + * @_name: Struct type name of the CPUID leaf/subleaf (e.g. 'leaf_0x4_0'). + * Such types are defined at , and follow the + * format 'struct leaf_0xN_M', where 0xN is the leaf and M is the + * subleaf. + * @_count: Number of storage entries to allocate for this leaf/subleaf + * + * For the given leaf/subleaf combination, define an array of CPUID output + * storage entries and an associated query info structure =E2=80=94 both r= esiding in a + * 'struct cpuid_leaves' instance. + * + * Use an array of storage entries to accommodate CPUID leaves which produ= ce + * the same output format for a large subleaf range. This is common for + * hierarchical objects enumeration; e.g., CPUID(0x4), CPUID(0xd), and + * CPUID(0x12). + * + * The example invocation for CPUID(0x7) storage, subleaves 0->1: + * + * __CPUID_LEAF(leaf_0x7_0, 1); + * __CPUID_LEAF(leaf_0x7_1, 1); + * + * generates 'struct cpuid_leaves' storage entries in the form:: + * + * struct leaf_0x7_0 leaf_0x7_0[1]; + * struct leaf_query_info leaf_0x7_0_info; + * + * struct leaf_0x7_1 leaf_0x7_1[1]; + * struct leaf_query_info leaf_0x7_1_info; + * + * The example invocation for CPUID(0x4) storage:: + * + * __CPUID_LEAF(leaf_0x4_0, 8); + * + * generates storage entries in the form: + * + * struct leaf_0x4_0 leaf_0x4_0[8]; + * struct leaf_query_info leaf_0x4_0_info; + * + * where the 'leaf_0x4_0[8]' storage array can accommodate the output of + * CPUID(0x4) subleaves 0->7, since they all have the same output format. + */ +#define __CPUID_LEAF(_name, _count) \ + struct _name _name[_count]; \ + struct leaf_query_info _name##_info + +/** + * CPUID_LEAF() - Define a CPUID storage entry in 'struct cpuid_leaves' + * @_leaf: CPUID Leaf number in the 0xN format; e.g., 0x4. + * @_subleaf: Subleaf number in decimal + * @_count: Number of repeated storage entries for this @_leaf/@_subleaf + * + * Convenience wrapper around __CPUID_LEAF(). + */ +#define CPUID_LEAF(_leaf, _subleaf, _count) \ + __CPUID_LEAF(leaf_ ## _leaf ## _ ## _subleaf, _count) + +/* + * struct cpuid_leaves - Structured CPUID data repository + */ +struct cpuid_leaves { + /* leaf subleaf count */ + CPUID_LEAF(0x0, 0, 1); + CPUID_LEAF(0x1, 0, 1); +}; + +/* + * Types for centralized CPUID tables: + * + * For external use. + */ + +/** + * struct cpuid_table - Per-CPU CPUID data repository + * @leaves: CPUID leaf/subleaf queries' output and metadata + * + * Embedded inside 'struct cpuinfo_x86' to provide access to stored, parse= d, + * and sanitized CPUID output per-CPU. Thus removing the need for any dir= ect + * CPUID query by call sites. + */ +struct cpuid_table { + struct cpuid_leaves leaves; +}; + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/include/asm/processor.h b/arch/x86/include/asm/proces= sor.h index bde58f6510ac..b5d90b60191b 100644 --- a/arch/x86/include/asm/processor.h +++ b/arch/x86/include/asm/processor.h @@ -165,6 +165,7 @@ struct cpuinfo_x86 { char x86_vendor_id[16]; char x86_model_id[64]; struct cpuinfo_topology topo; + struct cpuid_table cpuid; /* in KB - valid for CPUS which support this call: */ unsigned int x86_cache_size; int x86_cache_alignment; /* In bytes */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8D49D27CCE0 for ; Thu, 5 Jun 2025 19:24:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151468; cv=none; b=De1LtDmUrPUApaX8sUJm8NGgZFLRja7iBuMRFuGPSCT9K/rbS2WuYC4Mv6hkemWfiaYjWawVUuaQKa0QQYQXuRPF5P72s0t+ZF+mKgcn1alUa3NOyCSfUdyvFfd4SQ2BbbY9jthwRJSegxsYpJFaTuqagE38BUVO7G4ksqlwTnk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151468; c=relaxed/simple; bh=Xy3hFC5HbL+XhPleEpjLCP16fhe7CEQaC2laEUa1FIY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kS7cPkm/fi7wS9i1+cUy9kpDWBk52fO5G9Xr40izGIWYGO8Pe5ydcvf2BXVwuF+tlFHw2Vk8iplVAea6mdblfHZbLG0hulDitPQM469Er2DB6jSRIVu+l6rglO8bivEIpm12AVJ2ZLn55LqDZyzNkanIo9x+j73iI8XZc8LN++c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=p77h4NqJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dEE/sGcM; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="p77h4NqJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dEE/sGcM" From: "Ahmed S. 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Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 05/27] x86/cpuid: Introduce a centralized CPUID parser Date: Thu, 5 Jun 2025 21:23:34 +0200 Message-ID: <20250605192356.82250-6-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce a centralized CPUID parser to populate the per-CPU CPUID tables. To ensures consistent and early availablity of parsed CPUID data, invoke this parser during both early boot and secondary CPUs bring up. Since accessing the CPUID leaf output storage areas at 'struct cpuid_table' requires compile time tokenization, split the parser implementation into two stages: compile time macros for tokenizing the leaf/subleaf output offsets within a CPUID table, and generic runtime code to access and populate the relevant CPUID leaf/subleaf data structures using such offsets. For flexible parsing of CPUID leaf/subleaf outputs, support both generic and leaf-specific CPUID read functions. Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 7 ++ arch/x86/include/asm/cpuid/types.h | 3 + arch/x86/kernel/cpu/Makefile | 1 + arch/x86/kernel/cpu/common.c | 2 + arch/x86/kernel/cpu/cpuid_parser.c | 80 +++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 100 +++++++++++++++++++++++++++++ 6 files changed, 193 insertions(+) create mode 100644 arch/x86/kernel/cpu/cpuid_parser.c create mode 100644 arch/x86/kernel/cpu/cpuid_parser.h diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index b277c82e062f..a0c84fbc8fcb 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -7,6 +7,7 @@ #include #include =20 +#include #include =20 /* @@ -543,4 +544,10 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) __cpuid_leaves_subleaf_info(&_cpuinfo->cpuid.leaves, _leaf, 0).nr_entries= ;\ }) =20 +/* + * CPUID parser APIs: + */ + +void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c); + #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index f1b51ba21ca4..320f152675af 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -32,6 +32,9 @@ enum cpuid_regs_idx { #define CPUID_LEAF_FREQ 0x16 #define CPUID_LEAF_TILE 0x1d =20 +#define CPUID_BASE_START 0x0 +#define CPUID_BASE_END (CPUID_BASE_START + 0xffff) + /* * Types for CPUID(0x2) parsing: */ diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index 1e26179ff18c..b2421cfb59ed 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -19,6 +19,7 @@ KCSAN_SANITIZE_common.o :=3D n =20 obj-y :=3D cacheinfo.o scattered.o obj-y +=3D topology_common.o topology_ext.o topology_amd.o +obj-y +=3D cpuid_parser.o obj-y +=3D common.o obj-y +=3D rdrand.o obj-y +=3D match.o diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8feb8fd2957a..8aa3ba269c0b 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1716,6 +1716,7 @@ static void __init early_identify_cpu(struct cpuinfo_= x86 *c) =20 /* cyrix could have cpuid enabled via c_identify()*/ if (cpuid_feature()) { + cpuid_parser_scan_cpu(c); cpu_detect(c); get_cpu_vendor(c); intel_unlock_cpuid_leafs(c); @@ -2096,6 +2097,7 @@ void identify_secondary_cpu(unsigned int cpu) *c =3D boot_cpu_data; c->cpu_index =3D cpu; =20 + cpuid_parser_scan_cpu(c); identify_cpu(c); #ifdef CONFIG_X86_32 enable_sep_cpu(); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c new file mode 100644 index 000000000000..949a731e03b1 --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -0,0 +1,80 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Centralized CPUID parser (for populating the system's CPUID tables.) + */ + +#include +#include + +#include +#include +#include + +#include "cpuid_parser.h" + +/* + * Default CPUID parser read function + */ +static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct c= puid_read_output *output) +{ + output->info->nr_entries =3D 0; + for (int i =3D 0; i < e->maxcnt; i++, output->regs++, output->info->nr_en= tries++) + cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); +} + +static unsigned int cpuid_range_max_leaf(const struct cpuid_leaves *l, uns= igned int range) +{ + switch (range) { + case CPUID_BASE_START: return __cpuid_leaves_subleaf_0(l, 0x0).max_std_le= af; + default: return 0; + } +} + +static bool +cpuid_range_valid(const struct cpuid_leaves *l, unsigned int leaf, unsigne= d int start, unsigned int end) +{ + if (leaf < start || leaf > end) + return false; + + return leaf =3D=3D start || leaf <=3D cpuid_range_max_leaf(l, start); +} + +static bool cpuid_leaf_valid(const struct cpuid_leaves *l, unsigned int le= af) +{ + return cpuid_range_valid(l, leaf, CPUID_BASE_START, CPUID_BASE_END); +} + +static const struct cpuid_parse_entry cpuid_common_parse_entries[] =3D { + CPUID_PARSE_ENTRIES +}; + +static void +cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry ent= ries[], unsigned int nr_entries) +{ + const struct cpuid_parse_entry *entry =3D entries; + + for (unsigned int i =3D 0; i < nr_entries; i++, entry++) { + struct cpuid_read_output output =3D { + .regs =3D cpuid_leaves_query_regs_p(&t->leaves, entry->regs_offs), + .info =3D cpuid_leaves_query_info_p(&t->leaves, entry->info_offs), + }; + + if (!cpuid_leaf_valid(&t->leaves, entry->leaf)) + continue; + + entry->read(entry, &output); + } +} + +/** + * cpuid_parser_scan_cpu() - Populate current CPU's CPUID table + * @c: CPU capability structure associated with the current CPU + * + * Populate the CPUID table embedded within @c with parsed CPUID data. Si= nce all CPUID + * instructions are invoked locally, this must be called on the CPU associ= ated with @c. + */ +void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) +{ + cpuid_fill_table(&c->cpuid, cpuid_common_parse_entries, + ARRAY_SIZE(cpuid_common_parse_entries)); +} diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h new file mode 100644 index 000000000000..b09c39a9a0b8 --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef _ARCH_X86_CPUID_PARSER_H +#define _ARCH_X86_CPUID_PARSER_H + +#include + +/* + * 'struct cpuid_leaves' CPUID query output storage area accessors: + * + * @_leaf: CPUID leaf, in compile-time 0xN format + * @_subleaf: CPUID subleaf, in compile-time decimal format + * + * Since accessing the CPUID leaf output storage areas at 'struct cpuid_le= aves' requires + * compile time tokenization, split the CPUID parser implementation into t= wo stages: + * compile time macros for tokenizing the leaf/subleaf output offsets with= in the CPUID + * table, and generic runtime code to access and populate the relevant CPU= ID leaf/subleaf + * output data structures using such offsets. + * + * That is, the output of the __cpuid_leaves_query_*_offset() macros will= be cached by a + * compile time "parse entry" (see 'struct cpuid_parse_entry'). The runti= me parser code + * will then utilize such offsets by passing them to cpuid_leaves_query_*_= p() functions. + */ + +#define __cpuid_leaves_query_regs_offset(_leaf, _subleaf) \ + offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf) + +#define __cpuid_leaves_query_info_offset(_leaf, _subleaf) \ + offsetof(struct cpuid_leaves, leaf_ ## _leaf ## _ ## _subleaf ## _ ## inf= o) + +#define __cpuid_leaves_query_regs_maxcnt(_leaf, _subleaf) \ + ARRAY_SIZE(((struct cpuid_leaves *)NULL)->leaf_ ## _leaf ## _ ## _subleaf) + +static inline struct cpuid_regs * +cpuid_leaves_query_regs_p(const struct cpuid_leaves *l, unsigned long regs= _offset) +{ + return (struct cpuid_regs *)((unsigned long)(l) + regs_offset); +} + +static inline struct leaf_query_info * +cpuid_leaves_query_info_p(const struct cpuid_leaves *l, unsigned long info= _offset) +{ + return (struct leaf_query_info *)((unsigned long)(l) + info_offset); +} + +/** + * struct cpuid_read_output - Output of a CPUID parser read operation + * @regs: Pointer to an array of CPUID outputs, where each array element c= overs the + * full EAX->EDX output range. + * @info: Pointer to query info; for saving the number of filled @regs arr= ay elements. + * + * A CPUID parser read function like cpuid_read_generic() or cpuid_read_0x= N() uses this + * structure to save its CPUID query outputs. Actual storage for @regs an= d @info is provided + * by its caller, and is typically within a CPU's CPUID table (struct cpui= d_table.leaves). + * + * See struct cpuid_parse_entry.read(). + */ +struct cpuid_read_output { + struct cpuid_regs *regs; + struct leaf_query_info *info; +}; + +/** + * struct cpuid_parse_entry - Runtime CPUID parsing context for @leaf/@sub= leaf + * @leaf: Leaf number to be parsed + * @subleaf: Subleaf number to be parsed + * @regs_offs: Offset within 'struct cpuid_leaves' for saving CPUID @leaf/= @subleaf output; to be + * passed to cpuid_leaves_query_regs_p(). + * @info_offs: Offset within 'struct cpuid_leaves' for accessing @leaf/@su= bleaf parse info; to be + * passed to cpuid_leaves_query_info_p(). + * @maxcnt: Maximum number of output storage entries available for the @le= af/@subleaf query + * @read: Read function for this entry. It must save the parsed CPUID out= put to the passed + * 'struct cpuid_read_output'->regs registers array of size >=3D @maxcnt.= It must set + * 'struct cpuid_read_output'->info.nr_entries to the actual number of st= orage output + * entries filled. A generic implementation is provided at cpuid_read_ge= neric(). + */ +struct cpuid_parse_entry { + unsigned int leaf; + unsigned int subleaf; + unsigned int regs_offs; + unsigned int info_offs; + unsigned int maxcnt; + void (*read)(const struct cpuid_parse_entry *e, struct cpuid_read_output= *o); +}; + +#define CPUID_PARSE_ENTRY(_leaf, _subleaf, _reader_fn) \ + { \ + .leaf =3D _leaf, \ + .subleaf =3D _subleaf, \ + .regs_offs =3D __cpuid_leaves_query_regs_offset(_leaf, _subleaf), \ + .info_offs =3D __cpuid_leaves_query_info_offset(_leaf, _subleaf), \ + .maxcnt =3D __cpuid_leaves_query_regs_maxcnt(_leaf, _subleaf), \ + .read =3D cpuid_read_ ## _reader_fn, \ + } + +#define CPUID_PARSE_ENTRIES \ + /* Leaf Subleaf Reader function */ \ + CPUID_PARSE_ENTRY(0x0, 0, generic), \ + CPUID_PARSE_ENTRY(0x1, 0, generic), \ + +#endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 03A1B27E7F4 for ; Thu, 5 Jun 2025 19:24:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151471; cv=none; b=uaU1S0ZtzQMsnMlI2MNZ74fbzvd8stG9LfU6v82pjISitX5XflH3EFlWfv2yH/bzrZVl9flF89P5998djY8tV2G0pJuHxmn+AbQwwWJomsdllxkNB60+rXUvSRKCnLutkQ0gjsa++rmHXs6uJ5aSJjebzLdnokdoe8c54x0VWFM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151471; c=relaxed/simple; bh=uGq4PDMRlkbDz2q9cE8/8yjG9MzWmqLpG6DREyo6Buo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lpOUCt+XwVVMpNIYg+V38iov6+WTZ/SguFIZujWRd7OPDdOeV+t+ZPatqfotN0prR7m9OqWAWf3KJbqGDCnYLMuxupLmFqLlwBoMm44k7WPVD//XgXfLkoTK0fOls/L12nqc51lyiR8DBHOOO+hQdsJkh2VWch3Pn53tdQffmgc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fMhJoRxg; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PyVZjl1y; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fMhJoRxg"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PyVZjl1y" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151468; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jRw9/W2ZgpLvBd3Ycf4s2jzsX5uuNkOk7zIzQx3robI=; b=fMhJoRxgstPTpvegoP/lrP4NLlwseUkwpTPoF+DhRAy1OjNaJkX8P2nHIgbJDuInGpqRQu buyg0RodX7soeLy2QzAUsNZIzLUDQSndePs1FA6QMuPCeb9Rqm8oH70DtalU4dLLxXwBrG 5BF6FgESmYjEMHcbZzOozHme/IDV6eIuZdI4lJNK5I5Qm3UxyJ9d88RpPiMfE4P48PsHW1 nzjI/RJXyGiIIIigYaz8dkP+TwnPX4Xp2C6G5vwAMimTX65vPk1gM42AkegNHVQ2X5xXXd A1CifkoBBiCEs1nx3umKI0vLCwrShDOfZx4bASGroTQDwy/8AeQwJeDGlle6oQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151468; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jRw9/W2ZgpLvBd3Ycf4s2jzsX5uuNkOk7zIzQx3robI=; b=PyVZjl1yfRQbr5RTEJULEuXtcPDzaJtEreqoW1Kac+dKreufsjPNC4Og/7GD2SUlyiQA43 K/7+fotZO95UpjCA== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 06/27] x86/cpuid: Parse CPUID(0x80000000) Date: Thu, 5 Jun 2025 21:23:35 +0200 Message-ID: <20250605192356.82250-7-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID parser logic for CPUID(0x80000000). Similar to kernel/head_32.S and kernel/cpu/common.c, verify the CPUID(0x80000000) query output beforehand. This is due to x86-32 machines without an extended CPUID range, where a CPUID(0x80000000) query will just repeat the max-valid standard CPUID leaf output. References: 8a50e5135af0 ("x86-32: Use symbolic constants, safer CPUID when= enabling EFER.NX") References: 67ad24e6d39c ("- pre5: - Rasmus Andersen: add proper...") #= Historical git Suggested-by: Andrew Cooper Suggested-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish Cc: "H. Peter Anvin" Link: https://lore.kernel.org/r/d4fcfd91-cc92-4b3c-9dd2-56ecd754cecc@citrix= .com --- arch/x86/include/asm/cpuid/types.h | 7 ++++++- arch/x86/kernel/cpu/cpuid_parser.c | 22 +++++++++++++++++++++- arch/x86/kernel/cpu/cpuid_parser.h | 1 + 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 320f152675af..d0f0e6a8a457 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -33,7 +33,11 @@ enum cpuid_regs_idx { #define CPUID_LEAF_TILE 0x1d =20 #define CPUID_BASE_START 0x0 -#define CPUID_BASE_END (CPUID_BASE_START + 0xffff) +#define CPUID_EXT_START 0x80000000 + +#define __CPUID_RANGE_END(idx) ((idx) + 0xffff) +#define CPUID_BASE_END __CPUID_RANGE_END(CPUID_BASE_START) +#define CPUID_EXT_END __CPUID_RANGE_END(CPUID_EXT_START) =20 /* * Types for CPUID(0x2) parsing: @@ -211,6 +215,7 @@ struct cpuid_leaves { /* leaf subleaf count */ CPUID_LEAF(0x0, 0, 1); CPUID_LEAF(0x1, 0, 1); + CPUID_LEAF(0x80000000, 0, 1); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 949a731e03b1..731aab2ff9c0 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -22,10 +22,29 @@ static void cpuid_read_generic(const struct cpuid_parse= _entry *e, struct cpuid_r cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); } =20 +static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struc= t cpuid_read_output *output) +{ + struct leaf_0x80000000_0 *el0 =3D (struct leaf_0x80000000_0 *)output->reg= s; + + cpuid_read_subleaf(e->leaf, e->subleaf, el0); + + /* + * Protect against 32-bit CPUs lacking extended CPUID support: Max + * extended CPUID leaf must be in the 0x80000001-0x8000ffff range. + */ + if ((el0->max_ext_leaf & 0xffff0000) !=3D 0x80000000) { + *el0 =3D (struct leaf_0x80000000_0){ }; + return; + } + + output->info->nr_entries =3D 1; +} + static unsigned int cpuid_range_max_leaf(const struct cpuid_leaves *l, uns= igned int range) { switch (range) { case CPUID_BASE_START: return __cpuid_leaves_subleaf_0(l, 0x0).max_std_le= af; + case CPUID_EXT_START: return __cpuid_leaves_subleaf_0(l, 0x80000000).ma= x_ext_leaf; default: return 0; } } @@ -41,7 +60,8 @@ cpuid_range_valid(const struct cpuid_leaves *l, unsigned = int leaf, unsigned int =20 static bool cpuid_leaf_valid(const struct cpuid_leaves *l, unsigned int le= af) { - return cpuid_range_valid(l, leaf, CPUID_BASE_START, CPUID_BASE_END); + return cpuid_range_valid(l, leaf, CPUID_BASE_START, CPUID_BASE_END) || + cpuid_range_valid(l, leaf, CPUID_EXT_START, CPUID_EXT_END); } =20 static const struct cpuid_parse_entry cpuid_common_parse_entries[] =3D { diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index b09c39a9a0b8..f440948fc2fc 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -96,5 +96,6 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x0, 0, generic), \ CPUID_PARSE_ENTRY(0x1, 0, generic), \ + CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), =20 #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC97827EC7D for ; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151471; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gy7h4HawSvU5tLHqrdABGWs1B/wd8RgWXzUlvPObMJk=; b=vfQE6UYtA8as5f8H7CfF4htske2JNAf4t+sSLvmlQ390X1b8urxc5iKBK//CRrjsy98iWA 7gv3G7QLHlWGVU27XI6CDg2f1leT2eC4Gcm9FTAJ/lKEsk7Vbz3dAOQLU0o53hrxgo1FyJ AtR6HMuVkLwR0m35cgCEFp9OhiyH6N6ltUZ6QKkZV1QT0bYN1v8oU59z7fa3iq3dItLbTT AQUwio6ehNw5ILiXUBQj5HNJYb/qN9UwrpXM1WX9a1p0xsCwwi46dQoEoqUaFSggH6sEo6 3ebAUwfwfJkUj4VvMdMTTsrF9Kz3H/kDTc/yl3iY9UOi93toelqEa7VKsdg2fA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151471; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gy7h4HawSvU5tLHqrdABGWs1B/wd8RgWXzUlvPObMJk=; b=HEMcDGMgEkyMpHCXLRw67vxxAukzyhED/10rjWCLDULfTuwQCjHtBKdLFOgUoVEOgM2xb7 9H6a0iKuu5VF8KDw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 07/27] x86/cpuid: Introduce CPUID parser debugfs interface Date: Thu, 5 Jun 2025 21:23:36 +0200 Message-ID: <20250605192356.82250-8-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Introduce the debugfs files 'x86/cpuid/[0-ncpus]' to dump each CPU's cached CPUID table. For each cached CPUID leaf/subleaf, invoke the CPUID instruction on the target CPU and compare the hardware result against the cached values. Mark any mismatched cached CPUID output value with an asterisk. This should help with tricky bug reports in the future, if/when the cached CPUID tables get unexpectedly out of sync with actual hardware state. It also simplifies the development and testing of adding new CPUID leaves to the CPUID parser. Note, expose cpuid_common_parse_entries[] via "cpuid_parser.h" to allow the debugfs code to traverse and dump the parsed CPUID data. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/Makefile | 2 +- arch/x86/kernel/cpu/cpuid_debugfs.c | 102 ++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.c | 7 +- arch/x86/kernel/cpu/cpuid_parser.h | 3 + 4 files changed, 110 insertions(+), 4 deletions(-) create mode 100644 arch/x86/kernel/cpu/cpuid_debugfs.c diff --git a/arch/x86/kernel/cpu/Makefile b/arch/x86/kernel/cpu/Makefile index b2421cfb59ed..4e032ad851c7 100644 --- a/arch/x86/kernel/cpu/Makefile +++ b/arch/x86/kernel/cpu/Makefile @@ -61,7 +61,7 @@ obj-$(CONFIG_X86_LOCAL_APIC) +=3D perfctr-watchdog.o obj-$(CONFIG_HYPERVISOR_GUEST) +=3D vmware.o hypervisor.o mshyperv.o obj-$(CONFIG_ACRN_GUEST) +=3D acrn.o =20 -obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o +obj-$(CONFIG_DEBUG_FS) +=3D debugfs.o cpuid_debugfs.o =20 obj-$(CONFIG_X86_BUS_LOCK_DETECT) +=3D bus_lock.o =20 diff --git a/arch/x86/kernel/cpu/cpuid_debugfs.c b/arch/x86/kernel/cpu/cpui= d_debugfs.c new file mode 100644 index 000000000000..fd39305a3c99 --- /dev/null +++ b/arch/x86/kernel/cpu/cpuid_debugfs.c @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * CPUID parser debugfs entries: x86/cpuid/[0-ncpus] + * + * Dump each CPU's cached CPUID table and compare its values against curre= nt + * CPUID output on that CPU. Mark changed entries with an asterisk. + */ + +#include +#include +#include +#include + +#include +#include +#include + +#include "cpuid_parser.h" + +static void cpuid_this_cpu(void *info) +{ + struct cpuid_regs *regs =3D info; + + __cpuid(®s->eax, ®s->ebx, ®s->ecx, ®s->edx); +} + +static void +cpuid_show_leaf(struct seq_file *m, uintptr_t cpu_id, const struct cpuid_p= arse_entry *entry, + const struct leaf_query_info *info, const struct cpuid_regs *cached) +{ + for (int j =3D 0; j < info->nr_entries; j++) { + u32 subleaf =3D entry->subleaf + j; + struct cpuid_regs regs =3D { + .eax =3D entry->leaf, + .ecx =3D subleaf, + }; + int ret; + + seq_printf(m, "Leaf 0x%08x, subleaf %u:\n", entry->leaf, subleaf); + + ret =3D smp_call_function_single(cpu_id, cpuid_this_cpu, ®s, true); + if (ret) { + seq_printf(m, "Failed to invoke CPUID on CPU %lu: %d\n\n", cpu_id, ret); + continue; + } + + seq_printf(m, " cached: %cEAX=3D0x%08x %cEBX=3D0x%08x %cECX=3D0x%= 08x %cEDX=3D0x%08x\n", + cached[j].eax =3D=3D regs.eax ? ' ' : '*', cached[j].eax, + cached[j].ebx =3D=3D regs.ebx ? ' ' : '*', cached[j].ebx, + cached[j].ecx =3D=3D regs.ecx ? ' ' : '*', cached[j].ecx, + cached[j].edx =3D=3D regs.edx ? ' ' : '*', cached[j].edx); + seq_printf(m, " actual: EAX=3D0x%08x EBX=3D0x%08x ECX=3D0x%08x= EDX=3D0x%08x\n", + regs.eax, regs.ebx, regs.ecx, regs.edx); + } +} + +static int cpuid_debug_show(struct seq_file *m, void *p) +{ + uintptr_t cpu_id =3D (uintptr_t)m->private; + const struct cpuinfo_x86 *c =3D per_cpu_ptr(&cpu_info, cpu_id); + + const struct cpuid_parse_entry *entry =3D cpuid_common_parse_entries; + const struct cpuid_leaves *leaves =3D &c->cpuid.leaves; + + for (unsigned int i =3D 0; i < cpuid_common_parse_entries_size; i++, entr= y++) { + const struct leaf_query_info *qi =3D cpuid_leaves_query_info_p(leaves, e= ntry->info_offs); + const struct cpuid_regs *qr =3D cpuid_leaves_query_regs_p(leaves, entry-= >regs_offs); + + cpuid_show_leaf(m, cpu_id, entry, qi, qr); + } + + return 0; +} + +static int cpuid_debug_open(struct inode *inode, struct file *file) +{ + return single_open(file, cpuid_debug_show, inode->i_private); +} + +static const struct file_operations cpuid_ops =3D { + .open =3D cpuid_debug_open, + .read =3D seq_read, + .llseek =3D seq_lseek, + .release =3D single_release, +}; + +static __init int cpuid_init_debugfs(void) +{ + struct dentry *dir; + uintptr_t cpu_id; + char cpu_name[24]; + + dir =3D debugfs_create_dir("cpuid", arch_debugfs_dir); + + for_each_possible_cpu(cpu_id) { + scnprintf(cpu_name, sizeof(cpu_name), "%lu", cpu_id); + debugfs_create_file(cpu_name, 0444, dir, (void *)cpu_id, &cpuid_ops); + } + + return 0; +} +late_initcall(cpuid_init_debugfs); diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 731aab2ff9c0..e79835a09336 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -64,10 +64,12 @@ static bool cpuid_leaf_valid(const struct cpuid_leaves = *l, unsigned int leaf) cpuid_range_valid(l, leaf, CPUID_EXT_START, CPUID_EXT_END); } =20 -static const struct cpuid_parse_entry cpuid_common_parse_entries[] =3D { +const struct cpuid_parse_entry cpuid_common_parse_entries[] =3D { CPUID_PARSE_ENTRIES }; =20 +const int cpuid_common_parse_entries_size =3D ARRAY_SIZE(cpuid_common_pars= e_entries); + static void cpuid_fill_table(struct cpuid_table *t, const struct cpuid_parse_entry ent= ries[], unsigned int nr_entries) { @@ -95,6 +97,5 @@ cpuid_fill_table(struct cpuid_table *t, const struct cpui= d_parse_entry entries[] */ void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) { - cpuid_fill_table(&c->cpuid, cpuid_common_parse_entries, - ARRAY_SIZE(cpuid_common_parse_entries)); + cpuid_fill_table(&c->cpuid, cpuid_common_parse_entries, cpuid_common_pars= e_entries_size); } diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index f440948fc2fc..0c79919a6138 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -98,4 +98,7 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY(0x1, 0, generic), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), =20 +extern const struct cpuid_parse_entry cpuid_common_parse_entries[]; +extern const int cpuid_common_parse_entries_size; + #endif /* _ARCH_X86_CPUID_PARSER_H */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36E8427FB03 for ; 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Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 08/27] x86/cpu: Use parsed CPUID(0x0) Date: Thu, 5 Jun 2025 21:23:37 +0200 Message-ID: <20250605192356.82250-9-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x0) access instead of a direct CPUID query. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 8aa3ba269c0b..234d0f5de39e 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -895,11 +895,12 @@ void get_cpu_vendor(struct cpuinfo_x86 *c) =20 void cpu_detect(struct cpuinfo_x86 *c) { - /* Get vendor name */ - cpuid(0x00000000, (unsigned int *)&c->cpuid_level, - (unsigned int *)&c->x86_vendor_id[0], - (unsigned int *)&c->x86_vendor_id[8], - (unsigned int *)&c->x86_vendor_id[4]); + const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + + c->cpuid_level =3D l0->max_std_leaf; + *(u32 *)&c->x86_vendor_id[0] =3D l0->cpu_vendorid_0; + *(u32 *)&c->x86_vendor_id[4] =3D l0->cpu_vendorid_1; + *(u32 *)&c->x86_vendor_id[8] =3D l0->cpu_vendorid_2; =20 c->x86 =3D 4; /* Intel-defined flags: level 0x00000001 */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 73DAE27FB1C for ; Thu, 5 Jun 2025 19:24:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151480; cv=none; b=TWOb/7Xq+zUYBuue2gysnBeJojfpCOYjLZpB2QxgUALejwUu6sIFdxbjArJPh9WjKv3fYGOhjgRFJP2O7JslHBn14g/qO+1/HkAVkeNcYzdRfw/AdI0S5DezKXspMExLbg0AjE+wWUMBd3/t0H2lyxTnxuJpVHLnFNpmXydEO2I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151480; c=relaxed/simple; bh=tSAjyB89b4eytydfgx0gH4Tzjd8WBD196r5kl7VISI8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eVCIalTcHbTFX16X6GN12iGdFG8Erd57Y8D6Y6BfY3GGwDLiDL84quYi2FsMB4TyE1pIkXXgOsG8fLvov1yrisq+nHw3mz7GnYvb2SzvWREhVPsAVcLtEJTRAN29PbUuvzXJsE4N6mdcTXP+ibjXYLk7J1DW90mJnpQTDsTeSIk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=J27tsaIB; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dzNmRZw2; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="J27tsaIB"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dzNmRZw2" From: "Ahmed S. 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Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 09/27] x86/cpu: Use parsed CPUID(0x80000001) Date: Thu, 5 Jun 2025 21:23:38 +0200 Message-ID: <20250605192356.82250-10-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x80000001) access instead of a direct CPUID query. The affected code has the check: (eax & 0xffff0000) =3D=3D 0x80000000 to protect against 32-bit CPUs that lack extended CPUID support. A similar check is already done at the CPUID(0x80000001) scanner read function at cpuid_parser.c: /* * Protect against 32-bit CPUs lacking extended CPUID support: Max * extended CPUID leaf must be in the 0x80000001-0x8000ffff range. */ if ((el0->max_ext_leaf & 0xffff0000) !=3D 0x80000000) { // Handle error } Thus, just check that the parsed CPUID macro: cpuid_leaf(c, 0x80000000) does not return NULL, thus providing a sanity check similar to the original code. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 234d0f5de39e..b3408ae2b144 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -972,6 +972,7 @@ static void init_speculation_control(struct cpuinfo_x86= *c) =20 void get_cpu_cap(struct cpuinfo_x86 *c) { + const struct leaf_0x80000000_0 *el0; u32 eax, ebx, ecx, edx; =20 /* Intel-defined flags: level 0x00000001 */ @@ -1007,12 +1008,8 @@ void get_cpu_cap(struct cpuinfo_x86 *c) c->x86_capability[CPUID_D_1_EAX] =3D eax; } =20 - /* - * Check if extended CPUID leaves are implemented: Max extended - * CPUID leaf must be in the 0x80000001-0x8000ffff range. - */ - eax =3D cpuid_eax(0x80000000); - c->extended_cpuid_level =3D ((eax & 0xffff0000) =3D=3D 0x80000000) ? eax = : 0; + el0 =3D cpuid_leaf(c, 0x80000000); + c->extended_cpuid_level =3D (el0) ? el0->max_ext_leaf : 0; =20 if (c->extended_cpuid_level >=3D 0x80000001) { cpuid(0x80000001, &eax, &ebx, &ecx, &edx); --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3713727FD5F for ; Thu, 5 Jun 2025 19:24:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151483; cv=none; b=AZ2hIvzwCO2waTqGqb/6kH+3w9zhhjDTI5KO2IqcMDUdnzJvf8oVJWcSIVHRok37et7lR/ribuupUAI4BpwFZ5GViHm7QF6e8wprIkC1dDeMT70gCc49gEIm+s7i7TFfrdcPZxaxogVFlCEXWk/JC+YwfChX4xLOWzRX88/YVAU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151483; c=relaxed/simple; bh=JjpKnEEeb8EihD6NhJ+3mHH6ulCNckG1EK6KQwd39Rs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QaTnbIkDzlszLkgnsEVL3iwlMYF5X1cDZQK1rYimRz8nwN8ghIr4o7cVN6vWDCsPyG0YhOYe9MxqzwNDJ53sXR2Eeyq6bWY0KgGSwPH+ths4fZzhiCpWveaGDvMDH8cCfFrQyNNJlqh+Hj4ADebqZMBGZeAirRDedU3+JXA5vV0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=MqMUQNT4; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/Ih4Q0AY; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="MqMUQNT4"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/Ih4Q0AY" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151480; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+Xr7p/ILqaWRsY65Bf4IVSsO8x0nPruOpeIN/uFfX+o=; b=MqMUQNT4d9cZoEam50RRqDy/t2+FjZbPbk8/8/CWAZqkTKVzSmRtpy8Wd9RycpjxldUHu6 fWlHSf0uh3CBaKSZIcMV3GwYC2HHzWH3YcRCTlIWA0bcGKFGUO8YLLvO1IzBEsU3Og/5d4 pvP9Mxu/9BCDj/G8WFuCAftMb/ITS4QHiNgPmT1SeS8/T96IUL4rMcl9HkJnvr4YS7Z1OI SngzGX6XMmzYd+jN2F8wKSjr7VU0TyOR/VSqqn1jIC1R6J4vmLXSQPTL4a3J0/CJjb0Bul QW65QJlk+enN8FEdNK02/FDghFSpPfY9wrqjwc2YXbevJ+aXcwLphdhg017tVg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151480; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+Xr7p/ILqaWRsY65Bf4IVSsO8x0nPruOpeIN/uFfX+o=; b=/Ih4Q0AY92bSExMow42vcgBa32Y5kNa1nu6vGkCkn0vUNbhQZxzILyOy6lQ08FhF119AYY 96vGf2vL7c+2O2Dw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 10/27] x86/lib: Add CPUID(0x1) CPU family and model calculation Date: Thu, 5 Jun 2025 21:23:39 +0200 Message-ID: <20250605192356.82250-11-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The x86 library code provides x86_family() and x86_model(). They take raw CPUID(0x1) EAX register output, extract the necessary bitfields with bitwise operations, then calculate out the CPU family and model. In follow-up commits, the x86 code will use parsed CPUID access, along with its auto-generated CPUID leaf data structures and their detailed C99 bitfields. Introduce CPU family and model calculation functions to x86/lib that take the auto-generated 'struct leaf_0x1_0' data type. Refactor the pure CPU family and model calculation logic into internal static functions so that no logic is duplicated. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpu.h | 6 ++++++ arch/x86/lib/cpu.c | 41 ++++++++++++++++++++++---------------- 2 files changed, 30 insertions(+), 17 deletions(-) diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index ad235dda1ded..90902cd91335 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -7,7 +7,9 @@ #include #include #include + #include +#include =20 #ifndef CONFIG_SMP #define cpu_physical_id(cpu) boot_cpu_physical_apicid @@ -25,6 +27,10 @@ int mwait_usable(const struct cpuinfo_x86 *); unsigned int x86_family(unsigned int sig); unsigned int x86_model(unsigned int sig); unsigned int x86_stepping(unsigned int sig); + +unsigned int cpuid_family(const struct leaf_0x1_0 *l); +unsigned int cpuid_model(const struct leaf_0x1_0 *l); + #ifdef CONFIG_X86_BUS_LOCK_DETECT extern void __init sld_setup(struct cpuinfo_x86 *c); extern bool handle_user_split_lock(struct pt_regs *regs, long error_code); diff --git a/arch/x86/lib/cpu.c b/arch/x86/lib/cpu.c index 7ad68917a51e..eac217d637ac 100644 --- a/arch/x86/lib/cpu.c +++ b/arch/x86/lib/cpu.c @@ -1,36 +1,43 @@ // SPDX-License-Identifier: GPL-2.0-only #include #include + #include +#include =20 -unsigned int x86_family(unsigned int sig) +static unsigned int __x86_family(unsigned int base_fam, unsigned int ext_f= am) { - unsigned int x86; - - x86 =3D (sig >> 8) & 0xf; + return (base_fam =3D=3D 0xf) ? base_fam + ext_fam : base_fam; +} =20 - if (x86 =3D=3D 0xf) - x86 +=3D (sig >> 20) & 0xff; +static unsigned int +__x86_model(unsigned int family, unsigned int base_model, unsigned int ext= _model) +{ + return (family >=3D 0x6) ? base_model | ext_model << 4 : base_model; +} =20 - return x86; +unsigned int x86_family(unsigned int sig) +{ + return __x86_family((sig >> 8) & 0xf, (sig >> 20) & 0xff); } EXPORT_SYMBOL_GPL(x86_family); =20 -unsigned int x86_model(unsigned int sig) +unsigned int cpuid_family(const struct leaf_0x1_0 *l) { - unsigned int fam, model; - - fam =3D x86_family(sig); - - model =3D (sig >> 4) & 0xf; - - if (fam >=3D 0x6) - model +=3D ((sig >> 16) & 0xf) << 4; + return __x86_family(l->base_family_id, l->ext_family); +} =20 - return model; +unsigned int x86_model(unsigned int sig) +{ + return __x86_model(x86_family(sig), (sig >> 4) & 0xf, (sig >> 16) & 0xf); } EXPORT_SYMBOL_GPL(x86_model); =20 +unsigned int cpuid_model(const struct leaf_0x1_0 *l) +{ + return __x86_model(cpuid_family(l), l->base_model, l->ext_model); +} + unsigned int x86_stepping(unsigned int sig) { return sig & 0xf; --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FA6627FD63 for ; Thu, 5 Jun 2025 19:24:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151486; cv=none; b=QrIIcRiVcr2RX6NkS/bHQqNdXpTAkFdxS9SAdv1YwRVgcHbrk3/dlkJ8l33YoSeRIPxGlT8rG1l4eghpvgwh1ordoi/b4c+Eeo0FDBedaDCJqUJJPMO2gjU4fCffjPKzgqhMzxZMb677iD7PE1Ivr61Nm2Redqsm6dwsBbNTBtw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151486; c=relaxed/simple; bh=lSnfTGNvCCHUD1g3OuwoLvAwB3bAKJBfyXYmqNb6quc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=QjShDOXDlzlkzRFO3qW5rvIHHjx1jfQNPw1nZTr5IOK+/Rx7SALhuF1uZNoi0T3YNjNz9B93LzQKAy5raWZqdJQulegHdLK35bYyS52Xxdid8Xm1Sfud5XzSScZB2+S27Uct3ZTDUkveFFBU6MP5bmlIpc78jp2EYPfcIuQaNa4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ZVBfKGBZ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=SHr1DAqA; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ZVBfKGBZ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="SHr1DAqA" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CGXqbv3TKuxoI3faR1b+5Z5vqE19ecaVzTdKl1HhrNQ=; b=ZVBfKGBZ0I3YNBB5B66WQNzIhp6VDoCYKk1mwQoXzjtV7y60eP3Qp3iHLOZga+1AE7viMM GqNX1EtCfqf5zcOJ5V5XB3HoshOrce3VN55FZlOLAN+Ep6g05bo2TH2DU7li0uA7v4KZ5r LT24yxiOVT9mOj7sjWQhzOnnawc0n8cUaogNgzKTF1eBC15VPQo041tYcnZZJppoGBajni F5fpYQprnU4oRkbdgTfuKzBkFstMAGmJQdfikBlpkU0QtoGFia9zDeR9CfijrA8TswC3vz STmAGoDz/Yf5iZL4BS2jF3iGELoVYby+tQd8ObIEonxX2OC/t1uwIOepGwaKHg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151484; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=CGXqbv3TKuxoI3faR1b+5Z5vqE19ecaVzTdKl1HhrNQ=; b=SHr1DAqAoJUFGR8nOdFBZwVhc3aGvnfsq5Kxu4fceE8yNxvkqRw7mggxowCh95rYRIT8Eb BtjfMAeOKgY0sKDA== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 11/27] x86/cpu: Use parsed CPUID(0x1) Date: Thu, 5 Jun 2025 21:23:40 +0200 Message-ID: <20250605192356.82250-12-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x1) access, instead of a direct CPUID query, at early boot CPU detection code. Beside the centralization benefits of the new CPUID model APIs, this allows using the auto-generated leaf data types and their full C99 bitfields instead of performing ugly bitwise operations on CPUID register output. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index b3408ae2b144..023613698b15 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -896,6 +896,7 @@ void get_cpu_vendor(struct cpuinfo_x86 *c) void cpu_detect(struct cpuinfo_x86 *c) { const struct leaf_0x0_0 *l0 =3D cpuid_leaf(c, 0x0); + const struct leaf_0x1_0 *l1 =3D cpuid_leaf(c, 0x1); =20 c->cpuid_level =3D l0->max_std_leaf; *(u32 *)&c->x86_vendor_id[0] =3D l0->cpu_vendorid_0; @@ -903,17 +904,14 @@ void cpu_detect(struct cpuinfo_x86 *c) *(u32 *)&c->x86_vendor_id[8] =3D l0->cpu_vendorid_2; =20 c->x86 =3D 4; - /* Intel-defined flags: level 0x00000001 */ - if (c->cpuid_level >=3D 0x00000001) { - u32 junk, tfms, cap0, misc; =20 - cpuid(0x00000001, &tfms, &misc, &junk, &cap0); - c->x86 =3D x86_family(tfms); - c->x86_model =3D x86_model(tfms); - c->x86_stepping =3D x86_stepping(tfms); + if (l1) { + c->x86 =3D cpuid_family(l1); + c->x86_model =3D cpuid_model(l1); + c->x86_stepping =3D l1->stepping; =20 - if (cap0 & (1<<19)) { - c->x86_clflush_size =3D ((misc >> 8) & 0xff) * 8; + if (l1->clflush) { + c->x86_clflush_size =3D l1->clflush_size * 8; c->x86_cache_alignment =3D c->x86_clflush_size; } } --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69714280026 for ; Thu, 5 Jun 2025 19:24:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151490; cv=none; b=HRjQBnRRn/UeE3UyfSy4M50rQxVFIWW7QVOPVMMNi2ivwVpsG9yirbS1QPplkSWSVh/IUCFjXkTU1XjSuagnkD2LVc3V7idRO6XqtuieYdFQwAilM9F1+IxwB+WebbUE8WLqUo81rLGRYXivuuiWt8hm2KGJWGOtF6vMxrAv9sw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151490; c=relaxed/simple; bh=kON66gAz7NDVGVg8S0nkOes7rQfGi/wqq84UJvR2Ok0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=JOu4Gd9prXIboVvik/nj9JNVKb2n2EatcvH28rIDqgydZbeQSPnbRJNEN/S+DC4ogm2u1r0UL0Qg1xcLlMHbakwujGwc14iVe74Odn7C2AKwuo/T5x0tHPhoiAgl1Ei2xa56W4Uc6gTrB1uwiS6BUvC+chUtXyML4uDyx7Z/6vY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BUAoFwA/; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=O8nLOFSL; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BUAoFwA/"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="O8nLOFSL" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=h/Bn+rfrcaD/2x6weAGgttt6xgvJMEOc9JijKoPQVYk=; b=BUAoFwA/mgR/4Qr8X6VzcEwlW9Ua/d5YIoGvQTnx+XPtSC2vItUZzCPi5HDZi+LIjku6n7 4KiTx71VBI/zzjkxENIDEU1mhpHP5wYQXl0jr3Z2f0vAtwT5SPtCULMzxfxe91RuIaakFc 3JfbywgxAykYHzCNC3h6z/SMTcjTR0rihwBvA/TACn1nhCO/ESRNBFn8jPcG/pjf4P9FQv 4jEdS1KpxNPbiRbNWuMgnWSfC8e8n8nswR1kb49Q8t8TLPH/Vcup6HErDjgJ77zP8/jvTi 5nZ90lGGb01B957p12La6JecTECl05bA7VtRf/SBdmKh6vBkFd+bT+16JjKZ1A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151487; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=h/Bn+rfrcaD/2x6weAGgttt6xgvJMEOc9JijKoPQVYk=; b=O8nLOFSLhCj76RSCpvRZ6rCBMnIBMzERdxBt7V17NMUOyukYgHYjhQXTNO+Itntdfhp2fl s9ikHjshMtfZA2BQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 12/27] x86/cpuid: Parse CPUID(0x2) Date: Thu, 5 Jun 2025 21:23:41 +0200 Message-ID: <20250605192356.82250-13-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID(0x2) support to the CPUID parser. Keep the leaf marked as invalid at the CPUID table if the whole leaf, or all of its output registers, were malformed. Note, the cpuid_leaf_0x2() logic at will be removed once all the CPUID(0x2) call sites are transformed to the new CPUID model API. References: fe78079ec07f ("x86/cpu: Introduce and use CPUID leaf 0x2 parsin= g helpers") Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 1 + arch/x86/kernel/cpu/cpuid_parser.c | 35 ++++++++++++++++++++++++++++++ arch/x86/kernel/cpu/cpuid_parser.h | 1 + 3 files changed, 37 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index d0f0e6a8a457..7bbf0671cb95 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -215,6 +215,7 @@ struct cpuid_leaves { /* leaf subleaf count */ CPUID_LEAF(0x0, 0, 1); CPUID_LEAF(0x1, 0, 1); + CPUID_LEAF(0x2, 0, 1); CPUID_LEAF(0x80000000, 0, 1); }; =20 diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index e79835a09336..ab06c68e4453 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -22,6 +22,41 @@ static void cpuid_read_generic(const struct cpuid_parse_= entry *e, struct cpuid_r cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); } =20 +static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid= _read_output *output) +{ + union leaf_0x2_regs *regs =3D (union leaf_0x2_regs *)output->regs; + struct leaf_0x2_0 *l2 =3D (struct leaf_0x2_0 *)output->regs; + int invalid_regs =3D 0; + + /* + * All Intel CPUs must report an iteration count of 1. In case of + * bogus hardware, keep the leaf marked as invalid at the CPUID table. + */ + cpuid_read_subleaf(e->leaf, e->subleaf, l2); + if (l2->iteration_count !=3D 0x01) + return; + + /* + * The most significant bit (MSB) of each register must be clear. + * If a register is malformed, replace its descriptors with NULL. + */ + for (int i =3D 0; i < 4; i++) { + if (regs->reg[i].invalid) { + regs->regv[i] =3D 0; + invalid_regs++; + } + } + + /* + * If all the output registers were malformed, keep the leaf marked + * as invalid at the CPUID table. + */ + if (invalid_regs =3D=3D 4) + return; + + output->info->nr_entries =3D 1; +} + static void cpuid_read_0x80000000(const struct cpuid_parse_entry *e, struc= t cpuid_read_output *output) { struct leaf_0x80000000_0 *el0 =3D (struct leaf_0x80000000_0 *)output->reg= s; diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 0c79919a6138..3178e760e2b3 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -96,6 +96,7 @@ struct cpuid_parse_entry { /* Leaf Subleaf Reader function */ \ CPUID_PARSE_ENTRY(0x0, 0, generic), \ CPUID_PARSE_ENTRY(0x1, 0, generic), \ + CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), =20 extern const struct cpuid_parse_entry cpuid_common_parse_entries[]; --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D256A28003E for ; Thu, 5 Jun 2025 19:24:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151493; cv=none; b=b7LWMzzCqloiHW+s5ieuGQ/Cpx8++2V20xF5PLb2Gn5ZuPdubB5dxjQE/idHDn1j28EX5CmSw8JueIO4+2a+QtN/pwffVdcTaU7SwuGJ0/8Dm/NHzLr54Onx6Oug6BL4P1x9rqr7yU5zEWAgfzQIt9N/nkyXrLJvoMINExfJW8E= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151493; c=relaxed/simple; bh=/wOOh7ifW5jvQsoVt3Obs+KAAOm7odpeTZYOfRwXtrQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c0ROLAbPB6YyZpiUPFG3W839PeHf68CmbrlpNu9+qVpmOl44AqzHOJFwu2CS8YgOoxeOpn3A05pSZmja/iAdBG1+Yd1HD8EO/O0K2NXD7XJbG6Son9otHoe4MiXQcLLua3kYpUC4TylOkkY4ZsM5pGujBA+PXpQmiNdGN0U5Kg8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hOjE5B1c; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=FsYzTRpH; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hOjE5B1c"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="FsYzTRpH" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151490; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1S6VKHOLNXsAhJzB2QvGwtufLwN+0p9p7ZPBpXEN1Zw=; b=hOjE5B1clnRwsGZBA3gD3kyfYbtl6nngm0BqPMdIcTq8NquowypjxxcVWm7aU8oWG5+qPc VZ9unzHfDrV7zHgiulEqp3zSCv529/9IR4hkhhuof441HSsf9utebbKABeiJZd63jM6gLh /h4OKZP/MrRyiD3Y1YYjeVaTKdWNX6hxLQnPIoDtmD3PuEM8N2jDISjTQX3dOdwcNupunk yxUdOMC5+CWce2pkHblpF7XEWzQuMYBcBlQVGmV+EEyNpUekwEmep1BYgojh/OgjIRUNan 5Lve5ydEvNybs4sRPqM8OIipEVt5xsiblAzdCwqsBLqnVB2MKLsUK4RHOcnKww== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151490; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1S6VKHOLNXsAhJzB2QvGwtufLwN+0p9p7ZPBpXEN1Zw=; b=FsYzTRpHqK0v3E0hX2VlOMngnXA8DQQbOLb8M8gUuKmoJkxM7OVKLouX4u/t9K+jNLmp6O XTYtmiTO3mHuJCDg== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 13/27] x86/cpuid: Warn once on invalid CPUID(0x2) iteration count Date: Thu, 5 Jun 2025 21:23:42 +0200 Message-ID: <20250605192356.82250-14-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The CPUID(0x2) output includes an "query count" byte where it was supposed to specify the number of CPUID(0x2) subleaf 0 queries needed to extract all of the CPU's cache and TLB descriptors. Per current Intel manuals, all CPUs supporting this leaf "will always" return an iteration count of 1. Since the CPUID parser ignores any CPUID(0x2) output with an invalid iteration counts warn about this once at the kernel log. Do not emit a warning if any of the CPUID(0x2) output registers EAX->EDX, or even all of them, are invalid; i.e., their most significant bit is set. Such a case is architecturally defined and legitimate. References: b5969494c8d8 ("x86/cpu: Remove CPUID leaf 0x2 parsing loop") Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/aBnmy_Bmf-H0wxqz@gmail.com --- arch/x86/kernel/cpu/cpuid_parser.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index ab06c68e4453..4b960b23cab4 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -3,6 +3,8 @@ * Centralized CPUID parser (for populating the system's CPUID tables.) */ =20 +#define pr_fmt(fmt) "x86/cpuid: " fmt + #include #include =20 @@ -33,8 +35,11 @@ static void cpuid_read_0x2(const struct cpuid_parse_entr= y *e, struct cpuid_read_ * bogus hardware, keep the leaf marked as invalid at the CPUID table. */ cpuid_read_subleaf(e->leaf, e->subleaf, l2); - if (l2->iteration_count !=3D 0x01) + if (l2->iteration_count !=3D 0x01) { + pr_warn_once("Ignoring CPUID(0x2) due to invalid iteration count =3D %d", + l2->iteration_count); return; + } =20 /* * The most significant bit (MSB) of each register must be clear. --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AD1CD280312 for ; Thu, 5 Jun 2025 19:24:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151496; cv=none; b=I3OHljSxuYcJy533dSvl5PUXxKh7zzMv2a6cekR0JSIc+W0jAfPVqBXvmOnxR9tsz8GSsxRNZGA5kA0KPUOQ+5bYMwDlR7lrPhhVMv6fqF9j7JtK2cVLU71PszyLB3IXFY6j5C5M/hOzGoO9aiZ77PuereRpRaBmo/JtaRlytZI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151496; c=relaxed/simple; bh=bU9EYIqMXE1W6N++OSgjszY1XEyu/gdXCb/IYPfu2ew=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Zas470Js1CIVY8b7cAnqJTil+UJkdsd8nqW2qiVOwD9APbVTkkpik3A7fmILr+JA0pRRO3pB4ybKLGuPFwHGsoC/DwGaGRcO4ck7rM4mj4xGPqbGy9D1Iq+d2b0lWQykSSSEq87sq1LB8gNdyMPSmbauw3aGDU/0LH5rRML08QQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=F4+KBO1m; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=I776+h7b; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="F4+KBO1m"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="I776+h7b" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151493; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ach8PGqE+vUBqcIRU5YJpA7PFcKh+hh6xzW1+cmwIL0=; b=F4+KBO1mFsXEZ5XReJZdFoR6Rp5f5o2VruWsu4mv/vicA+wN08liqaGBeR5xVwu1M/dSUx wWCigaKPFVFslLuE7x86GWzZGHn3D15ma27bCAj+GYW/wBKO0Pg6wFFYYZTvzM96bWT42H u9FLgD5fviBla/AkHbj77oF8VCbVfDAY0dNvJIr0mrbcGxXQ0OrXhqGMm4awl4UdXzOjsd TLDqw+NAJEgUFL09gpCDipmtV55fqIaIB+6PWgkIM62XQsi+CFtWlThF9+wtDG3E7M3bNI 0JB8JXO8Mi7YTJz/23mv4MpbMVc2tFVxj/zw+wQTDtbpAhML+z8U0ONdCOZccQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151493; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Ach8PGqE+vUBqcIRU5YJpA7PFcKh+hh6xzW1+cmwIL0=; b=I776+h7bSSDL1WgsvVoTnaQ6jiYkugDXUGf2PGyaJh5U7twdjOrRV0UHfwFHW3SUc09ETD bb6pZsLIMIM3qEBg== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 14/27] x86/cpuid: Introduce parsed CPUID(0x2) API Date: Thu, 5 Jun 2025 21:23:43 +0200 Message-ID: <20250605192356.82250-15-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a new iterator macro, for_each_parsed_cpuid_0x2_desc(), for retrieving parsed CPUID(0x2) entries as 1-byte descriptors. Unlike the existing for_each_cpuid_0x2_desc() macro, which operates on directly retrieved CPUID data, the new one takes its input from the centralized CPUID parser. That is, it is expected to be used as: const struct leaf_0x2_table *desc; const struct cpuid_regs *regs; u8 *ptr; regs =3D cpuid_leaf_regs(c, 0x2); // Parsed CPUID access for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { ... } which should replace the older method: const struct leaf_0x2_table *desc; union leaf_0x2_regs regs; u8 *ptr; cpuid_leaf_0x2(®s); // Direct CPUID access for_each_leaf_0x2_desc(regs, ptr, desc) { ... } In the new macro, assert that the passed 'regs' is the same size as a 'union leaf_0x2_regs'. This is necessary since the macro internally casts 'regs' to that union in order to iterate over the CPUID(0x2) output as a 1-byte array. A size equivalence assert is used, instead of a typeof() check, to give callers the freedom to either pass a 'struct cpuid_regs' pointer or a 'struct leaf_0x2_0' pointer, both as returned by the parsed CPUID API at . That size comparison matches what other kernel CPUID do; e.g. cpuid_leaf() and cpuid_leaf_reg() at . Note, put the size equivalence check inside a GNU statement expression, ({..}), so that it can be placed inside the macro's loop initialization. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 35 ++++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index a0c84fbc8fcb..7ee6b4443333 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -281,6 +281,41 @@ static inline void cpuid_leaf_0x2(union leaf_0x2_regs = *regs) _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ _ptr++) =20 +/** + * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors + * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_regs() + * @_ptr: u8 pointer, for macro internal use only + * @_desc: Pointer to parsed descriptor information at each iteration + * + * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers + * @_regs. Provide the parsed information for each descriptor through @_d= esc. + * + * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB + * descriptors, switch on @_desc->t_type. + * + * Example usage for cache descriptors:: + * + * const struct leaf_0x2_table *desc; + * struct cpuid_regs *regs; + * u8 *ptr; + * + * regs =3D cpuid_leaf_regs(c, 0x2); + * if (!regs) { + * // Handle error + * } + * + * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * switch (desc->c_type) { + * ... + * } + * } + */ +#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ + for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ + _ptr =3D &((union leaf_0x2_regs *)(_regs))->desc[1]; \ + _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc =3D &cp= uid_0x2_table[*_ptr]);\ + _ptr++) + /* * CPUID(0x80000006) parsing: */ --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E1541280334 for ; Thu, 5 Jun 2025 19:24:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151500; cv=none; b=JN/H0xVtxb94sgE6ubvvQWt0r64h4vz+N4oG/94+uKFRi9E3nQpWA/z16nJriSNxsw1t/Wrqok4v8NeWVVeMIBuy5GKAPmQ2Rdj6gcIymth3Qm+MaEhvCLspJl4fjIqf2rxwD43J9pzL9IOQE3uspm4pyhZ7tpL3IKA8Dic2TnY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151500; c=relaxed/simple; bh=qNz1iLYzXxbN2lk1k0TKlGVeCiAHYj+yH8k72e66X/g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=EjNcnmyvJ5HcrMGNYP+WKar5LyLcpqLOokduBJhVs17PH4/kXl5IHTza0QuC4bQjfFevODmrxnLCUMwegWDByD/q95fLoBtX2CQGW52W/j52J91SUPP7g1+CUVxcyMj4Sdta7e3PUcdudMnIktbSKefWh9uWpUs26eQs/ezVgG8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=hWPHLiE5; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=GdMI1Qft; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="hWPHLiE5"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="GdMI1Qft" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151497; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lTVNlPfPuV0WuhPUD2xW99Y6GJi+2sofUiXVRrozsf0=; b=hWPHLiE5aTA9b2q5YpZdAmC4pCEBXP5YpOwa+2iRJdWQ7b5ggDyyw2W+GmxFTfnY/Hy3yP qDTgJK8Xk4NKWi7YpptBLL3x0uLoVyqtW4fcH53yO+7USL6JRuO1WuAfZEJkgUKEBuJiFU Snc+Vpp0/G8iZEBNppouQlT5HUcXqh1im8sR9E8+/jCcQAhtJUDMwnI6u04DEDhuPv4V1f ItEKb7VOql+NK1UjynpPknXpuajK9DKqKEcKc3PTY3bbVkbBJAvTsizQKyMqTfj5O4nkBK 2h8tdwLk18Vtn8TxulupG7y+o5unvLysCtClMeH7Yz0PgwFtedfjWUuon1UZZg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151497; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lTVNlPfPuV0WuhPUD2xW99Y6GJi+2sofUiXVRrozsf0=; b=GdMI1QftpTTXVG8VQXcNvuhan8hycTIPilYXCini8lRBhmsq/gWteNGWlb712b7Qp/qWc6 SsqS+o5+NFZtlYDg== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 15/27] x86/cpu: Use parsed CPUID(0x2) Date: Thu, 5 Jun 2025 21:23:44 +0200 Message-ID: <20250605192356.82250-16-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x2) access instead of direct CPUID queries. Remove the max standard CPUID level check since the NULL check of cpuid_leaf_regs()'s result is equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 076eaa41b8c8..5eab9135b144 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -710,14 +710,14 @@ static void intel_tlb_lookup(const struct leaf_0x2_ta= ble *desc) static void intel_detect_tlb(struct cpuinfo_x86 *c) { const struct leaf_0x2_table *desc; - union leaf_0x2_regs regs; + struct cpuid_regs *regs; u8 *ptr; =20 - if (c->cpuid_level < 2) + regs =3D cpuid_leaf_regs(c, 0x2); + if (!regs) return; =20 - cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, desc) + for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95B9C280A4D for ; Thu, 5 Jun 2025 19:25:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151503; cv=none; b=Y+CCD0KUAzhisx6dVJ43FpBzjrV/3c4rcP7gshJMfpzfPMxQVEkXyV4Ap0KcSkBHXwuMxmdIMgguqm1BODzLFIiZB7w8gjVt95iSMcA6y7ehPmxGSt1BZ/Bv9dO7DZxruk0cqRC/+bghx1uwqiGC+sxV2TWEqcIvQSQwF8ZkS2Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151503; c=relaxed/simple; bh=Q6VUb++4XOTCTCjcxAP97gZhJFg//ThEY0Q6wlCmFQg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=htR9q6+GDzSqIomr1gb8UU5lRtZw0DME3b3Erne0kkQZT8P+8dxwyKbrIkfa2CJIgyZypryWMcppphHJJkv/HdNBqpaV0A/zP64GKw2IvDBpKoqFIcj5NIVpRdxzWLEFVUv73p5qIct6+dOCVi9W1uN/AzntSfz+pZIsWB80C9A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=mKjQ8WSp; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=wyIRlaRO; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="mKjQ8WSp"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="wyIRlaRO" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151500; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rmtXB3vSta6fGqJCXxmMRAj9XLGXz6rgjPfCqdr78qY=; b=mKjQ8WSpkZemTMgGl+7sFxkplPjeD3kDN5lMzp4R0n/KxaPslykdvCMRnu6YU28wT6ilif fZ9WPJAJAG89+lclnDuo1tvmilTEi8Wipn7ikUCYTsF+HFk6ZkNw70KyzEVHoQLlKYUT1r 6tyo6MQ9cuGzbfWi0qXntAYxouXUS4MtbJG4XoKAUhfluVhWVDJI0tH6dG+rEnk1+WpP9e Ej6StNIvsF7Ggry02eX5c6JO/eJ30p20GrWO9vBrUpAHoDlk7LgdcOWcb5x8wqlxVK2OHV 64LJqfnZIylE1AtxjExLYCiJ7mH32H9XWgNyKnr6kIbGIbpIszedO0n1kYnpbQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151500; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rmtXB3vSta6fGqJCXxmMRAj9XLGXz6rgjPfCqdr78qY=; b=wyIRlaRO7MYNRZUfAKSdLDCVcyTw3QOuEx97Xwl6cxF0FSFqIIf+47iPrDadORCb1rlLPo vvwyb4If3VCXNHAw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 16/27] x86/cacheinfo: Use parsed CPUID(0x2) Date: Thu, 5 Jun 2025 21:23:45 +0200 Message-ID: <20250605192356.82250-17-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Use parsed CPUID(0x2) access instead of direct CPUID queries. Remove the max standard CPUID level check since the NULL check of cpuid_leaf_regs()'s result is equivalent. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index adfa7e8bb865..39cd6db4f702 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -382,14 +382,14 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) { unsigned int l1i =3D 0, l1d =3D 0, l2 =3D 0, l3 =3D 0; const struct leaf_0x2_table *desc; - union leaf_0x2_regs regs; + struct cpuid_regs *regs; u8 *ptr; =20 - if (c->cpuid_level < 2) + regs =3D cpuid_leaf_regs(c, 0x2); + if (!regs) return; =20 - cpuid_leaf_0x2(®s); - for_each_cpuid_0x2_desc(regs, ptr, desc) { + for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 12DFD281355 for ; Thu, 5 Jun 2025 19:25:04 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151506; cv=none; b=XX1xIMKSkVHh1EFhd0pe38v7CVYHnrfvoarAx7HqYNQlk7R7IpH9ViKpK1fnu3Bi1PPYyVUrKC/j7TmCyzD9t3nGO0ASCw2cwM6PZKEyQ6OCnep+hQ32GQ3araaxAkVKlMEO2cMEUpxT9my+4SXJck+FQn/NPyECfWVD/8iO2eQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151506; c=relaxed/simple; bh=P/frtEZjFeSXKi503tP58VsB8k/DsdL0OrB6nj9NcD0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=meruY2TbgxGH4BA4fLXg5ZjUbKaUDqioR2SL/uAHWb3/qoS6uNAsIQkyloqkzf/buFcEm/nugw5eYVpCy8+6cXpv9Ta2cICFK0Mj/8C6SfOFx4AI9fupwbLuyxPHhsW0MmSqwviCTa6DkIwpz7ZI5Iz3xlosM/swI2rQvacAby4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=f6UhyUR3; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=8VnUhi5O; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="f6UhyUR3"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="8VnUhi5O" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qv3QbtIIkCWi/aPuS7tUL80Ou+8ODVes7Cu5qsAPAc8=; b=f6UhyUR3t9XI4ODFuiotUVxNcFk/xjSCymsSks4m2p4H635YwVOEf+Pjq4dbEdsnCloSRE DmbtIUKpZGFzX6eBP+HLIR986lFQGXz27MAaVYO3+qz8TovIKeyR53roz2wMlYMVzRdq4m 08PZ7WtnZ1z7Qg1poNiXK5LOz+QChOCoP8sNHqmIlN9enmZPm9HdzbamCmSCflMrJrcP6c X/qlJliB6WwO+cyydTv2ptZbsEBaqs2ld9Wq8tou40fw6/ZDGNjzaME14BzqsG7URchkCO 9+i2BkWUm5Zzf/wrlyD1z3tOIMOOBkCOg8UscSyNolskqf4EBp6MZL4w2v0uNg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151503; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qv3QbtIIkCWi/aPuS7tUL80Ou+8ODVes7Cu5qsAPAc8=; b=8VnUhi5O9ArzSWgmiDTpwS10oers4fBPGpWv5FxcOOtQAxsITZ23v54X1I/ajsoo01g/JX SY6D0th7Pv3r/3Dw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 17/27] x86/cpuid: Remove direct CPUID(0x2) query API Date: Thu, 5 Jun 2025 21:23:46 +0200 Message-ID: <20250605192356.82250-18-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" All call sites at x86/cpu and x86/cacheinfo has been switched from direct CPUID(0x2) access to parsed CPUID access. Remove the direct CPUID(0x2) query APIs at : cpuid_leaf_0x2() for_each_cpuid_0x2_desc() Rename the iterator macro: for_each_parsed_cpuid_0x2_desc() back to: for_each_cpuid_0x2_desc() since the "for_each_parsed_.." name and was just chosen to accommodate the transition from direct CPUID(0x2) access to parsed access. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 69 +------------------------------- arch/x86/kernel/cpu/cacheinfo.c | 2 +- arch/x86/kernel/cpu/intel.c | 2 +- 3 files changed, 4 insertions(+), 69 deletions(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 7ee6b4443333..82d36d210930 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -216,73 +216,8 @@ static inline u32 cpuid_base_hypervisor(const char *si= g, u32 leaves) * CPUID(0x2) parsing: */ =20 -/** - * cpuid_leaf_0x2() - Return sanitized CPUID(0x2) register output - * @regs: Output parameter - * - * Query CPUID(0x2) and store its output in @regs. Force set any - * invalid 1-byte descriptor returned by the hardware to zero (the NULL - * cache/TLB descriptor) before returning it to the caller. - * - * Use for_each_cpuid_0x2_desc() to iterate over the register output in - * parsed form. - */ -static inline void cpuid_leaf_0x2(union leaf_0x2_regs *regs) -{ - cpuid_read(0x2, regs); - - /* - * All Intel CPUs must report an iteration count of 1. In case - * of bogus hardware, treat all returned descriptors as NULL. - */ - if (regs->desc[0] !=3D 0x01) { - for (int i =3D 0; i < 4; i++) - regs->regv[i] =3D 0; - return; - } - - /* - * The most significant bit (MSB) of each register must be clear. - * If a register is invalid, replace its descriptors with NULL. - */ - for (int i =3D 0; i < 4; i++) { - if (regs->reg[i].invalid) - regs->regv[i] =3D 0; - } -} - /** * for_each_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descriptors - * @_regs: CPUID(0x2) register output, as returned by cpuid_leaf_0x2() - * @_ptr: u8 pointer, for macro internal use only - * @_desc: Pointer to the parsed CPUID(0x2) descriptor at each iteration - * - * Loop over the 1-byte descriptors in the passed CPUID(0x2) output regist= ers - * @_regs. Provide the parsed information for each descriptor through @_d= esc. - * - * To handle cache-specific descriptors, switch on @_desc->c_type. For TLB - * descriptors, switch on @_desc->t_type. - * - * Example usage for cache descriptors:: - * - * const struct leaf_0x2_table *desc; - * union leaf_0x2_regs regs; - * u8 *ptr; - * - * cpuid_leaf_0x2(®s); - * for_each_cpuid_0x2_desc(regs, ptr, desc) { - * switch (desc->c_type) { - * ... - * } - * } - */ -#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ - for (_ptr =3D &(_regs).desc[1]; \ - _ptr < &(_regs).desc[16] && (_desc =3D &cpuid_0x2_table[*_ptr]); \ - _ptr++) - -/** - * for_each_parsed_cpuid_0x2_desc() - Iterator for parsed CPUID(0x2) descr= iptors * @_regs: Leaf 0x2 register output, as returned by cpuid_leaf_regs() * @_ptr: u8 pointer, for macro internal use only * @_desc: Pointer to parsed descriptor information at each iteration @@ -304,13 +239,13 @@ static inline void cpuid_leaf_0x2(union leaf_0x2_regs= *regs) * // Handle error * } * - * for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + * for_each_cpuid_0x2_desc(regs, ptr, desc) { * switch (desc->c_type) { * ... * } * } */ -#define for_each_parsed_cpuid_0x2_desc(_regs, _ptr, _desc) \ +#define for_each_cpuid_0x2_desc(_regs, _ptr, _desc) \ for (({ static_assert(sizeof(*_regs) =3D=3D sizeof(union leaf_0x2_regs));= }), \ _ptr =3D &((union leaf_0x2_regs *)(_regs))->desc[1]; \ _ptr < &((union leaf_0x2_regs *)(_regs))->desc[16] && (_desc =3D &cp= uid_0x2_table[*_ptr]);\ diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 39cd6db4f702..f837ccdec116 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -389,7 +389,7 @@ static void intel_cacheinfo_0x2(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) { + for_each_cpuid_0x2_desc(regs, ptr, desc) { switch (desc->c_type) { case CACHE_L1_INST: l1i +=3D desc->c_size; break; case CACHE_L1_DATA: l1d +=3D desc->c_size; break; diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 5eab9135b144..06c249110c8b 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -717,7 +717,7 @@ static void intel_detect_tlb(struct cpuinfo_x86 *c) if (!regs) return; =20 - for_each_parsed_cpuid_0x2_desc(regs, ptr, desc) + for_each_cpuid_0x2_desc(regs, ptr, desc) intel_tlb_lookup(desc); } =20 --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D8DA281365 for ; Thu, 5 Jun 2025 19:25:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151509; cv=none; b=qr8yAutw+ltyUDa5p5pyZ1GnTqsC10s1L5LTIqRa96TjRRk/B6xWutkFyJieUSCC1wQvRibFINLEX5sFmWNWAeLq6vUF9056kNJQa87vyKfLF748UcNi/WFFYFZx7PopqjtauLMlnW9SU2OOSD1a5+fgfSX82/TAdN3kR2lbnR8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151509; c=relaxed/simple; bh=+qBsiSSUy1jp5TJAOjQX4DOldglOngbOXvP0Y78UtZs=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=eikQD/Y/eTXb8DCEB61RVs8AYQig0+b+EC7AEflYWcnopY28q3V+c8pGBCSW+pNs5S0lpWede+VPY4MXTWDuKsT/cNljGXy4gYEWEFs5e3bO46AYqulVEkIfN3wKKLvZmu+UIhO7uvOR8FzrctpXpYVZk0GZ7j9zxcl4T4RaP4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=OdZmDhv0; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Ac42tVHg; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="OdZmDhv0"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Ac42tVHg" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151506; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1LVvx7eIEVDJLIVUqt5/zmHhvKagbb+ZKbwzhn6boLs=; b=OdZmDhv0S/p4nfyvazaKvRR/lNJl0UQ2tP7eKAJW/sVRahk6W/9TKII+P4tLUBOuGtbyVH JtFNPWR24P+tARsUFtgGbTD/GcIWLFQkpqd6GEWaQ1xDHXyOFI5aAaBL7WyF52JqBxjfiZ hlCTD8IS0BuOBc+YTIWPi2lDEx6eyIta4ljKrB5aNB7H6oiuWvUcqykZxtEcdBoRWfzXiU 65LWZTmOdKPcLMBTy6X4vi585IKaAk3CIYe+3mBVvHdl1aPsTbhaQUC8bqPWED1U6Ex3PT wZ6QuEOVdvN4YWotn9O9UM4ztlJAZRGQ86lgeVybmRmIv6lOHxPrv5gBXCNawA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151506; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=1LVvx7eIEVDJLIVUqt5/zmHhvKagbb+ZKbwzhn6boLs=; b=Ac42tVHgyXzvVzjLUJce86qVLFvAwuw4DVW/TfiDLMNqiSA5m2DbnP8Jf+1pDzBuMhgBWi zlcRmgGgpAFVwpBQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 18/27] x86/cpuid: Parse deterministic cache parameters CPUID leaves Date: Thu, 5 Jun 2025 21:23:47 +0200 Message-ID: <20250605192356.82250-19-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID parser logic for Intel CPUID(0x4) and AMD CPUID(0x8000001d). Define a single cpuid_read_deterministic_cache() parsing function for both leaves, as both have the same subleaf cache enumeration logic. Introduce __define_cpuid_read_function() macro to avoid code duplication between cpuid_read_generic(), the CPUID parser's default read function, and the new cpuid_read_deterministic_cache() one. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 2 ++ arch/x86/kernel/cpu/cpuid_parser.c | 40 +++++++++++++++++++++++++----- arch/x86/kernel/cpu/cpuid_parser.h | 4 ++- 3 files changed, 39 insertions(+), 7 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 7bbf0671cb95..89c399629e58 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -216,7 +216,9 @@ struct cpuid_leaves { CPUID_LEAF(0x0, 0, 1); CPUID_LEAF(0x1, 0, 1); CPUID_LEAF(0x2, 0, 1); + CPUID_LEAF(0x4, 0, 8); CPUID_LEAF(0x80000000, 0, 1); + CPUID_LEAF(0x8000001d, 0, 8); }; =20 /* diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 4b960b23cab4..1f3b4cd6b411 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -14,15 +14,43 @@ =20 #include "cpuid_parser.h" =20 +/** + * __define_cpuid_read_function() - Generate a CPUID parser read function + * @_suffix: Suffix for the generated function name (full name: cpuid_read= _@_suffix()) + * @_leaf_t: Type to cast the CPUID query output storage pointer + * @_leaf: Name of the CPUID query storage pointer + * @_break_c: Condition to break the CPUID parsing loop, which may referen= ce @_leaf, and + * where @_leaf stores each iteration's CPUID query output. + * + * Define a CPUID parser read function according to the requirements state= d at + * &struct cpuid_parse_entry->read(). + */ +#define __define_cpuid_read_function(_suffix, _leaf_t, _leaf, _break_c) = \ +static void \ +cpuid_read_##_suffix(const struct cpuid_parse_entry *e, struct cpuid_read_= output *output) \ +{ \ + struct _leaf_t *_leaf =3D (struct _leaf_t *)output->regs; \ + \ + static_assert(sizeof(*_leaf) =3D=3D 16); \ + \ + output->info->nr_entries =3D 0; \ + for (int i =3D 0; i < e->maxcnt; i++, _leaf++, output->info->nr_entries++= ) { \ + cpuid_read_subleaf(e->leaf, e->subleaf + i, _leaf); \ + if (_break_c) \ + break; \ + } \ +} + /* * Default CPUID parser read function */ -static void cpuid_read_generic(const struct cpuid_parse_entry *e, struct c= puid_read_output *output) -{ - output->info->nr_entries =3D 0; - for (int i =3D 0; i < e->maxcnt; i++, output->regs++, output->info->nr_en= tries++) - cpuid_read_subleaf(e->leaf, e->subleaf + i, output->regs); -} +__define_cpuid_read_function(generic, cpuid_regs, ignored, false); + +/* + * Shared read function for Intel CPUID leaf 0x4 and AMD CPUID leaf 0x8000= 001d, + * as both have the same subleaf enumeration logic and registers output fo= rmat. + */ +__define_cpuid_read_function(deterministic_cache, leaf_0x4_0, leaf, leaf->= cache_type =3D=3D 0); =20 static void cpuid_read_0x2(const struct cpuid_parse_entry *e, struct cpuid= _read_output *output) { diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index 3178e760e2b3..c79c77547a1d 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -97,7 +97,9 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY(0x0, 0, generic), \ CPUID_PARSE_ENTRY(0x1, 0, generic), \ CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ - CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), + CPUID_PARSE_ENTRY(0x4, 0, deterministic_cache), \ + CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ + CPUID_PARSE_ENTRY(0x8000001d, 0, deterministic_cache), =20 extern const struct cpuid_parse_entry cpuid_common_parse_entries[]; extern const int cpuid_common_parse_entries_size; --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E7854281528 for ; Thu, 5 Jun 2025 19:25:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151512; cv=none; b=AEWp5mdJ6cetBhO+bpWCOFDXhVMN+ZcDNfNuVTM9FsS2x7+Yu/d4nDctfk3fPzBt+NQl8iPNTPOyDLQbIRKa4/gOzO6k04Y+ct3kHz2LfG8EFZ1zIcE1iagEqh47QRKzCuF7REBdKjMw3JUx6klmkLY3RYpl11ucHkkZyqyeoas= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151512; c=relaxed/simple; bh=ZRkIeO0BTcv/lumFRsJ4Atyy4DdC7OCXYFbW9VI5Lig=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=InGuVDpynanD7vvD3aU+eHAdEGwIyUkRFeaWZl9woPjydDQPqx1kLEw04yl9EDZjYd9DVcNpA0NBVyL/3zXXvjpmXwTGM3P1D+l6j07EkqtpKXhpBbT8N73rY7k9rGh1R1Gzao9JpH83oR8fPd4eE94CQ5RmwG0pOKXVjCgnykA= ARC-Authentication-Results: i=1; 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Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 19/27] x86/cacheinfo: Pass a 'struct cpuinfo_x86' refrence to CPUID(0x4) code Date: Thu, 5 Jun 2025 21:23:48 +0200 Message-ID: <20250605192356.82250-20-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Prepare the CPUID(0x4) cache topology code for using parsed CPUID APIs instead of invoking direct CPUID queries. Since such an API requires a 'struct cpuinfo_x86' reference, trickle it from the 's populate_cache_leaves() x86 implementation down to fill_cpuid4_info() and its Intel-specific CPUID(0x4) code. No functional change intended. Suggested-by: Ingo Molnar Signed-off-by: Ahmed S. Darwish Link: https://lore.kernel.org/lkml/aBnEBbDATdE2LTGU@gmail.com --- arch/x86/kernel/cpu/cacheinfo.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f837ccdec116..0ed5dd6d29ef 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,7 +252,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpui= d4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -264,13 +264,13 @@ static int intel_fill_cpuid4_info(int index, struct _= cpuid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) { u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? amd_fill_cpuid4_info(index, id4) : - intel_fill_cpuid4_info(index, id4); + intel_fill_cpuid4_info(c, index, id4); } =20 static int find_num_cache_leaves(struct cpuinfo_x86 *c) @@ -434,7 +434,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) struct _cpuid4_info id4 =3D {}; int ret; =20 - ret =3D intel_fill_cpuid4_info(i, &id4); + ret =3D intel_fill_cpuid4_info(c, i, &id4); if (ret < 0) continue; =20 @@ -618,13 +618,14 @@ int populate_cache_leaves(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci =3D this_cpu_ci->info_list; + struct cpuinfo_x86 *c =3D &cpu_data(cpu); u8 cpu_vendor =3D boot_cpu_data.x86_vendor; struct amd_northbridge *nb =3D NULL; struct _cpuid4_info id4 =3D {}; int idx, ret; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { - ret =3D fill_cpuid4_info(idx, &id4); + ret =3D fill_cpuid4_info(c, idx, &id4); if (ret) return ret; =20 --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A7692820C2 for ; Thu, 5 Jun 2025 19:25:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151515; cv=none; b=Sv3duJGCRnv/1SwSmAB1cvo8cJrb45iCKXCzZmnfol7Hgv4WP+ve5dDH3gR1KVK4xaO28ulUciD4kiFet3eu52MPF65/7IV+hmF3OxYCgML0nhGzjBbh2KFxiPut4Tz5i+UoiuMTNiPl96Mj2Tq1ye6zJx0ddBjYAnoEBYF1DI8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151515; c=relaxed/simple; bh=EbfwzJoyPeSWcXCnGLgeZ+nY1PlcXpzd7l86nm+NKwQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c2Z7T99TI/sQ8cQ5hzuXRZ8/2KbN8z6iJSozHm4V/QdhTPVhLv5iHU+AxUJP9PfzPAjoxeyTnZ4IcB0bFnb8ztqSHcinr3rKLMkKQI9wadziLK1YXSGO+CtDXRSnpgwqPjRlrXD6wIAJSyrAoQLlXdw709aV578v8QHVJEBnP1w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=t1Dee47B; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rb5VgdgK; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="t1Dee47B"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rb5VgdgK" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9tsVcjRsrmz5t1HharsE0QO5QjInb35V8lQCspKnDVw=; b=t1Dee47BGS7nDiyd4IRLmpCVvZmmvUfwghKYc3u1CoxB+B8nEgzhkfTY26h9d2/wTB4Bf6 mIlj7SH0YHSRHuavSmX3pU2ApH7iNBMSydSmMY1h+ea/AqbN92Bv3GPq1M5qnsM3xpKT92 EJz6KpVJ1yVNK09tjaPvuCAe0exiqn9FMtP/FcjeIGjiU1HQP2gTG8P785uvK4927n/2PN VGzPwcadNmwqFjf4e43/ttr4kro1Q8rfWWUHwUnzcty6UWS6FymX1mOv8zzhEyZiWbUDCd 5sUvMpJ2Mj7WrnvqdlgqbGBr9jhqtjS55R56RMlrvLQ4z19LSPr54SD0z6yisw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151512; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=9tsVcjRsrmz5t1HharsE0QO5QjInb35V8lQCspKnDVw=; b=rb5VgdgK9mL7xgMDoytHicFdi7dh3izRxqHCRaxgB8P0J7hAk4Zjxkw7zEls6RHBxeq9Ox /BqeqYktawEfTTBA== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 20/27] x86/cacheinfo: Use parsed CPUID(0x4) Date: Thu, 5 Jun 2025 21:23:49 +0200 Message-ID: <20250605192356.82250-21-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the Intel CPUID(0x4) cacheinfo logic to use parsed CPUID access instead of issuing direct CPUID queries. Use the parsed CPUID access macro: cpuid_subleaf_count(c, 0x4) to determine the number of Intel CPUID(0x4) cache leaves instead of calling find_num_cache_leaves(), which internally issues direct CPUID queries. Since find_num_cache_leaves() is no longer needed for Intel code paths, make it AMD-specific. Rename it to amd_find_num_cache_leaves() and remove its Intel CPUID(0x4) logic. Adjust the AMD paths accordingly. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 31 ++++++++++++++----------------- 1 file changed, 14 insertions(+), 17 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 0ed5dd6d29ef..07f0883f9fbe 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -252,16 +252,14 @@ static int amd_fill_cpuid4_info(int index, struct _cp= uid4_info *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(struct cpuinfo_x86 *unused, int index, s= truct _cpuid4_info *id4) +static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; - u32 ignored; - - cpuid_count(4, index, &eax.full, &ebx.full, &ecx.full, &ignored); + const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x4, index); =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, + (union _cpuid4_leaf_eax)(regs->eax), + (union _cpuid4_leaf_ebx)(regs->ebx), + (union _cpuid4_leaf_ecx)(regs->ecx)); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -273,17 +271,16 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf intel_fill_cpuid4_info(c, index, id4); } =20 -static int find_num_cache_leaves(struct cpuinfo_x86 *c) +static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) { - unsigned int eax, ebx, ecx, edx, op; union _cpuid4_leaf_eax cache_eax; + unsigned int eax, ebx, ecx, edx; int i =3D -1; =20 - /* Do a CPUID(op) loop to calculate num_cache_leaves */ - op =3D (c->x86_vendor =3D=3D X86_VENDOR_AMD || c->x86_vendor =3D=3D X86_V= ENDOR_HYGON) ? 0x8000001d : 4; + /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ do { ++i; - cpuid_count(op, i, &eax, &ebx, &ecx, &edx); + cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); cache_eax.full =3D eax; } while (cache_eax.split.type !=3D CTYPE_NULL); return i; @@ -313,7 +310,7 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u= 16 die_id) * of threads sharing the L3 cache. */ u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; - u32 llc_index =3D find_num_cache_leaves(c) - 1; + u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; =20 cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); if (eax) @@ -344,7 +341,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -353,7 +350,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D amd_find_num_cache_leaves(c); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, @@ -425,7 +422,7 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) * that the number of leaves has been previously initialized. */ if (!ci->num_leaves) - ci->num_leaves =3D find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x4); =20 if (!ci->num_leaves) return false; --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3505C283120 for ; Thu, 5 Jun 2025 19:25:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151519; cv=none; b=EH4IVM0U/3PSonou6CRjFsS9RWnvhYD3tTkOLTbyjduIx22T4XkGAvXdE3ncNOj4MxOJ7mBiEg+KaZorVQ0OrWfPHgS6aBGX7809QjoFrn/eTNWU/+/REEZIVkTSfWLUTiMsUsLZgoLoNPhhn79nS60810VG4WeiYWKdJPwbPV0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151519; c=relaxed/simple; bh=FPi0T+ZPHVxFlKBJeZhvqtH99ssopk9ydCy7etjY6jM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Vs9ErOK6f++ANI+lESiEpalGxVO7e8FEb2yqM0cHO8aEJiSGolwXZxyOC8nyy8RVilrnB9XU3Q556Omnpx2r+dISLDl934x/gDzEm2ymbmN3dYBdwc9VMqINIDDGAhiHxbSCcADyxDmEnaBUUn39VYGpJh5E5iUotJfUMIiM6js= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=irqk510j; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=0AtAZ6AN; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="irqk510j"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="0AtAZ6AN" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151515; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mjuF6lOnbxM2mnXkJdbZYdkl6Gf4g+uakMCPx4X7vT8=; b=irqk510jsC8KH0glDWs0hrZ/GSVgUV/VLtlyRnc5CWYm3c6CIq/47AfYvLcq7tFsf4II9c s0OgW1TTIVvQLlRgQAM3Jb1NiQ2x711o/1s19P0vBHM6sLk9/L4VQOG+gi5eDdP7STxcqN V1hNCJ4+Nz09FbTB71/N8wYY38/VPi5thWZtn3okk8iLfEmTHQ6EFjFtK4bfriTPmaDCwV 6iOIlYW8Q1ANqofadaJSSdnc7qBLz0VLFCKbIPiORq99LRNNebawv6knC+eP/SW+7KMDFM TWmjYrWWrpSep9Zy9l8XF5v2D7oyhUE9ppapcDZgt5LCOc02Zt6PPqWc0zc4cw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151515; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=mjuF6lOnbxM2mnXkJdbZYdkl6Gf4g+uakMCPx4X7vT8=; b=0AtAZ6ANQyFCmflG9wp9nNV7q7tpXF/UE3jr/rVBf70UooSJBDMv7t6J+FYe54C5wYYVfr s5+TQsREPR7jsbCQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 21/27] x86/cacheinfo: Use parsed CPUID(0x8000001d) Date: Thu, 5 Jun 2025 21:23:50 +0200 Message-ID: <20250605192356.82250-22-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor the AMD CPUID(0x8000001d) cacheinfo logic to use the parsed CPUID API instead of issuing direct CPUID queries. Beside CPUID data centralization benefits, this allows using the auto-generated 'struct cpuid_0x8000001d_0' data type with its full C99 bitfields instead of doing ugly bitwise operations. Since parsed CPUID access requires a 'struct cpuinfo_x86' reference, trickle it down to relevant functions. Use the parsed CPUID API: cpuid_subleaf_count(c, 0x8000001d) to find the number of cache leaves, thus replacing amd_find_num_cache_leaves() and its direct CPUID queries. Drop that function entirely as it is no longer needed. For now, keep using the 'union _cpuid4_leaf_eax/ebx/ecx' structures as they are required by the AMD CPUID(0x4) emulation code paths. A follow up commit will replace them with equivalents. Note, for below code: cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); if (eax) num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; if (num_sharing_cache) { int index_msb =3D get_count_order(num_sharing_cache); ... } it is replaced with: const struct leaf_0x8000001d_0 *leaf =3D cpuid_subleaf_index(c, 0x8000001d, llc_index); if (leaf) { int index_msb =3D get_count_order(l->num_threads_sharing + 1); ... } The "if (leaf)" check is sufficient since the parsed CPUID API returns NULL if the leaf is out of range (> max CPU extended leaf) or if the 'llc_index' is out of range. An out of range LLC index is equivalent to "EAX.cache_type =3D=3D 0" in the original code, making the logic match. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 47 +++++++++++---------------------- 1 file changed, 16 insertions(+), 31 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 07f0883f9fbe..05a3fbd0d849 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -237,16 +237,19 @@ static int cpuid4_info_fill_done(struct _cpuid4_info = *id4, union _cpuid4_leaf_ea return 0; } =20 -static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4) +static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _= cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; union _cpuid4_leaf_ecx ecx; - u32 ignored; =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) - cpuid_count(0x8000001d, index, &eax.full, &ebx.full, &ecx.full, &ignored= ); - else + if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) { + const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x8000001d= , index); + + eax.full =3D regs->eax; + ebx.full =3D regs->ebx; + ecx.full =3D regs->ecx; + } else legacy_amd_cpuid4(index, &eax, &ebx, &ecx); =20 return cpuid4_info_fill_done(id4, eax, ebx, ecx); @@ -267,25 +270,10 @@ static int fill_cpuid4_info(struct cpuinfo_x86 *c, in= t index, struct _cpuid4_inf u8 cpu_vendor =3D boot_cpu_data.x86_vendor; =20 return (cpu_vendor =3D=3D X86_VENDOR_AMD || cpu_vendor =3D=3D X86_VENDOR_= HYGON) ? - amd_fill_cpuid4_info(index, id4) : + amd_fill_cpuid4_info(c, index, id4) : intel_fill_cpuid4_info(c, index, id4); } =20 -static int amd_find_num_cache_leaves(struct cpuinfo_x86 *c) -{ - union _cpuid4_leaf_eax cache_eax; - unsigned int eax, ebx, ecx, edx; - int i =3D -1; - - /* Do a CPUID(0x8000001d) loop to calculate num_cache_leaves */ - do { - ++i; - cpuid_count(0x8000001d, i, &eax, &ebx, &ecx, &edx); - cache_eax.full =3D eax; - } while (cache_eax.split.type !=3D CTYPE_NULL); - return i; -} - /* * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist. */ @@ -309,15 +297,12 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c,= u16 die_id) * Newer families: LLC ID is calculated from the number * of threads sharing the L3 cache. */ - u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; - u32 llc_index =3D amd_find_num_cache_leaves(c) - 1; - - cpuid_count(0x8000001d, llc_index, &eax, &ebx, &ecx, &edx); - if (eax) - num_sharing_cache =3D ((eax >> 14) & 0xfff) + 1; + u32 llc_index =3D cpuid_subleaf_count(c, 0x8000001d) - 1; + const struct leaf_0x8000001d_0 *leaf =3D + cpuid_subleaf_index(c, 0x8000001d, llc_index); =20 - if (num_sharing_cache) { - int index_msb =3D get_count_order(num_sharing_cache); + if (leaf) { + int index_msb =3D get_count_order(leaf->num_threads_sharing + 1); =20 c->topo.llc_id =3D c->topo.apicid >> index_msb; } @@ -341,7 +326,7 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D amd_find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); else if (c->extended_cpuid_level >=3D 0x80000006) ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; } @@ -350,7 +335,7 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - ci->num_leaves =3D amd_find_num_cache_leaves(c); + ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); } =20 static void intel_cacheinfo_done(struct cpuinfo_x86 *c, unsigned int l3, --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B613628312C for ; Thu, 5 Jun 2025 19:25:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151522; cv=none; b=H/xiepER+TevZ5U5jhUCt5I96bQTB8OUehvk9suIMb9UgC8KumnG6fGfp80yOPvo5DA/Kzt/XvorJIRghbrS2KNuu8L4LZN/HkRMk1DFLIi6V2sG3P4XW153J8y7B8CfdafXiOKwG261L3AbTpqNAtGOIw3q6K2n888fpqbayN0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151522; c=relaxed/simple; bh=STapveQm26BuKwcv5pdhoVZEubsnxFFLXX5Dy33HG/s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=FutyZUudYKPy7BT9oyzm5EOk5/FiVZ97fOB4URg3Rh9DGAZFML0sqFvbeNRzPA07WAHZbPACCN5k+WSSFeOORjmqdATZX70HLoSfWmOTh/8lVvzRQEUPrKhFMxigY4XAhb9KKJSsj8aFGeea4/VpGiOkRHxHCx1XmJSEqVg2/bM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=fYKpV+XU; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9c57+W2t; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="fYKpV+XU"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9c57+W2t" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151519; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jDICetuUOtKlClQz0zuD5XW28Xt/po6NkLIRVVNMY4o=; b=fYKpV+XU7Mc3asLYtSRx8az7KhZEghUPfgBNOV/bmwzcgeCG8TrsrwqaD9n/1zlHzSnuVj auXNjXkESQXnUbCsvZ5BZQZYyNSBakZbpPLgD6ZkDRuUVdw6VfH0V7c3LWBeOvCpMpBV5Y gohomSoCrWAIps1ET2U263W2Z2X8TexQb3SZ1Ca44PlPFOxWH/vNxN6emRoqNk8rnGIVHQ Zyw/o6wASCkDR+aYEvmuFrjbpXSNNPSQISX3GHYDUTkArYcmSJDuo4yeySrValrPU9A+Bi X+H+uO+YtSy5q1a1ETIarX7h2aqJWw0WPcQJqgeuMyUaTddEa4cJgHWoCrKDxQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151519; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=jDICetuUOtKlClQz0zuD5XW28Xt/po6NkLIRVVNMY4o=; b=9c57+W2toulGiDF2rdWj43AAZ5A1gUkQTihYU0AixJ/EARqj1M9KTrqBClgBEbV3Mn7QRm 0E3J6IKsiVDSsnCQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 22/27] x86/cpuid: Parse CPUID(0x80000005) and CPUID(0x80000006) Date: Thu, 5 Jun 2025 21:23:51 +0200 Message-ID: <20250605192356.82250-23-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parse AMD cacheinfo CPUID(0x80000005) and CPUID(0x80000006), if available, using the generic CPUID parser read function cpuid_read_generic(). The x86/cacheinfo AMD CPUID(0x4)-emulation logic will be swithced next to the parsed CPUID table APIs instead of invoking direct CPUID queries. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 2 ++ arch/x86/kernel/cpu/cpuid_parser.h | 2 ++ 2 files changed, 4 insertions(+) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 89c399629e58..63d2569e2821 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -218,6 +218,8 @@ struct cpuid_leaves { CPUID_LEAF(0x2, 0, 1); CPUID_LEAF(0x4, 0, 8); CPUID_LEAF(0x80000000, 0, 1); + CPUID_LEAF(0x80000005, 0, 1); + CPUID_LEAF(0x80000006, 0, 1); CPUID_LEAF(0x8000001d, 0, 8); }; =20 diff --git a/arch/x86/kernel/cpu/cpuid_parser.h b/arch/x86/kernel/cpu/cpuid= _parser.h index c79c77547a1d..d9bb970c308f 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.h +++ b/arch/x86/kernel/cpu/cpuid_parser.h @@ -99,6 +99,8 @@ struct cpuid_parse_entry { CPUID_PARSE_ENTRY(0x2, 0, 0x2), \ CPUID_PARSE_ENTRY(0x4, 0, deterministic_cache), \ CPUID_PARSE_ENTRY(0x80000000, 0, 0x80000000), \ + CPUID_PARSE_ENTRY(0x80000005, 0, generic), \ + CPUID_PARSE_ENTRY(0x80000006, 0, generic), \ CPUID_PARSE_ENTRY(0x8000001d, 0, deterministic_cache), =20 extern const struct cpuid_parse_entry cpuid_common_parse_entries[]; --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCB1D283680 for ; Thu, 5 Jun 2025 19:25:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151525; cv=none; b=VcjWsPmN2bCBBnKagsC7Xt7H+i5vfZWCNUcamkhvlB84KPQ1zlEeLL7XZKifhGFxgtlmfWZ+xkG/Ye4EIObIRoT9U3aqhDDOJhRXRxnNO8qC0JWly3fROkS9i+uYb36SnXjoMWirfZAuTQhKcoJKiWJKVcNOeh87vTSgHAomCCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151525; c=relaxed/simple; bh=o474ANeWJVZlzcrSMV5Ed/SZ1EjEIgzsMfOO8j2h6aQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=c6sEx2Lo4mafP/byHwbHlwtGrXtSlir3v4Xnje2eGT01DzpklqSIdcUbfpMrmIasFGQQrbbmdLUmMUEuXwRqvXYY5IrZk91wOEipBxi800rpL9SWexDuD9xU0mn2PkYe+hKojjEco2zBmeIXZXoT16JEnxV5HoSXoAd7TVWSgsk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=cRWTMO1L; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=+aDKZt/t; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="cRWTMO1L"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="+aDKZt/t" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151522; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2ec7o83d4fyhY5AOtDVdz8zKCDhFmAcZqf5S8EoVtgQ=; b=cRWTMO1LxCjU9xjFW0fWWzlR8vs8W6D4WlhHsmyPpSW64ZbsmpTvuTlP8X5fa1JPgMnrlQ g+vg7Pi6VkFGQ7PKiqh2GrM1RhetCL1hWRUDx3NB0ic6npKo+ADxpOJrXKYYju8Rv9MpPo SUGk9rcltd9nzJnbNUe+ppwpkSHuSyWgCbu+PMcK3XEqSDhj/ayruTm0cGwgZHOLwMYfHt j+9orX2+W4yKrHUdhoKZUnQCT8jBs1Yy9p5tuNiUi1Bit7fE+47PF2MbaRrJ8gKxDNSgN4 leZGofn3kKlhxY4QN/zZq0Oumul2TXLgRN7GhjQ0Ha5j6LiFyNY80qjn86pFXA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151522; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=2ec7o83d4fyhY5AOtDVdz8zKCDhFmAcZqf5S8EoVtgQ=; b=+aDKZt/tJRRMTF/EyaKRJb3BpDswF7nBxAF+pzUYZ9U8SLePS/AB5/bZ82FSC7lwCR1RKF qcNwyNk7N5+tXrBA== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 23/27] x86/cacheinfo: Use auto-generated data types Date: Thu, 5 Jun 2025 21:23:52 +0200 Message-ID: <20250605192356.82250-24-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(0x4) emulation logic, use the auto-generated data type: struct leaf_0x4_0 instead of the manually-defined: union _cpuid4_leaf_{eax,ebx,ecx} ones. Remove such unions entirely as they are no longer used. Signed-off-by: Ahmed S. Darwish Link: https://gitlab.com/x86-cpuid.org/x86-cpuid-db --- arch/x86/kernel/cpu/cacheinfo.c | 130 +++++++++++--------------------- 1 file changed, 42 insertions(+), 88 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index 05a3fbd0d849..f0540cba4bd4 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -41,39 +41,8 @@ enum _cache_type { CTYPE_UNIFIED =3D 3 }; =20 -union _cpuid4_leaf_eax { - struct { - enum _cache_type type :5; - unsigned int level :3; - unsigned int is_self_initializing :1; - unsigned int is_fully_associative :1; - unsigned int reserved :4; - unsigned int num_threads_sharing :12; - unsigned int num_cores_on_die :6; - } split; - u32 full; -}; - -union _cpuid4_leaf_ebx { - struct { - unsigned int coherency_line_size :12; - unsigned int physical_line_partition :10; - unsigned int ways_of_associativity :10; - } split; - u32 full; -}; - -union _cpuid4_leaf_ecx { - struct { - unsigned int number_of_sets :32; - } split; - u32 full; -}; - struct _cpuid4_info { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + struct leaf_0x4_0 regs; unsigned int id; unsigned long size; }; @@ -148,17 +117,14 @@ static const unsigned short assocs[] =3D { static const unsigned char levels[] =3D { 1, 1, 2, 3 }; static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 -static void legacy_amd_cpuid4(int index, union _cpuid4_leaf_eax *eax, - union _cpuid4_leaf_ebx *ebx, union _cpuid4_leaf_ecx *ecx) +static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs) { unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; union l1_cache l1i, l1d, *l1; union l2_cache l2; union l3_cache l3; =20 - eax->full =3D 0; - ebx->full =3D 0; - ecx->full =3D 0; + *regs =3D (struct leaf_0x4_0){ }; =20 cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); @@ -204,65 +170,53 @@ static void legacy_amd_cpuid4(int index, union _cpuid= 4_leaf_eax *eax, return; } =20 - eax->split.is_self_initializing =3D 1; - eax->split.type =3D types[index]; - eax->split.level =3D levels[index]; - eax->split.num_threads_sharing =3D 0; - eax->split.num_cores_on_die =3D topology_num_cores_per_package(); + regs->cache_self_init =3D 1; + regs->cache_type =3D types[index]; + regs->cache_level =3D levels[index]; + regs->num_threads_sharing =3D 0; + regs->num_cores_on_die =3D topology_num_cores_per_package(); =20 if (assoc =3D=3D AMD_CPUID4_FULLY_ASSOCIATIVE) - eax->split.is_fully_associative =3D 1; + regs->fully_associative =3D 1; =20 - ebx->split.coherency_line_size =3D line_size - 1; - ebx->split.ways_of_associativity =3D assoc - 1; - ebx->split.physical_line_partition =3D lines_per_tag - 1; - ecx->split.number_of_sets =3D (size_in_kb * 1024) / line_size / - (ebx->split.ways_of_associativity + 1) - 1; + regs->cache_linesize =3D line_size - 1; + regs->cache_nways =3D assoc - 1; + regs->cache_npartitions =3D lines_per_tag - 1; + regs->cache_nsets =3D (size_in_kb * 1024) / line_size / + (regs->cache_nways + 1) - 1; } =20 -static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_l= eaf_eax eax, - union _cpuid4_leaf_ebx ebx, union _cpuid4_leaf_ecx ecx) +static int cpuid4_info_fill_done(struct _cpuid4_info *id4, const struct le= af_0x4_0 *regs) { - if (eax.split.type =3D=3D CTYPE_NULL) + if (regs->cache_type =3D=3D CTYPE_NULL) return -EIO; =20 - id4->eax =3D eax; - id4->ebx =3D ebx; - id4->ecx =3D ecx; - id4->size =3D (ecx.split.number_of_sets + 1) * - (ebx.split.coherency_line_size + 1) * - (ebx.split.physical_line_partition + 1) * - (ebx.split.ways_of_associativity + 1); + id4->regs =3D *regs; + id4->size =3D (regs->cache_nsets + 1) * + (regs->cache_linesize + 1) * + (regs->cache_npartitions + 1) * + (regs->cache_nways + 1); =20 return 0; } =20 static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _= cpuid4_info *id4) { - union _cpuid4_leaf_eax eax; - union _cpuid4_leaf_ebx ebx; - union _cpuid4_leaf_ecx ecx; + struct leaf_0x4_0 regs; =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) { - const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x8000001d= , index); - - eax.full =3D regs->eax; - ebx.full =3D regs->ebx; - ecx.full =3D regs->ecx; - } else - legacy_amd_cpuid4(index, &eax, &ebx, &ecx); + if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) + regs =3D *(struct leaf_0x4_0 *)cpuid_subleaf_index(c, 0x8000001d, index); + else + legacy_amd_cpuid4(index, ®s); =20 - return cpuid4_info_fill_done(id4, eax, ebx, ecx); + return cpuid4_info_fill_done(id4, ®s); } =20 static int intel_fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct= _cpuid4_info *id4) { - const struct cpuid_regs *regs =3D cpuid_subleaf_index_regs(c, 0x4, index); + const struct leaf_0x4_0 *regs =3D cpuid_subleaf_index(c, 0x4, index); =20 - return cpuid4_info_fill_done(id4, - (union _cpuid4_leaf_eax)(regs->eax), - (union _cpuid4_leaf_ebx)(regs->ebx), - (union _cpuid4_leaf_ecx)(regs->ecx)); + return cpuid4_info_fill_done(id4, regs); } =20 static int fill_cpuid4_info(struct cpuinfo_x86 *c, int index, struct _cpui= d4_info *id4) @@ -388,7 +342,7 @@ static unsigned int calc_cache_topo_id(struct cpuinfo_x= 86 *c, const struct _cpui unsigned int num_threads_sharing; int index_msb; =20 - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; index_msb =3D get_count_order(num_threads_sharing); return c->topo.apicid & ~((1 << index_msb) - 1); } @@ -420,11 +374,11 @@ static bool intel_cacheinfo_0x4(struct cpuinfo_x86 *c) if (ret < 0) continue; =20 - switch (id4.eax.split.level) { + switch (id4.regs.cache_level) { case 1: - if (id4.eax.split.type =3D=3D CTYPE_DATA) + if (id4.regs.cache_type =3D=3D CTYPE_DATA) l1d =3D id4.size / 1024; - else if (id4.eax.split.type =3D=3D CTYPE_INST) + else if (id4.regs.cache_type =3D=3D CTYPE_INST) l1i =3D id4.size / 1024; break; case 2: @@ -485,7 +439,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } else if (boot_cpu_has(X86_FEATURE_TOPOEXT)) { unsigned int apicid, nshared, first, last; =20 - nshared =3D id4->eax.split.num_threads_sharing + 1; + nshared =3D id4->regs.num_threads_sharing + 1; apicid =3D cpu_data(cpu).topo.apicid; first =3D apicid - (apicid % nshared); last =3D first + nshared - 1; @@ -532,7 +486,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int = index, } =20 ci =3D this_cpu_ci->info_list + index; - num_threads_sharing =3D 1 + id4->eax.split.num_threads_sharing; + num_threads_sharing =3D 1 + id4->regs.num_threads_sharing; =20 cpumask_set_cpu(cpu, &ci->shared_cpu_map); if (num_threads_sharing =3D=3D 1) @@ -559,13 +513,13 @@ static void ci_info_init(struct cacheinfo *ci, const = struct _cpuid4_info *id4, { ci->id =3D id4->id; ci->attributes =3D CACHE_ID; - ci->level =3D id4->eax.split.level; - ci->type =3D cache_type_map[id4->eax.split.type]; - ci->coherency_line_size =3D id4->ebx.split.coherency_line_size + 1; - ci->ways_of_associativity =3D id4->ebx.split.ways_of_associativity + 1; + ci->level =3D id4->regs.cache_level; + ci->type =3D cache_type_map[id4->regs.cache_type]; + ci->coherency_line_size =3D id4->regs.cache_linesize + 1; + ci->ways_of_associativity =3D id4->regs.cache_nways + 1; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151525; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NDLgExsVbLhKJ5840XSmyp+63ZOIMoDXGAvTIqWxPMo=; b=HEeCKMDN07oEQSap7YfAcos9tBOzarjGbe+XwkQNeCqARqO3HUoUMcFLZAkj6xx66z4W5A Aw40J4rD0dDEYgeVzxJJrQ5pwK+xK7L6fw/u7f6gADOJj2tdQfL4v8Q45WOXI+FEGVXsAk AiKNIjk0BTdwr2nJ9pijKM1PMWCaHBxrAz+VJ1ClQPhzOlelSR8xU8rwInSylpKhDcb73M qNg/Pf1kqfx8+GiJHDZhhKu8SNPq3z6zIhvpa5vyylLL66yffy/fpJydAAq65+WmnYCtGa CQ2hO1u9jeif44MaguttRyguCY6w6BT9eiByV1UrrCnJI1U8Dg7eiLSUHzhkmw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151525; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=NDLgExsVbLhKJ5840XSmyp+63ZOIMoDXGAvTIqWxPMo=; b=CxCsDYcgrV1olxIT2Y1zS+ti7mPyTdHuyAB5MIMOPE6kr7DtHr7/y5cGRKy6woX5P22ATX jOkNZKLtwvEu9iBw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 24/27] x86/cacheinfo: Use parsed CPUID(0x80000005) and CPUID(0x80000006) Date: Thu, 5 Jun 2025 21:23:53 +0200 Message-ID: <20250605192356.82250-25-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" For the AMD CPUID(0x4)-emulation logic, use parsed CPUID(0x80000005) and CPUID(0x80000006) APID access instead of invoking direct CPUID queries. Beside centralizing CPUID access, this allows using the auto-generated 'struct leaf_0x80000005_0' and 'struct leaf_0x80000006_0' data types. Remove the 'union {l1,l2,l3}_cache' definitions as they are no longer needed. Note, the expression: ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; is replaced with: ci->num_leaves =3D cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3; which is the same logic, since the 'l3_assoc' bitfield is 4 bits wide at EDX offset 12. Per AMD manuals, an L3 associativity of zero implies the absence of L3 cache on the CPU. While at it, separate the 'Fallback AMD CPUID(0x4) emulation' comment from the '@AMD_L2_L3_INVALID_ASSOC' one, since the former acts as a source code section header. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 105 ++++++++++++-------------------- 1 file changed, 40 insertions(+), 65 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index f0540cba4bd4..de8e7125eedd 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -56,47 +56,17 @@ static const enum cache_type cache_type_map[] =3D { }; =20 /* - * Fallback AMD CPUID(0x4) emulation + * Fallback AMD CPUID(0x4) emulation: * AMD CPUs with TOPOEXT can just use CPUID(0x8000001d) - * + */ + +/* * @AMD_L2_L3_INVALID_ASSOC: cache info for the respective L2/L3 cache sho= uld * be determined from CPUID(0x8000001d) instead of CPUID(0x80000006). */ - #define AMD_CPUID4_FULLY_ASSOCIATIVE 0xffff #define AMD_L2_L3_INVALID_ASSOC 0x9 =20 -union l1_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :8; - unsigned assoc :8; - unsigned size_in_kb :8; - }; - unsigned int val; -}; - -union l2_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :4; - unsigned assoc :4; - unsigned size_in_kb :16; - }; - unsigned int val; -}; - -union l3_cache { - struct { - unsigned line_size :8; - unsigned lines_per_tag :4; - unsigned assoc :4; - unsigned res :2; - unsigned size_encoded :14; - }; - unsigned int val; -}; - /* L2/L3 associativity mapping */ static const unsigned short assocs[] =3D { [1] =3D 1, @@ -117,50 +87,52 @@ static const unsigned short assocs[] =3D { static const unsigned char levels[] =3D { 1, 1, 2, 3 }; static const unsigned char types[] =3D { 1, 2, 3, 3 }; =20 -static void legacy_amd_cpuid4(int index, struct leaf_0x4_0 *regs) +static void legacy_amd_cpuid4(struct cpuinfo_x86 *c, int index, struct lea= f_0x4_0 *regs) { - unsigned int dummy, line_size, lines_per_tag, assoc, size_in_kb; - union l1_cache l1i, l1d, *l1; - union l2_cache l2; - union l3_cache l3; + const struct leaf_0x80000005_0 *el5 =3D cpuid_leaf(c, 0x80000005); + const struct leaf_0x80000006_0 *el6 =3D cpuid_leaf(c, 0x80000006); + const struct cpuid_regs *el5_raw =3D (const struct cpuid_regs *)el5; + unsigned int line_size, lines_per_tag, assoc, size_in_kb; =20 *regs =3D (struct leaf_0x4_0){ }; =20 - cpuid(0x80000005, &dummy, &dummy, &l1d.val, &l1i.val); - cpuid(0x80000006, &dummy, &dummy, &l2.val, &l3.val); - - l1 =3D &l1d; switch (index) { - case 1: - l1 =3D &l1i; - fallthrough; case 0: - if (!l1->val) + if (!el5 || !el5_raw->ecx) return; =20 - assoc =3D (l1->assoc =3D=3D 0xff) ? AMD_CPUID4_FULLY_ASSOCIATIVE : l1->= assoc; - line_size =3D l1->line_size; - lines_per_tag =3D l1->lines_per_tag; - size_in_kb =3D l1->size_in_kb; + assoc =3D el5->l1_dcache_assoc; + line_size =3D el5->l1_dcache_line_size; + lines_per_tag =3D el5->l1_dcache_nlines; + size_in_kb =3D el5->l1_dcache_size_kb; + break; + case 1: + if (!el5 || !el5_raw->edx) + return; + + assoc =3D el5->l1_icache_assoc; + line_size =3D el5->l1_icache_line_size; + lines_per_tag =3D el5->l1_icache_nlines; + size_in_kb =3D el5->l1_icache_size_kb; break; case 2: - if (!l2.assoc || l2.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) + if (!el6 || !el6->l2_assoc || el6->l2_assoc =3D=3D AMD_L2_L3_INVALID_ASS= OC) return; =20 /* Use x86_cache_size as it might have K7 errata fixes */ - assoc =3D assocs[l2.assoc]; - line_size =3D l2.line_size; - lines_per_tag =3D l2.lines_per_tag; + assoc =3D assocs[el6->l2_assoc]; + line_size =3D el6->l2_line_size; + lines_per_tag =3D el6->l2_nlines; size_in_kb =3D __this_cpu_read(cpu_info.x86_cache_size); break; case 3: - if (!l3.assoc || l3.assoc =3D=3D AMD_L2_L3_INVALID_ASSOC) + if (!el6 || !el6->l3_assoc || el6->l3_assoc =3D=3D AMD_L2_L3_INVALID_ASS= OC) return; =20 - assoc =3D assocs[l3.assoc]; - line_size =3D l3.line_size; - lines_per_tag =3D l3.lines_per_tag; - size_in_kb =3D l3.size_encoded * 512; + assoc =3D assocs[el6->l3_assoc]; + line_size =3D el6->l3_line_size; + lines_per_tag =3D el6->l3_nlines; + size_in_kb =3D el6->l3_size_range * 512; if (boot_cpu_has(X86_FEATURE_AMD_DCM)) { size_in_kb =3D size_in_kb >> 1; assoc =3D assoc >> 1; @@ -170,6 +142,10 @@ static void legacy_amd_cpuid4(int index, struct leaf_0= x4_0 *regs) return; } =20 + /* For L1d and L1i caches, 0xff is the full associativity marker */ + if ((index =3D=3D 0 || index =3D=3D 1) && assoc =3D=3D 0xff) + assoc =3D AMD_CPUID4_FULLY_ASSOCIATIVE; + regs->cache_self_init =3D 1; regs->cache_type =3D types[index]; regs->cache_level =3D levels[index]; @@ -207,7 +183,7 @@ static int amd_fill_cpuid4_info(struct cpuinfo_x86 *c, = int index, struct _cpuid4 if (boot_cpu_has(X86_FEATURE_TOPOEXT) || boot_cpu_data.x86_vendor =3D=3D = X86_VENDOR_HYGON) regs =3D *(struct leaf_0x4_0 *)cpuid_subleaf_index(c, 0x8000001d, index); else - legacy_amd_cpuid4(index, ®s); + legacy_amd_cpuid4(c, index, ®s); =20 return cpuid4_info_fill_done(id4, ®s); } @@ -279,10 +255,9 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c) { struct cpu_cacheinfo *ci =3D get_cpu_cacheinfo(c->cpu_index); =20 - if (boot_cpu_has(X86_FEATURE_TOPOEXT)) - ci->num_leaves =3D cpuid_subleaf_count(c, 0x8000001d); - else if (c->extended_cpuid_level >=3D 0x80000006) - ci->num_leaves =3D (cpuid_edx(0x80000006) & 0xf000) ? 4 : 3; + ci->num_leaves =3D boot_cpu_has(X86_FEATURE_TOPOEXT) ? + cpuid_subleaf_count(c, 0x8000001d) : + cpuid_leaf(c, 0x80000006)->l3_assoc ? 4 : 3; } =20 void init_hygon_cacheinfo(struct cpuinfo_x86 *c) --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8E59C284695 for ; Thu, 5 Jun 2025 19:25:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151531; cv=none; b=Ffsy04ixYoPLtIG+8b7U7O+40oYDf5lNuJlhZu+bDj49H0sOpQZSL3Vb9HM7jqnlSTnPshKdjDrXDisYgp0+O+nmmql2W7m07N2P+c17oxKhWw3Ak1e7LQkwhHs03n8Lv4dIbJ1diqVg0HjJUvYUUO3bZThd8eEbmykSFtPJ5kA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151531; c=relaxed/simple; bh=F3VBsvBWaXgoJf3PVV9A2l5bXC3TcwMyGK1nkWMIrUE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=AZF9bF644n422awIqymuRk9sde5f/ee7jby/So2nw04SA73SqHmU4+r5ibwnVmKE/mco9VOY0IXyQgJg3Y67I+1aAcYALIo6eL7N7JB8hp2v+spMcKufu6Ag4Iim/OIgVKlJ4jUp7/N5VpZIz0bsXH8wcBsVnx+q8MJQxUO25IQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=bAic/721; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=KfxDWXt5; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="bAic/721"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="KfxDWXt5" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151528; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KW5WdGb/m4hgqnmYLiE2ZFB6NP3p8ik4xLAbGqDxgGw=; b=bAic/721kWhc7AJFRHFNiWZQUefcrEsD7x6B6+AHRQGiSs4cczCrwTuMRVFcTcyNiPAYfd R4RRMSfzoPw0lluIDneAWOHC0Fr6trBijS8qWBHv2HgL3TfNV+cSF07tey2PZAW1pHyEOY zyKsM/2jOWJdSpDy4/M09wPlSr3KEbaYkIPwaXyslS56cnqwStQ0zgMwzI+oh1HJqe0FDR 5NCiD2M1aUrl2PXGQ4CAMzeoSPyJi52GCdcrWa1552khCGXDTCkjTrIOCjTREYWsg+rEo1 LFeov9W2yHctIMMYhhD2D5Q3MifdDXqvKWDKgwn4oLRXa2BaN4eaoGBsqDjusg== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151528; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=KW5WdGb/m4hgqnmYLiE2ZFB6NP3p8ik4xLAbGqDxgGw=; b=KfxDWXt5OtfvcQSIt5wVx43xb3b3wKzw6b5LhGBkdEtCKO7Dvbjb4Ud20dq0UQ/PSjiz4P tXEUVPPvppw6rTCQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 25/27] x86/cpuid: Add CPUID parser table rescan support Date: Thu, 5 Jun 2025 21:23:54 +0200 Message-ID: <20250605192356.82250-26-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add CPUID table(s) rescan support through cpuid_parser_rescan_cpu(). This will be needed for handling events that can change the system CPUID state; e.g. disabing the Processor Serial Number (PSN) or performing a late microcode update. Call sites in need of CPUID table rescan will be updated next. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/api.h | 1 + arch/x86/kernel/cpu/cpuid_parser.c | 42 +++++++++++++++++++++++++++++- 2 files changed, 42 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/cpuid/api.h b/arch/x86/include/asm/cpuid/= api.h index 82d36d210930..235f1a05792a 100644 --- a/arch/x86/include/asm/cpuid/api.h +++ b/arch/x86/include/asm/cpuid/api.h @@ -519,5 +519,6 @@ static inline bool cpuid_amd_hygon_has_l3_cache(void) */ =20 void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c); +void cpuid_parser_rescan_cpu(struct cpuinfo_x86 *c); =20 #endif /* _ASM_X86_CPUID_API_H */ diff --git a/arch/x86/kernel/cpu/cpuid_parser.c b/arch/x86/kernel/cpu/cpuid= _parser.c index 1f3b4cd6b411..b7a44026ab1a 100644 --- a/arch/x86/kernel/cpu/cpuid_parser.c +++ b/arch/x86/kernel/cpu/cpuid_parser.c @@ -156,6 +156,30 @@ cpuid_fill_table(struct cpuid_table *t, const struct c= puid_parse_entry entries[] } } =20 +/* + * __cpuid_parser_scan_cpu() - Populate current CPU's CPUID table + * @c: CPU capability structure associated with the current CPU + * @clear_cpuid_table: Zero-out the CPUID table residing within @c before = populating it + * + * The CPUID parser code expects a zeroed-out CPUID table since the access= or macros at + * use the leaf's "nr_entries" field as a validity marker; o= therwise NULL is + * returned. + * + * At boot, all CPUID tables within the CPU capability structure(s) are ze= roed. For + * subsequent CPUID table scans, which are normally done after hardware st= ate changes, the + * table might contain stale data that must be cleared beforehand; e.g., a= CPUID leaf that + * is no longer available, but with a "nr_entries" value bigger than zero. + */ +static void __cpuid_parser_scan_cpu(struct cpuinfo_x86 *c, bool clear_cpui= d_table) +{ + struct cpuid_table *table =3D &c->cpuid; + + if (clear_cpuid_table) + memset(table, 0, sizeof(*table)); + + cpuid_fill_table(table, cpuid_common_parse_entries, cpuid_common_parse_en= tries_size); +} + /** * cpuid_parser_scan_cpu() - Populate current CPU's CPUID table * @c: CPU capability structure associated with the current CPU @@ -165,5 +189,21 @@ cpuid_fill_table(struct cpuid_table *t, const struct c= puid_parse_entry entries[] */ void cpuid_parser_scan_cpu(struct cpuinfo_x86 *c) { - cpuid_fill_table(&c->cpuid, cpuid_common_parse_entries, cpuid_common_pars= e_entries_size); + __cpuid_parser_scan_cpu(c, false); +} + +/** + * cpuid_parser_rescan_cpu() - Re-populate current CPU's CPUID table + * @c: CPU capability structure associated with the current CPU + * + * Zero-out the CPUID table embedded within @c, then re-populate it using = a fresh CPUID scan. + * Since all CPUID instructions are invoked locally, this function must be= called on the CPU + * associated with @c. + * + * A CPUID table rescan is usually required after system changes that can = affect CPUID state; + * e.g., disabing the Processor Serial Number (PSN) or performing a late m= icrocode update. + */ +void cpuid_parser_rescan_cpu(struct cpuinfo_x86 *c) +{ + __cpuid_parser_scan_cpu(c, true); } --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6A422857FB for ; Thu, 5 Jun 2025 19:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151534; cv=none; b=dqxCq7Va3RNkVt4PA/qh4gOxpjkIQgvz9h2aWfmEr4os36EG3PJ0ZlrSmvtiAUk44zdo4eO1GTuBScLTbVHpZYwzp66FuLNkAQV8JxPJ0diL7DNuNQt9xb1uHSe+dU5e8prnA8B1okMHUNLtjIBOAH7lYZiLUG3ZhnqeWYiyi7M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151534; c=relaxed/simple; bh=W3dTfIe7wNxHvY5661/WbK2xZkXVVQCSXUOWHesObeY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=d5r9rCgkRYK9ipLJYzEE68+ASU6JNHlv08vng3ljgr5WEJO+e9v/DvmL+c7/hcID+Bg973pgp4Jt3Tekzf1XvTv+o5Xeje1UPCMXYWrge7iTDuzc3FTbyMWKpX1tUQomDw0HHmKINPlQltl9ciIBej12oJQ3CbP5910mX0CHqbo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=PPUmrZen; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=9CC40TBt; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="PPUmrZen"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="9CC40TBt" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151531; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=06vLN0q3YMEOZ8znXlguEvGzBlU5hq5/7MCh3v91C8E=; b=PPUmrZenVsJf/PMG/HCzYGyQOknltFXrU3Vmw+cnpCgbnxaLczXgTyNCaZgvm9Vq1HOUzV I3mNX0nKRPM9B77azOBbBOtJwHKAbNNKEcR2nN13bwu5GSctJf1JWDt4ssc+OwAQZQzAsJ 45eHw0npcUZdEgTmCxnxRI12emf+/tKZ7Ix1jiNXVm/+OnDhJZZapUlp+ideL8tTXJLslg pGq5syfUy4xmWTbWEhsRQo4oTurSghGlXiMjgScpa7dd5Ne1siDh90Crqhf7wT27+HoxBe rcqZjHl5rLFmM+0EizQrL4MNv5YVKXeOVaKqNO50JHKn1uSFBi8viQqpIGRxAw== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151531; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=06vLN0q3YMEOZ8znXlguEvGzBlU5hq5/7MCh3v91C8E=; b=9CC40TBtHgmw8SgIX/htO9vZLZ4xefhfZ8L58uRKvzs+tS7Cf/yaFQLUrSb9pJbzRfNRaK EwhgRHjpr+/mvnCQ== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 26/27] x86/cpu: Rescan system CPUID table after PSN disable Date: Thu, 5 Jun 2025 21:23:55 +0200 Message-ID: <20250605192356.82250-27-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" On Pentium-III and Transmeta CPUs, disabling the CPUID(0x3) Processor Serial Number (PSN) can affect the maximum valid CPUID standard leaf. Rescan the CPU's CPUID table in that case, not to have stale cached data. Use parsed CPUID(0x0) access, instead of direct CPUID query, afterwards. Rename squash_the_stupid_serial_number() to disable_cpu_serial_number() and explain the rational for disabling the CPU's PSN. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/common.c | 20 +++++++++++++------- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 023613698b15..d74a098d259a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -327,15 +327,17 @@ bool cpuid_feature(void) return flag_is_changeable_p(X86_EFLAGS_ID); } =20 -static void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) +/* + * For privacy concerns, disable legacy Intel and Transmeta CPUID(0x3) + * feature, Processor Serial Number, by default. + */ +static void disable_cpu_serial_number(struct cpuinfo_x86 *c) { unsigned long lo, hi; =20 if (!cpu_has(c, X86_FEATURE_PN) || !disable_x86_serial_nr) return; =20 - /* Disable processor serial number: */ - rdmsr(MSR_IA32_BBL_CR_CTL, lo, hi); lo |=3D 0x200000; wrmsr(MSR_IA32_BBL_CR_CTL, lo, hi); @@ -343,8 +345,12 @@ static void squash_the_stupid_serial_number(struct cpu= info_x86 *c) pr_notice("CPU serial number disabled.\n"); clear_cpu_cap(c, X86_FEATURE_PN); =20 - /* Disabling the serial number may affect the cpuid level */ - c->cpuid_level =3D cpuid_eax(0); + /* + * Disabling CPUID(0x3) might affect the maximum standard CPUID + * level. Rescan the CPU's CPUID table afterwards. + */ + cpuid_parser_rescan_cpu(c); + c->cpuid_level =3D cpuid_leaf(c, 0x0)->max_std_leaf; } =20 static int __init x86_serial_nr_setup(char *s) @@ -354,7 +360,7 @@ static int __init x86_serial_nr_setup(char *s) } __setup("serialnumber", x86_serial_nr_setup); #else -static inline void squash_the_stupid_serial_number(struct cpuinfo_x86 *c) +static inline void disable_cpu_serial_number(struct cpuinfo_x86 *c) { } #endif @@ -1968,7 +1974,7 @@ static void identify_cpu(struct cpuinfo_x86 *c) bus_lock_init(); =20 /* Disable the PN if appropriate */ - squash_the_stupid_serial_number(c); + disable_cpu_serial_number(c); =20 /* Set up SMEP/SMAP/UMIP */ setup_smep(c); --=20 2.49.0 From nobody Fri Dec 19 00:05:13 2025 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BC07928642D for ; Thu, 5 Jun 2025 19:25:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151538; cv=none; b=bT+sWMPo64k0A++TEnwYdcu/Bgx/3wMrpoOQzFt3aztcVdDra1YqbFB0aQXdq+V2J7Nidm3VqyTY30W9h//20NUiizaZqAX3/F8BFaX5eDaNUIu98Egd9pSw5Ny5HguUjtgR7BwiEn4BgrtK9kPQTl4h9WM/7BJcA3E7s8QhW3I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749151538; c=relaxed/simple; bh=oAdmUOsJ/hI0kEQIro0mWFWtDEHDV5wWzT5xDgGKpFQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=W8TwCUJSLZyB5srE9tIVfvVWqxy4pkyFFnk3uE0r2ypc688LnJ9yBfqz3ZLz1u2O+8RMTOwUDYpoMyoeV4RUfmgsPbAVIfk/d0QO1RYvWhKyb45/w4wrTrbHKU3lGr+gjKE22b+LvKMUAzBY7cIqnxjBA0bzeNXzzUxN7fKxSPs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=agGCmPOK; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nCOdgxiT; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="agGCmPOK"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nCOdgxiT" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1749151534; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HvaCvMJm0jpMRter6UXb3BRb34UtTypyr6H6vZTefjg=; b=agGCmPOK3sr5mehlLg3XK4x35yRiZYu6GGMB/Ft/FJNp/ZEjZ+yMZIRc2BRyR0yhPNrUXa VHD2TMklcYXA2tRU4JOUkR25b7ByTkHP0kAVeu2kK6cI3VMKGQcRDMm7qDpJ8BG4FcTP7N HNhUVEQfuUikapPeytMevTTRi7LO64wDfUb2H36LT3B/6gfU1maCA/r6itnkB7QRZqyMmi YwseZiMQJCJJ/m4jR/OVJbzY3HFv8yxb2P5bw9F/UapqVZJlW2ziq2fd9Ur92rRz9NO2gV vPU5eCH7oaYDQ2fmGLnJmk7m6IcQR6axErrhhzQe/sHvc63csFxtbZK0u2pz8A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1749151534; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=HvaCvMJm0jpMRter6UXb3BRb34UtTypyr6H6vZTefjg=; b=nCOdgxiTdrfQcmx0x2SideQCA88pYlehDRMFmecAoUPY1mLY51Jct+H4WKJZeCdu3mzloG 7eG5GQr3OVsPOZBw== To: Ingo Molnar , Borislav Petkov , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , Peter Zijlstra , Sean Christopherson , Sohil Mehta , Ard Biesheuvel , John Ogness , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v2 27/27] x86/cpu: Rescan CPUID table after unlocking full CPUID range Date: Thu, 5 Jun 2025 21:23:56 +0200 Message-ID: <20250605192356.82250-28-darwi@linutronix.de> In-Reply-To: <20250605192356.82250-1-darwi@linutronix.de> References: <20250605192356.82250-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Intel CPUs have an MSR bit to limit CPUID enumeration to leaf two, which can be set by old BIOSen before booting Linux. Rescan the CPUID table after unlocking the CPU's full CPUID range. Use parsed CPUID(0x0) access, instead of a direct CPUID query, afterwards. References: 066941bd4eeb ("x86: unmask CPUID levels on Intel CPUs") References: 0c2f6d04619e ("x86/topology/intel: Unlock CPUID before evaluati= ng anything") Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/intel.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c index 06c249110c8b..4784afaf178b 100644 --- a/arch/x86/kernel/cpu/intel.c +++ b/arch/x86/kernel/cpu/intel.c @@ -192,11 +192,14 @@ void intel_unlock_cpuid_leafs(struct cpuinfo_x86 *c) return; =20 /* - * The BIOS can have limited CPUID to leaf 2, which breaks feature - * enumeration. Unlock it and update the maximum leaf info. + * Intel CPUs have an MSR bit to limit CPUID enumeration to CPUID(0x2), + * which can be set by old BIOSes before booting Linux. Unlock the CPU's + * full CPUID range then rescan its CPUID table. */ - if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_= BIT) > 0) - c->cpuid_level =3D cpuid_eax(0); + if (msr_clear_bit(MSR_IA32_MISC_ENABLE, MSR_IA32_MISC_ENABLE_LIMIT_CPUID_= BIT) > 0) { + cpuid_parser_rescan_cpu(c); + c->cpuid_level =3D cpuid_leaf(c, 0x0)->max_std_leaf; + } } =20 static void early_init_intel(struct cpuinfo_x86 *c) --=20 2.49.0