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([178.197.223.125]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-451febed5d7sm9711795e9.3.2025.06.05.10.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jun 2025 10:36:12 -0700 (PDT) From: Krzysztof Kozlowski To: Bjorn Andersson , Konrad Dybcio , linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org Cc: Krzysztof Kozlowski Subject: [RESEND PATCH] arm64: defconfig: Enable camcc and videocc on Qualcomm SM8450+ Date: Thu, 5 Jun 2025 19:36:09 +0200 Message-ID: <20250605173608.217495-2-krzysztof.kozlowski@linaro.org> X-Mailer: git-send-email 2.45.2 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=1120; i=krzysztof.kozlowski@linaro.org; h=from:subject; bh=dl8Jg60ElVh4ZYg5JYQyBSog9Gk/qp3bgu5GdVsMqhQ=; b=owEBbQKS/ZANAwAKAcE3ZuaGi4PXAcsmYgBoQdWIg0KFlLqP1FkVueD0UsRvJ00CqeHqO4uav Ac+lFcBHjWJAjMEAAEKAB0WIQTd0mIoPREbIztuuKjBN2bmhouD1wUCaEHViAAKCRDBN2bmhouD 10vOD/0ZMt4+8X+Vjca4R+MkxyjOIH9VunlrWkdoS41xwOdrV2c4SMfXEGbYdA5fTDUKKOEVQee s4zBiNC9dWMQOqV4F8ybyJtA3ntvXGKZo3gjBVE1OVgG0yNT63xBE/R99O6eTF1DmB818Y5JEsZ G3xR7txsU9JJrqXxboShpg/QK3/lWD9bLIZ1FPaDqJ25GhMSTMaF2DyJTXkaVb/zBuL0siWMD7j ObtFLvnylLf22EseMJmBcRDBMHOnPjlVMrW84QcmoKZBfv1PZSXXQ5DgDhB5gnlEb5K+korOT08 iQi6MEqmRppY9u0Gk0uQEPWgDMTfgoiGZUUFH3sI2UNTWcmcCnOfX2jzIwwzJdxz1DyLzvnAiw2 NWkuYGP/xPDgN+IquvM/97zNSzcEqpPKwy3Lqitgc6uRDHZzOPbX2BxyONcs+d7PRwMDBhBFO00 eSX+htPnWVKK8gRgf9vQWetqn0ZLfj5jEnIzZSL35JPB2OYzEadbjv1eFnJm6Q/uVl6eZqPHrO7 fjsu0dDzeSGvuIKyLr7VNP62yJsy//S6eWxeeajQfU3Sd5Hsy/j5V3hQl04H4B1yuv+QJnDIafQ UqyZLZEK8y5w6cerptvRGjHofkFdBLsjsYSfmSGbRMtYVT4S/CJc8ISPpAg4GBsXRZsnNR2zKjI eXOyqfAD7b1dIuQ== X-Developer-Key: i=krzysztof.kozlowski@linaro.org; a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Enable the drivers for camera clock controllers on Qualcomm SM8550 and SM8650 SoC (enabled in all DTS files like SM8550-HDK or SM8650-HDK) and video clock controllers on Qualcomm SM8450 SoC (enabled in SM8450-HDK DTS). Signed-off-by: Krzysztof Kozlowski Reviewed-by: Konrad Dybcio Reviewed-by: Neil Armstrong --- Resend because I forgot to CC right people. --- arch/arm64/configs/defconfig | 3 +++ 1 file changed, 3 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 62d3c87858e1..2ffa590b962f 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -1404,6 +1404,8 @@ CONFIG_SDM_DISPCC_845=3Dy CONFIG_SDM_LPASSCC_845=3Dm CONFIG_SDX_GCC_75=3Dy CONFIG_SM_CAMCC_8250=3Dm +CONFIG_SM_CAMCC_8550=3Dm +CONFIG_SM_CAMCC_8650=3Dm CONFIG_SM_DISPCC_6115=3Dm CONFIG_SM_DISPCC_8250=3Dy CONFIG_SM_DISPCC_8450=3Dm @@ -1431,6 +1433,7 @@ CONFIG_SM_VIDEOCC_8250=3Dy CONFIG_SM_VIDEOCC_8550=3Dm CONFIG_QCOM_HFPLL=3Dy CONFIG_CLK_GFM_LPASS_SM8250=3Dm +CONFIG_SM_VIDEOCC_8450=3Dm CONFIG_CLK_RCAR_USB2_CLOCK_SEL=3Dy CONFIG_CLK_RENESAS_VBATTB=3Dm CONFIG_HWSPINLOCK=3Dy --=20 2.45.2