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[93.70.53.177]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f00a00d4sm24281167f8f.92.2025.06.05.01.59.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 Jun 2025 01:59:40 -0700 (PDT) From: Stefano Radaelli To: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: othacehe@gnu.org, andrew@lunn.ch, Stefano Radaelli , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Shawn Guo , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org Subject: [PATCH v3] arm64: dts: freescale: imx93-var-som: update eqos support for MaxLinear PHY Date: Thu, 5 Jun 2025 10:59:04 +0200 Message-ID: <20250605085904.12199-1-stefano.radaelli21@gmail.com> X-Mailer: git-send-email 2.43.0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Variscite has updated the Ethernet PHY on the VAR-SOM-MX93 from the ADIN1300BCPZ to the MaxLinear MXL86110, as documented in the August 2023 revision changelog. Link: https://variwiki.com/index.php?title=3DVAR-SOM-MX93_rev_changelog Update the device tree accordingly: - Drop the regulator node used to power the previously PHY. - Add support for the reset line using GPIO1_IO07 with proper timings. - Configure the PHY LEDs via the LED subsystem under /sys/class/leds/, leveraging the support implemented in the mxl86110 PHY driver (drivers/net/phy/mxl-86110.c). Two LEDs are defined to match the LED configuration on the Variscite VAR-SOM Carrier Boards: * LED@0: Yellow, netdev trigger. * LED@1: Green, netdev trigger. - Adjust the RGMII clock pad control settings to match the updated PHY requirements. These changes ensure proper PHY initialization and LED status indication for the new MaxLinear MXL86110, improving board compatibility with the latest hardware revision. Signed-off-by: Stefano Radaelli --- v3: - Add "PATCH" to subject line. - Fix wrong reference to previous PHY in commit message. v2: https://lore.kernel.org/imx/20250604153510.55689-1-stefano.radaelli21@g= mail.com/ - Clarified the use of 'rgmii' mode by adding a comment in the DT, explaining that hardware delays are already implemented on the SOM PCB. v1: https://lore.kernel.org/imx/20250603221416.74523-1-stefano.radaelli21@g= mail.com/ .../boot/dts/freescale/imx93-var-som.dtsi | 45 ++++++++++++------- 1 file changed, 30 insertions(+), 15 deletions(-) diff --git a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi b/arch/arm64/= boot/dts/freescale/imx93-var-som.dtsi index 783938245e4f..cea8d792328c 100644 --- a/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi +++ b/arch/arm64/boot/dts/freescale/imx93-var-som.dtsi @@ -19,26 +19,19 @@ mmc_pwrseq: mmc-pwrseq { reset-gpios =3D <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */ <&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */ }; - - reg_eqos_phy: regulator-eqos-phy { - compatible =3D "regulator-fixed"; - pinctrl-names =3D "default"; - pinctrl-0 =3D <&pinctrl_reg_eqos_phy>; - regulator-name =3D "eth_phy_pwr"; - regulator-min-microvolt =3D <3300000>; - regulator-max-microvolt =3D <3300000>; - gpio =3D <&gpio1 7 GPIO_ACTIVE_HIGH>; - enable-active-high; - startup-delay-us =3D <100000>; - regulator-always-on; - }; }; =20 &eqos { pinctrl-names =3D "default"; pinctrl-0 =3D <&pinctrl_eqos>; + /* + * The required RGMII TX and RX 2ns delays are implemented directly + * in hardware via passive delay elements on the SOM PCB. + * No delay configuration is needed in software via PHY driver. + */ phy-mode =3D "rgmii"; phy-handle =3D <ðphy0>; + snps,clk-csr =3D <5>; status =3D "okay"; =20 mdio { @@ -51,6 +44,27 @@ ethphy0: ethernet-phy@0 { compatible =3D "ethernet-phy-ieee802.3-c22"; reg =3D <0>; eee-broken-1000t; + reset-gpios =3D <&gpio1 7 GPIO_ACTIVE_LOW>; + reset-assert-us =3D <10000>; + reset-deassert-us =3D <100000>; + leds { + #address-cells =3D <1>; + #size-cells =3D <0>; + + led@0 { + reg =3D <0>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + + led@1 { + reg =3D <1>; + color =3D ; + function =3D LED_FUNCTION_LAN; + linux,default-trigger =3D "netdev"; + }; + }; }; }; }; @@ -75,14 +89,15 @@ MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e - MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x5fe + MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e - MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe + MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e + MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e >; }; =20 base-commit: a9dfb7db96f7bc1f30feae673aab7fdbfbc94e9c prerequisite-patch-id: 2335ebcc90360b008c840e7edf7e34a595880edf --=20 2.43.0