From nobody Fri Dec 19 20:58:14 2025 Received: from smtp-190c.mail.infomaniak.ch (smtp-190c.mail.infomaniak.ch [185.125.25.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D60481EEA3C for ; Thu, 5 Jun 2025 15:41:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.125.25.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749138090; cv=none; b=hms0Xf3dTieg3Bhc5hQ7vGDnca5Pi8dMnm8aNxriLwnr7o0LlJj6Dk85XjXazXlqg3p9okldvwWd27efmoF6ilgPeGG/PVF9gvwcUq5yE84Oi5IodoGDxphW2pFBHP3OAiBzJtMmL9CVbLqGSUPzYlUf2KYl2NwGzgh7Jv3civY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749138090; c=relaxed/simple; bh=nmfuwsHfObbwfOxWN3QCkxhDB/TrN7Ik4c69MJA6cTw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=mLg+SNgxHEaQy7BPA5PpAwce8Cpb3Eh67VE9t4T38ylSr5qasbvaztpGtucEeS8WZUj+ytq8WmwM++6eKrMhoRhmBJPpBDyjWG7hOS0/XBcdjEFWko9OYf3M0Y5hjfz65WUTs6D13f2fuEH4tzkoyAtcpitdJAVWq0QLgBo7xIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=185.125.25.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (smtp-3-0000.mail.infomaniak.ch [10.4.36.107]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bCpZl743dztGn; Thu, 5 Jun 2025 17:41:19 +0200 (CEST) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4bCpZl1zQJzpLP; Thu, 5 Jun 2025 17:41:19 +0200 (CEST) From: Quentin Schulz Date: Thu, 05 Jun 2025 17:41:06 +0200 Subject: [PATCH v2 1/4] dt-bindings: mfd: rk806: allow to customize PMIC reset mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250605-rk8xx-rst-fun-v2-1-143d190596dd@cherry.de> References: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> In-Reply-To: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The RK806 PMIC allows to configure its reset/restart behavior whenever the PMIC is reset either programmatically or via some external pins (e.g. PWRCTRL or RESETB). The following modes exist: - 0 (RK806_RESTART) restart PMU, - 1 (RK806_RESET) reset all power off reset registers and force state to switch to ACTIVE mode, - 2 (RK806_RESET_NOTIFY) same as RK806_RESET and also pull RESETB pin down for 5ms, For example, some hardware may require a full restart (RK806_RESTART mode) in order to function properly as regulators are shortly interrupted in this mode. This is the case for RK3588 Jaguar and RK3588 Tiger which have a companion microcontroller running on an independent power supply and monitoring the PMIC power rail to know the state of the main system. When it detects a restart, it resets its own IPs exposed to the main system as if to simulate its own reset. Failing to perform this fake reset of the microcontroller may break things (e.g. watchdog not automatically disabled, buzzer still running until manually disabled, leftover configuration from previous main system state, etc...). Some other systems may be depending on the power rails to not be interrupted even for a small amount of time[1]. This allows to specify how the PMIC should perform on the hardware level and may differ between harwdare designs, so a DT property seems warranted. I unfortunately do not see how this could be made generic enough to make it a non-vendor property. [1] https://lore.kernel.org/linux-rockchip/2577051.irdbgypaU6@workhorse/ Signed-off-by: Quentin Schulz --- .../devicetree/bindings/mfd/rockchip,rk806.yaml | 23 ++++++++++++++++++= ++++ include/dt-bindings/mfd/rockchip,rk8xx.h | 17 ++++++++++++++++ 2 files changed, 40 insertions(+) diff --git a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml b/Do= cumentation/devicetree/bindings/mfd/rockchip,rk806.yaml index 3c2b06629b75ea94f90712470bf14ed7fc16d68d..c555b5956cea9f594d80ebd3b27= e8489e520d97d 100644 --- a/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml +++ b/Documentation/devicetree/bindings/mfd/rockchip,rk806.yaml @@ -31,6 +31,29 @@ properties: =20 system-power-controller: true =20 + rockchip,reset-mode: + $ref: /schemas/types.yaml#/definitions/uint32 + enum: [0, 1, 2] + description: + Mode to use when a reset of the PMIC is triggered. + + The reset can be triggered either programmatically, via one of + the PWRCTRL pins (provided additional configuration) or + asserting RESETB pin low. + + The following modes are supported (see also + include/dt-bindings/mfd/rockchip,rk8xx.h) + + - 0 (RK806_RESTART) restart PMU, + - 1 (RK806_RESET) reset all power off reset registers and force + state to switch to ACTIVE mode, + - 2 (RK806_RESET_NOTIFY) same as RK806_RESET and also pull + RESETB pin down for 5ms, + + For example, some hardware may require a full restart + (RK806_RESTART mode) in order to function properly as regulators + are shortly interrupted in this mode. + vcc1-supply: description: The input supply for dcdc-reg1. diff --git a/include/dt-bindings/mfd/rockchip,rk8xx.h b/include/dt-bindings= /mfd/rockchip,rk8xx.h new file mode 100644 index 0000000000000000000000000000000000000000..f058ed1ca661185f79738a358aa= 2d4f04539c590 --- /dev/null +++ b/include/dt-bindings/mfd/rockchip,rk8xx.h @@ -0,0 +1,17 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Device Tree defines for Rockchip RK8xx PMICs + * + * Copyright 2025 Cherry Embedded Solutions GmbH + * + * Author: Quentin Schulz + */ + +#ifndef _DT_BINDINGS_MFD_ROCKCHIP_RK8XX_H +#define _DT_BINDINGS_MFD_ROCKCHIP_RK8XX_H + +#define RK806_RESTART 0 +#define RK806_RESET 1 +#define RK806_RESET_NOTIFY 2 + +#endif --=20 2.49.0 From nobody Fri Dec 19 20:58:14 2025 Received: from smtp-bc0a.mail.infomaniak.ch (smtp-bc0a.mail.infomaniak.ch [45.157.188.10]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5ED1E1E500C for ; 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dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:4:17::246b]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bCpZm56pzz5TC; Thu, 5 Jun 2025 17:41:20 +0200 (CEST) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4bCpZl6yQBzq71; Thu, 5 Jun 2025 17:41:19 +0200 (CEST) From: Quentin Schulz Date: Thu, 05 Jun 2025 17:41:07 +0200 Subject: [PATCH v2 2/4] mfd: rk8xx-core: allow to customize RK806 reset mode Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250605-rk8xx-rst-fun-v2-2-143d190596dd@cherry.de> References: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> In-Reply-To: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The RK806 PMIC has a bitfield for configuring the restart/reset behavior (which I assume Rockchip calls "function") whenever the PMIC is reset either programmatically (c.f. DEV_RST in the datasheet) or via PWRCTRL or RESETB pins. For RK806, the following values are possible for RST_FUN: 0b00 means "restart PMU" 0b01 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode" 0b10 means "Reset all the power off reset registers, forcing the state to switch to ACTIVE mode, and simultaneously pull down the RESETB PIN for 5mS before releasing" 0b11 means the same as for 0b10 just above. This adds the appropriate logic in the driver to parse the new rockchip,reset-mode DT property to pass this information. It just happens that the values in the binding match the values to write in the bitfield so no mapping is necessary. If it is missing, the register is left untouched and relies either on the silicon default or on whatever was set earlier in the boot stages (e.g. the bootloader). Signed-off-by: Quentin Schulz --- drivers/mfd/rk8xx-core.c | 14 ++++++++++++++ include/linux/mfd/rk808.h | 2 ++ 2 files changed, 16 insertions(+) diff --git a/drivers/mfd/rk8xx-core.c b/drivers/mfd/rk8xx-core.c index 71c2b80a4678d627e86cfbec8135f08e262559d3..32294af0b843fa20677513b1e1a= 5a6c8e76be4b6 100644 --- a/drivers/mfd/rk8xx-core.c +++ b/drivers/mfd/rk8xx-core.c @@ -699,6 +699,7 @@ int rk8xx_probe(struct device *dev, int variant, unsign= ed int irq, struct regmap const struct mfd_cell *cells; int dual_support =3D 0; int nr_pre_init_regs; + u32 rst_fun =3D 0; int nr_cells; int ret; int i; @@ -726,6 +727,19 @@ int rk8xx_probe(struct device *dev, int variant, unsig= ned int irq, struct regmap cells =3D rk806s; nr_cells =3D ARRAY_SIZE(rk806s); dual_support =3D IRQF_SHARED; + + ret =3D device_property_read_u32(dev, "rockchip,reset-mode", &rst_fun); + if (ret) { + dev_dbg(dev, + "rockchip,reset-mode property missing, not setting RST_FUN\n"); + break; + } + + ret =3D regmap_update_bits(rk808->regmap, RK806_SYS_CFG3, + RK806_RST_FUN_MSK, + FIELD_PREP(RK806_RST_FUN_MSK, rst_fun)); + if (ret) + return dev_err_probe(dev, ret, "RST_FUN write err\n"); break; case RK808_ID: rk808->regmap_irq_chip =3D &rk808_irq_chip; diff --git a/include/linux/mfd/rk808.h b/include/linux/mfd/rk808.h index 69cbea78b430b562a23d995263369d475daa6287..28170ee08898ca59c76a741a1d4= 2763a42b72380 100644 --- a/include/linux/mfd/rk808.h +++ b/include/linux/mfd/rk808.h @@ -812,6 +812,8 @@ enum rk806_pin_dr_sel { #define RK806_INT_POL_H BIT(1) #define RK806_INT_POL_L 0 =20 +/* SYS_CFG3 */ +#define RK806_RST_FUN_MSK GENMASK(7, 6) #define RK806_SLAVE_RESTART_FUN_MSK BIT(1) #define RK806_SLAVE_RESTART_FUN_EN BIT(1) #define RK806_SLAVE_RESTART_FUN_OFF 0 --=20 2.49.0 From nobody Fri Dec 19 20:58:14 2025 Received: from smtp-42ac.mail.infomaniak.ch (smtp-42ac.mail.infomaniak.ch [84.16.66.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CCBA713D8A4 for ; Thu, 5 Jun 2025 15:41:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749138086; cv=none; b=m1u2xN2RptfscK7oeuKrYFHHeJHYwt8yuXOfmDcIY/aoKXPSnwH2i51ZIw8K9xotRuTyHv6lZlrqAY0oPyXyNcyAmQm/OMUL3D9bXGhMo+yMkiKlyJm8WEz1neA1aC5684EvSaNjPkC7DYxfxlE8ogL4QjxL211TAB4OgjBt9SE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749138086; c=relaxed/simple; bh=48Bc+nXf9XM8e7P6/iwUEIqVjxJ1/oJ48Vgd5O3Ja7o=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V2UG9Ugkxuk0f/t0Dy9HwCvUZc7YnB9mksw50EdBPWVGWjq7741auqhoPvy9nhGHt/YJamY/wOF3ocyFxiJ5lRQTTWPipqKB8VTiDNke4oSBozg4ZkpKKJe2kAZgmw3RDJAvhJMgAylYs2YEQXfXb4FqmyBBUqarm2E0Xlm30KQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (unknown [IPv6:2001:1600:4:17::246b]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bCpZn4ccZz3fw; Thu, 5 Jun 2025 17:41:21 +0200 (CEST) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4bCpZm4zsJznlL; Thu, 5 Jun 2025 17:41:20 +0200 (CEST) From: Quentin Schulz Date: Thu, 05 Jun 2025 17:41:08 +0200 Subject: [PATCH v2 3/4] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Jaguar Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250605-rk8xx-rst-fun-v2-3-143d190596dd@cherry.de> References: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> In-Reply-To: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The bootloader for RK3588 Jaguar currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts b/arch/arm64/bo= ot/dts/rockchip/rk3588-jaguar.dts index ebe77cdd24e803b00fb848dc81258909472290f1..def6af77efaccabe0dd08aaa795= 9602bfb143607 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts +++ b/arch/arm64/boot/dts/rockchip/rk3588-jaguar.dts @@ -7,6 +7,7 @@ #include #include #include +#include #include #include #include @@ -693,6 +694,7 @@ pmic@0 { vcc13-supply =3D <&vcc_1v1_nldo_s3>; vcc14-supply =3D <&vcc_1v1_nldo_s3>; vcca-supply =3D <&vcc5v0_sys>; + rockchip,reset-mode =3D ; =20 rk806_dvs1_null: dvs1-null-pins { pins =3D "gpio_pwrctrl1"; --=20 2.49.0 From nobody Fri Dec 19 20:58:14 2025 Received: from smtp-42a8.mail.infomaniak.ch (smtp-42a8.mail.infomaniak.ch [84.16.66.168]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 78D8419F11B for ; Thu, 5 Jun 2025 15:41:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=84.16.66.168 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749138086; cv=none; b=bduT5u7OKL5aEnvJSoVAEaHT67nqZqpe73l9To4n3e1k6Xki+X7FjgNabtcKoFWUiqqR0gd5+6b0XFrMzRfqBAqTMUR+2uNwo8nLx9Df01TannRZLRX+1HoEHvKGx6choVB8PtkVOVIjH7doSs9gA+tOS4rSPZFcxz3RpMjAa1M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749138086; c=relaxed/simple; bh=P719VLxHFxERjXUpHSjJfqPi7IZOb95FqVlS6IdDChg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=lhOi4tvlByHDf/ZjOqk5TEbRf45Vi03egklMp9jYqdYRtN3MtvM8K7zby0tshMWFqbSQUxXcCLcsdek/Hoh3VhFf8KjJRqVUJWVW2AD/cRY1GcTaOjYVL6N69asxn1wNZ83gRxIlXcVc6Sx3e+FCACYpehcDAO7DbI2Vms6IL5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net; spf=pass smtp.mailfrom=0leil.net; arc=none smtp.client-ip=84.16.66.168 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=0leil.net Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=0leil.net Received: from smtp-3-0000.mail.infomaniak.ch (smtp-3-0000.mail.infomaniak.ch [10.4.36.107]) by smtp-3-3000.mail.infomaniak.ch (Postfix) with ESMTPS id 4bCpZp2PGNzrRp; Thu, 5 Jun 2025 17:41:22 +0200 (CEST) Received: from unknown by smtp-3-0000.mail.infomaniak.ch (Postfix) with ESMTPA id 4bCpZn4Vc1zdCl; Thu, 5 Jun 2025 17:41:21 +0200 (CEST) From: Quentin Schulz Date: Thu, 05 Jun 2025 17:41:09 +0200 Subject: [PATCH v2 4/4] arm64: dts: rockchip: force PMIC reset behavior to restart PMU on RK3588 Tiger Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250605-rk8xx-rst-fun-v2-4-143d190596dd@cherry.de> References: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> In-Reply-To: <20250605-rk8xx-rst-fun-v2-0-143d190596dd@cherry.de> To: Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Heiko Stuebner , Sebastian Reichel Cc: Lukasz Czechowski , Daniel Semkowicz , Nicolas Frattaroli , devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org, Quentin Schulz X-Mailer: b4 0.14.2 X-Infomaniak-Routing: alpha From: Quentin Schulz The bootloader for RK3588 Tiger currently forces the PMIC reset behavior (stored in RST_FUN bitfield in register SYS_CFG3 of the PMIC) to 0b1X which is incorrect for our devices. It is required to restart the PMU as otherwise the companion microcontroller cannot detect the PMIC (and by extension the full product and main SoC) being rebooted which is an issue as that is used to reset a few things like the PWM beeper and watchdogs. Let's add the new rockchip,reset-mode property to make sure the PMIC reset behavior is the expected one. Signed-off-by: Quentin Schulz --- arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi b/arch/arm64/bo= ot/dts/rockchip/rk3588-tiger.dtsi index c4933a08dd1e3c92f3e0747135faf97c5eeca906..4c05603abed2e458e406ed45f1b= c7cdb57b42478 100644 --- a/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi +++ b/arch/arm64/boot/dts/rockchip/rk3588-tiger.dtsi @@ -5,6 +5,7 @@ =20 #include #include +#include #include #include "rk3588.dtsi" =20 @@ -440,6 +441,7 @@ pmic@0 { vcc13-supply =3D <&vcc_1v1_nldo_s3>; vcc14-supply =3D <&vcc_1v1_nldo_s3>; vcca-supply =3D <&vcc5v0_sys>; + rockchip,reset-mode =3D ; =20 rk806_dvs1_null: dvs1-null-pins { pins =3D "gpio_pwrctrl1"; --=20 2.49.0