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Update the qcom,pcie-common.yaml to include the phys, phy-names properties in the root port node. There is already reset-gpios defined for PERST# in pci-bus-common.yaml, start using that property instead of perst-gpio. For backward compatibility, do not remove any existing properties in the bridge node. Hence mark them as 'deprecated'. [1] https://lore.kernel.org/linux-pci/20241211192014.GA3302752@bhelgaas/ Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Rob Herring (Arm) --- .../devicetree/bindings/pci/qcom,pcie-common.yaml | 32 ++++++++++++++++++= ++-- .../devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 16 ++++++++--- 2 files changed, 42 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml index 0480c58f7d998adbac4c6de20cdaec945b3bab21..ab2509ec1c4b40ac91a93033d1b= ab1b12c39362f 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-common.yaml @@ -51,10 +51,18 @@ properties: =20 phys: maxItems: 1 + deprecated: true + description: + This property is deprecated, instead of referencing this property fr= om + the host bridge node, use the property from the PCIe root port node. =20 phy-names: items: - const: pciephy + deprecated: true + description: + Phandle to the register map node. This property is deprecated, and n= ot + required to add in the root port also, as the root port has only one= phy. =20 power-domains: maxItems: 1 @@ -71,12 +79,18 @@ properties: maxItems: 12 =20 perst-gpios: - description: GPIO controlled connection to PERST# signal + description: GPIO controlled connection to PERST# signal. This propert= y is + deprecated, instead of referencing this property from the host bridg= e node, + use the reset-gpios property from the root port node. maxItems: 1 + deprecated: true =20 wake-gpios: - description: GPIO controlled connection to WAKE# signal + description: GPIO controlled connection to WAKE# signal. This property= is + deprecated, instead of referencing this property from the host bridg= e node, + use the property from the PCIe root port node. maxItems: 1 + deprecated: true =20 vddpe-3v3-supply: description: PCIe endpoint power supply @@ -85,6 +99,20 @@ properties: opp-table: type: object =20 +patternProperties: + "^pcie@": + type: object + $ref: /schemas/pci/pci-pci-bridge.yaml# + + properties: + reg: + maxItems: 1 + + phys: + maxItems: 1 + + unevaluatedProperties: false + required: - reg - reg-names diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index ff508f592a1acf7557ed8035d819207dab01f94d..4d0a915566030f8fbd8bf83a9cc= ca00fbc7574bd 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -165,9 +165,6 @@ examples: iommu-map =3D <0x0 &apps_smmu 0x1c80 0x1>, <0x100 &apps_smmu 0x1c81 0x1>; =20 - phys =3D <&pcie1_phy>; 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Currently, QCOM controllers only support single port, and all properties are present in the host bridge node itself. This is incorrect, as properties like phys, perst-gpios, etc.. can vary per port and should be present in the root port node. To maintain DT backwards compatibility, fallback to the legacy method of parsing the host bridge node if the port parsing fails. pci-bus-common.yaml uses reset-gpios property for representing PERST#, use same property instead of perst-gpios. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 177 ++++++++++++++++++++++++++++-= ---- 1 file changed, 150 insertions(+), 27 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index c789e3f856550bcfa1ce09962ba9c086d117de05..653be8125a6a0e48f9d09706ada= fb3ff96b4b52b 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -262,6 +262,12 @@ struct qcom_pcie_cfg { bool no_l0s; }; =20 +struct qcom_pcie_port { + struct list_head list; + struct gpio_desc *reset; + struct phy *phy; +}; + struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ @@ -274,24 +280,37 @@ struct qcom_pcie { struct icc_path *icc_cpu; const struct qcom_pcie_cfg *cfg; struct dentry *debugfs; + struct list_head ports; bool suspended; bool use_pm_opp; }; =20 #define to_qcom_pcie(x) dev_get_drvdata((x)->dev) =20 -static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +static void qcom_perst_assert(struct qcom_pcie *pcie, bool assert) { - gpiod_set_value_cansleep(pcie->reset, 1); + struct qcom_pcie_port *port; + int val =3D assert ? 1 : 0; + + if (list_empty(&pcie->ports)) + gpiod_set_value_cansleep(pcie->reset, val); + else + list_for_each_entry(port, &pcie->ports, list) + gpiod_set_value_cansleep(port->reset, val); + usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 +static void qcom_ep_reset_assert(struct qcom_pcie *pcie) +{ + qcom_perst_assert(pcie, true); +} + static void qcom_ep_reset_deassert(struct qcom_pcie *pcie) { /* Ensure that PERST has been asserted for at least 100 ms */ msleep(PCIE_T_PVPERL_MS); - gpiod_set_value_cansleep(pcie->reset, 0); - usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); + qcom_perst_assert(pcie, false); } =20 static int qcom_pcie_start_link(struct dw_pcie *pci) @@ -1229,6 +1248,59 @@ static bool qcom_pcie_link_up(struct dw_pcie *pci) return val & PCI_EXP_LNKSTA_DLLLA; } =20 +static void qcom_pcie_phy_exit(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + + if (list_empty(&pcie->ports)) + phy_exit(pcie->phy); + else + list_for_each_entry(port, &pcie->ports, list) + phy_exit(port->phy); +} + +static void qcom_pcie_phy_power_off(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + + if (list_empty(&pcie->ports)) { + phy_power_off(pcie->phy); + } else { + list_for_each_entry(port, &pcie->ports, list) + phy_power_off(port->phy); + } +} + +static int qcom_pcie_phy_power_on(struct qcom_pcie *pcie) +{ + struct qcom_pcie_port *port; + int ret =3D 0; + + if (list_empty(&pcie->ports)) { + ret =3D phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) + return ret; + + ret =3D phy_power_on(pcie->phy); + if (ret) + return ret; + } else { + list_for_each_entry(port, &pcie->ports, list) { + ret =3D phy_set_mode_ext(port->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); + if (ret) + return ret; + + ret =3D phy_power_on(port->phy); + if (ret) { + qcom_pcie_phy_power_off(pcie); + return ret; + } + } + } + + return ret; +} + static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -1241,11 +1313,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; =20 - ret =3D phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); - if (ret) - goto err_deinit; - - ret =3D phy_power_on(pcie->phy); + ret =3D qcom_pcie_phy_power_on(pcie); if (ret) goto err_deinit; =20 @@ -1268,7 +1336,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) err_assert_reset: qcom_ep_reset_assert(pcie); err_disable_phy: - phy_power_off(pcie->phy); + qcom_pcie_phy_power_off(pcie); err_deinit: pcie->cfg->ops->deinit(pcie); =20 @@ -1281,7 +1349,7 @@ static void qcom_pcie_host_deinit(struct dw_pcie_rp *= pp) struct qcom_pcie *pcie =3D to_qcom_pcie(pci); =20 qcom_ep_reset_assert(pcie); - phy_power_off(pcie->phy); + qcom_pcie_phy_power_off(pcie); pcie->cfg->ops->deinit(pcie); } =20 @@ -1579,11 +1647,41 @@ static irqreturn_t qcom_pcie_global_irq_thread(int = irq, void *data) return IRQ_HANDLED; } =20 +static int qcom_pcie_parse_port(struct qcom_pcie *pcie, struct device_node= *node) +{ + struct device *dev =3D pcie->pci->dev; + struct qcom_pcie_port *port; + struct gpio_desc *reset; + struct phy *phy; + + reset =3D devm_fwnode_gpiod_get(dev, of_fwnode_handle(node), + "reset", GPIOD_OUT_HIGH, "PERST#"); + if (IS_ERR(reset)) + return PTR_ERR(reset); + + phy =3D devm_of_phy_get(dev, node, NULL); + if (IS_ERR(phy)) + return PTR_ERR(phy); + + port =3D devm_kzalloc(dev, sizeof(*port), GFP_KERNEL); + if (!port) + return -ENOMEM; + + port->reset =3D reset; + port->phy =3D phy; + INIT_LIST_HEAD(&port->list); + list_add_tail(&port->list, &pcie->ports); + + return 0; +} + static int qcom_pcie_probe(struct platform_device *pdev) { const struct qcom_pcie_cfg *pcie_cfg; unsigned long max_freq =3D ULONG_MAX; + struct qcom_pcie_port *port, *tmp; struct device *dev =3D &pdev->dev; + struct device_node *of_port; struct dev_pm_opp *opp; struct qcom_pcie *pcie; struct dw_pcie_rp *pp; @@ -1611,6 +1709,8 @@ static int qcom_pcie_probe(struct platform_device *pd= ev) if (ret < 0) goto err_pm_runtime_put; =20 + INIT_LIST_HEAD(&pcie->ports); + pci->dev =3D dev; pci->ops =3D &dw_pcie_ops; pp =3D &pci->pp; @@ -1619,12 +1719,6 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 pcie->cfg =3D pcie_cfg; =20 - pcie->reset =3D devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); - if (IS_ERR(pcie->reset)) { - ret =3D PTR_ERR(pcie->reset); - goto err_pm_runtime_put; - } - pcie->parf =3D devm_platform_ioremap_resource_byname(pdev, "parf"); if (IS_ERR(pcie->parf)) { ret =3D PTR_ERR(pcie->parf); @@ -1647,12 +1741,6 @@ static int qcom_pcie_probe(struct platform_device *p= dev) } } =20 - pcie->phy =3D devm_phy_optional_get(dev, "pciephy"); - if (IS_ERR(pcie->phy)) { - ret =3D PTR_ERR(pcie->phy); - goto err_pm_runtime_put; - } - /* OPP table is optional */ ret =3D devm_pm_opp_of_add_table(dev); if (ret && ret !=3D -ENODEV) { @@ -1699,9 +1787,42 @@ static int qcom_pcie_probe(struct platform_device *p= dev) =20 pp->ops =3D &qcom_pcie_dw_ops; =20 - ret =3D phy_init(pcie->phy); - if (ret) - goto err_pm_runtime_put; + for_each_available_child_of_node(dev->of_node, of_port) { + ret =3D qcom_pcie_parse_port(pcie, of_port); + of_node_put(of_port); + if (ret) { + if (ret !=3D -ENOENT) { + dev_err_probe(pci->dev, ret, + "Failed to parse port nodes %d\n", + ret); + goto err_pm_runtime_put; + } + break; + } + } + + /* + * In the case of properties not populated in root port, fallback to the + * legacy method of parsing the host bridge node. This is to maintain DT + * backwards compatibility. + */ + if (ret) { + pcie->phy =3D devm_phy_optional_get(dev, "pciephy"); + if (IS_ERR(pcie->phy)) { + ret =3D PTR_ERR(pcie->phy); + goto err_pm_runtime_put; + } + + pcie->reset =3D devm_gpiod_get_optional(dev, "perst", GPIOD_OUT_HIGH); + if (IS_ERR(pcie->reset)) { + ret =3D PTR_ERR(pcie->reset); + goto err_pm_runtime_put; + } + + ret =3D phy_init(pcie->phy); + if (ret) + goto err_pm_runtime_put; + } =20 platform_set_drvdata(pdev, pcie); =20 @@ -1746,10 +1867,12 @@ static int qcom_pcie_probe(struct platform_device *= pdev) err_host_deinit: dw_pcie_host_deinit(pp); err_phy_exit: - phy_exit(pcie->phy); + qcom_pcie_phy_exit(pcie); err_pm_runtime_put: pm_runtime_put(dev); pm_runtime_disable(dev); + list_for_each_entry_safe(port, tmp, &pcie->ports, list) + list_del(&port->list); =20 return ret; } --=20 2.34.1