From nobody Fri Dec 19 20:53:39 2025 Received: from zg8tmja2lje4os43os4xodqa.icoremail.net (zg8tmja2lje4os43os4xodqa.icoremail.net [206.189.79.184]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 45C3E28B7E1; Wed, 4 Jun 2025 08:52:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=206.189.79.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749027181; cv=none; b=i7sGsRFlpV925r5KqqtpWpyW8r6qJr9YMLuMFCo/YFmZWdgO2XlylVDfmfNQdsE8MVUZZgRzrrxZy/njP/2qILfo3tGIFVhjsyd7XYsvsoD5uHntB5s6AeKMycwcZP/295WhPT8qNc+f022Q8EbmyUXGYOVtLA86+m8SmpagNMM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749027181; c=relaxed/simple; bh=qFpva0TmfGMoqQwfYpHpQh703G/IXdwn7pLxD30Dac4=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=H2zb35M+zT0slvaKoBqxNP4vQf5l85p/MGueyZR3oV3Wu3VJimAikWLMfr0dBahSktvQCqQgkZueaKmgiYpUAtmg7RN5g+n744Oxnq+HueKYuelxp2QYkIniFVcPBPjCMfdEO1jxzhXdPbgji+Lpeqm1ecE9plnx44BwAqazHrg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=206.189.79.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005152DT.eswin.cn (unknown [10.12.96.41]) by app2 (Coremail) with SMTP id TQJkCgD3lpVVCUBo0WKaAA--.53474S2; Wed, 04 Jun 2025 16:52:39 +0800 (CST) From: dongxuyang@eswincomputing.com To: p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, huangyifeng@eswincomputing.com, Xuyang Dong Subject: [PATCH v2 1/2] dt-bindings: reset: eswin: Documentation for eic7700 SoC Date: Wed, 4 Jun 2025 16:52:35 +0800 Message-Id: <20250604085235.2153-1-dongxuyang@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20250604085124.2098-1-dongxuyang@eswincomputing.com> References: <20250604085124.2098-1-dongxuyang@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgD3lpVVCUBo0WKaAA--.53474S2 X-Coremail-Antispam: 1UD129KBjvJXoWxAF1UKry8Zw1kuFykuryDJrb_yoWrAw47pF 4kCFyDtr1DKFWIgw4FvF1SkF13Jwn3Wr1DXr4UZF47JF1Utw1vya4YgFs5JF98ZFs3GrW3 WFykXw18Zr9rAw7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUXJ5wUUUUU= X-CM-SenderInfo: pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/ Content-Type: text/plain; charset="utf-8" From: Xuyang Dong Add device tree binding documentation and header file for the ESWIN eic7700 reset controller module. Signed-off-by: Yifeng Huang Signed-off-by: Xuyang Dong --- .../bindings/reset/eswin,eic7700-reset.yaml | 41 +++++++++++ .../dt-bindings/reset/eswin,eic7700-reset.h | 73 +++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/eswin,eic7700-r= eset.yaml create mode 100644 include/dt-bindings/reset/eswin,eic7700-reset.h diff --git a/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.ya= ml b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml new file mode 100644 index 000000000000..85ad5fec9430 --- /dev/null +++ b/Documentation/devicetree/bindings/reset/eswin,eic7700-reset.yaml @@ -0,0 +1,41 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/eswin,eic7700-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: ESWIN EIC7700 SoC reset controller + +maintainers: + - Yifeng Huang + - Xuyang Dong + +properties: + compatible: + items: + - const: eswin,eic7700-reset + - const: syscon + - const: simple-mfd + + reg: + maxItems: 1 + + '#reset-cells': + const: 2 + +required: + - compatible + - reg + - '#reset-cells' + +additionalProperties: false + +examples: + - | + #include + + reset-controller@51828000 { + compatible =3D "eswin,eic7700-reset", "syscon", "simple-mfd"; + reg =3D <0x51828000 0x80000>; + #reset-cells =3D <2>; + }; diff --git a/include/dt-bindings/reset/eswin,eic7700-reset.h b/include/dt-b= indings/reset/eswin,eic7700-reset.h new file mode 100644 index 000000000000..7ba31db86141 --- /dev/null +++ b/include/dt-bindings/reset/eswin,eic7700-reset.h @@ -0,0 +1,73 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All right= s reserved. + * + * Device Tree binding constants for EIC7700 reset controller. + * + * Authors: + * Yifeng Huang + * Xuyang Dong + */ + +#ifndef __DT_ESWIN_EIC7700_RESET_H__ +#define __DT_ESWIN_EIC7700_RESET_H__ + +#define SNOC_RST_CTRL 0 +#define GPU_RST_CTRL 1 +#define DSP_RST_CTRL 2 +#define D2D_RST_CTRL 3 +#define DDR_RST_CTRL 4 +#define TCU_RST_CTRL 5 +#define NPU_RST_CTRL 6 +#define HSPDMA_RST_CTRL 7 +#define PCIE_RST_CTRL 8 +#define I2C_RST_CTRL 9 +#define FAN_RST_CTRL 10 +#define PVT_RST_CTRL 11 +#define MBOX_RST_CTRL 12 +#define UART_RST_CTRL 13 +#define GPIO_RST_CTRL 14 +#define TIMER_RST_CTRL 15 +#define SSI_RST_CTRL 16 +#define WDT_RST_CTRL 17 +#define LSP_CFGRST_CTRL 18 +#define U84_RST_CTRL 19 +#define SCPU_RST_CTRL 20 +#define LPCPU_RST_CTRL 21 +#define VC_RST_CTRL 22 +#define JD_RST_CTRL 23 +#define JE_RST_CTRL 24 +#define VD_RST_CTRL 25 +#define VE_RST_CTRL 26 +#define G2D_RST_CTRL 27 +#define VI_RST_CTRL 28 +#define DVP_RST_CTRL 29 +#define ISP0_RST_CTRL 30 +#define ISP1_RST_CTRL 31 +#define SHUTTER_RST_CTRL 32 +#define VO_PHYRST_CTRL 33 +#define VO_I2SRST_CTRL 34 +#define VO_RST_CTRL 35 +#define BOOTSPI_RST_CTRL 36 +#define I2C1_RST_CTRL 37 +#define I2C0_RST_CTRL 38 +#define DMA1_RST_CTRL 39 +#define FPRT_RST_CTRL 40 +#define HBLOCK_RST_CTRL 41 +#define SECSR_RST_CTRL 42 +#define OTP_RST_CTRL 43 +#define PKA_RST_CTRL 44 +#define SPACC_RST_CTRL 45 +#define TRNG_RST_CTRL 46 +#define RESERVED 47 +#define TIMER0_RST_CTRL 48 +#define TIMER1_RST_CTRL 49 +#define TIMER2_RST_CTRL 50 +#define TIMER3_RST_CTRL 51 +#define RTC_RST_CTRL 52 +#define MNOC_RST_CTRL 53 +#define RNOC_RST_CTRL 54 +#define CNOC_RST_CTRL 55 +#define LNOC_RST_CTRL 56 + +#endif /*endif __DT_ESWIN_EIC7700_RESET_H__*/ -- 2.17.1 From nobody Fri Dec 19 20:53:39 2025 Received: from azure-sdnproxy.icoremail.net (l-sdnproxy.icoremail.net [20.188.111.126]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1177479F2; 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dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005152DT.eswin.cn (unknown [10.12.96.41]) by app2 (Coremail) with SMTP id TQJkCgAnuZJ+CUBo7WKaAA--.10072S2; Wed, 04 Jun 2025 16:53:20 +0800 (CST) From: dongxuyang@eswincomputing.com To: p.zabel@pengutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, huangyifeng@eswincomputing.com, Xuyang Dong Subject: [PATCH v2 2/2] reset: eswin: Add eic7700 reset driver Date: Wed, 4 Jun 2025 16:53:16 +0800 Message-Id: <20250604085316.2211-1-dongxuyang@eswincomputing.com> X-Mailer: git-send-email 2.31.1.windows.1 In-Reply-To: <20250604085124.2098-1-dongxuyang@eswincomputing.com> References: <20250604085124.2098-1-dongxuyang@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgAnuZJ+CUBo7WKaAA--.10072S2 X-Coremail-Antispam: 1UD129KBjvJXoW3XFW7Kry5GrW7Gry3CFy8Xwb_yoWfArW5pF WrGFW3Jr4UJr4fWw4xJryv9F4ag3Z3KFyUGrZrKw4Iyw13ta4UJF48tFyrtFyDCryDXFy5 KF12gayruFnxtF7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBv14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26w1j6s0DM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_Jrv_JF1lYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r1q6r43MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw0_GFylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Gr0_Cr1l IxAIcVCF04k26cxKx2IYs7xG6r1j6r1xMIIF0xvEx4A2jsIE14v26r1j6r4UMIIF0xvEx4 A2jsIEc7CjxVAFwI0_Gr0_Gr1UYxBIdaVFxhVjvjDU0xZFpf9x0JUHCJQUUUUU= X-CM-SenderInfo: pgrqw5xx1d0w46hv4xpqfrz1xxwl0woofrz/ Content-Type: text/plain; charset="utf-8" From: Xuyang Dong Add support for reset controller in eic7700 series chips. Provide functionality for asserting and deasserting resets on the chip. Signed-off-by: Yifeng Huang Signed-off-by: Xuyang Dong --- drivers/reset/Kconfig | 10 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-eic7700.c | 234 ++++++++++++++++++++++++++++++++++ 3 files changed, 245 insertions(+) create mode 100644 drivers/reset/reset-eic7700.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index d85be5899da6..82f829f4c9f0 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -66,6 +66,16 @@ config RESET_BRCMSTB_RESCAL This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on BCM7216. =20 +config RESET_EIC7700 + bool "Reset controller driver for ESWIN SoCs" + depends on ARCH_ESWIN || COMPILE_TEST + default ARCH_ESWIN + help + This enables the reset controller driver for ESWIN SoCs. This driver is + specific to ESWIN SoCs and should only be enabled if using such hardwar= e. + The driver supports eic7700 series chips and provides functionality for + asserting and deasserting resets on the chip. + config RESET_EYEQ bool "Mobileye EyeQ reset controller" depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 91e6348e3351..ceafbad0555c 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -12,6 +12,7 @@ obj-$(CONFIG_RESET_BCM6345) +=3D reset-bcm6345.o obj-$(CONFIG_RESET_BERLIN) +=3D reset-berlin.o obj-$(CONFIG_RESET_BRCMSTB) +=3D reset-brcmstb.o obj-$(CONFIG_RESET_BRCMSTB_RESCAL) +=3D reset-brcmstb-rescal.o +obj-$(CONFIG_RESET_EIC7700) +=3D reset-eic7700.o obj-$(CONFIG_RESET_EYEQ) +=3D reset-eyeq.o obj-$(CONFIG_RESET_GPIO) +=3D reset-gpio.o obj-$(CONFIG_RESET_HSDK) +=3D reset-hsdk.o diff --git a/drivers/reset/reset-eic7700.c b/drivers/reset/reset-eic7700.c new file mode 100644 index 000000000000..e651016ea042 --- /dev/null +++ b/drivers/reset/reset-eic7700.c @@ -0,0 +1,234 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright 2024, Beijing ESWIN Computing Technology Co., Ltd.. All right= s reserved. + * + * ESWIN Reset Driver + * + * Authors: + * Yifeng Huang + * Xuyang Dong + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SYSCRG_CLEAR_BOOT_INFO_OFFSET 0x30C +#define CLEAR_BOOT_FLAG_BIT BIT(0) +#define SYSCRG_RESET_OFFSET 0x400 + +/** + * struct eswin_reset_data - reset controller information structure + * @rcdev: reset controller entity + * @dev: reset controller device pointer + * @idr: idr structure for mapping ids to reset control structures + * @regmap: reset controller device register map + */ +struct eswin_reset_data { + struct reset_controller_dev rcdev; + struct device *dev; + struct idr idr; + struct regmap *regmap; +}; + +/** + * struct eswin_reset_control - reset control structure + * @dev_id: SoC-specific device identifier + * @reset_bit: reset mask to use for toggling reset + */ +struct eswin_reset_control { + u32 dev_id; + u32 reset_bit; +}; + +#define to_eswin_reset_data(p) container_of((p), struct eswin_reset_data, = rcdev) + +/** + * eswin_reset_set() - program a device's reset + * @rcdev: reset controller entity + * @id: ID of the reset to toggle + * @assert: boolean flag to indicate assert or deassert + * + * This is a common internal function used to assert or deassert a device's + * reset by clear and set the reset bit. The device's reset is asserted if= the + * @assert argument is true, or deasserted if @assert argument is false. + * + * Return: 0 for successful request, else a corresponding error value + */ +static int eswin_reset_set(struct reset_controller_dev *rcdev, unsigned lo= ng id, + bool assert) +{ + struct eswin_reset_data *data =3D to_eswin_reset_data(rcdev); + struct eswin_reset_control *control; + int ret; + + control =3D idr_find(&data->idr, id); + + if (!control) + return -EINVAL; + + if (assert) + ret =3D regmap_clear_bits(data->regmap, SYSCRG_RESET_OFFSET + + control->dev_id * sizeof(u32), + control->reset_bit); + else + ret =3D regmap_set_bits(data->regmap, SYSCRG_RESET_OFFSET + + control->dev_id * sizeof(u32), + control->reset_bit); + + return ret; +} + +static int eswin_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return eswin_reset_set(rcdev, id, true); +} + +static int eswin_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return eswin_reset_set(rcdev, id, false); +} + +static int eswin_reset_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + int ret; + + ret =3D eswin_reset_assert(rcdev, id); + if (ret !=3D 0) + return ret; + + usleep_range(10, 15); + ret =3D eswin_reset_deassert(rcdev, id); + if (ret !=3D 0) + return ret; + + return 0; +} + +static const struct reset_control_ops eswin_reset_ops =3D { + .reset =3D eswin_reset_reset, + .assert =3D eswin_reset_assert, + .deassert =3D eswin_reset_deassert, +}; + +static int eswin_reset_of_xlate_lookup_id(int id, void *p, void *data) +{ + struct of_phandle_args *reset_spec =3D (struct of_phandle_args *)data; + struct eswin_reset_control *slot_control =3D + (struct eswin_reset_control *)p; + + if (reset_spec->args[0] =3D=3D slot_control->dev_id && + reset_spec->args[1] =3D=3D slot_control->reset_bit) + return id; + + return 0; +} + +/** + * eswin_reset_of_xlate() - translate a set of OF arguments to a reset ID + * @rcdev: reset controller entity + * @reset_spec: OF reset argument specifier + * + * This function performs the translation of the reset argument specifier + * values defined in a reset consumer device node. The function allocates a + * reset control structure for that device reset, and will be used by the + * driver for performing any reset functions on that reset. An idr structu= re + * is allocated and used to map to the reset control structure. This idr + * is used by the driver to do reset lookups. + * + * Return: 0 for successful request, else a corresponding error value + */ +static int eswin_reset_of_xlate(struct reset_controller_dev *rcdev, + const struct of_phandle_args *reset_spec) +{ + struct eswin_reset_data *data =3D to_eswin_reset_data(rcdev); + struct eswin_reset_control *control; + int ret; + + if (WARN_ON(reset_spec->args_count !=3D rcdev->of_reset_n_cells)) + return -EINVAL; + + ret =3D idr_for_each(&data->idr, eswin_reset_of_xlate_lookup_id, + (void *)reset_spec); + if (ret) + return ret; + + control =3D devm_kzalloc(data->dev, sizeof(*control), GFP_KERNEL); + if (!control) + return -ENOMEM; + + control->dev_id =3D reset_spec->args[0]; + control->reset_bit =3D reset_spec->args[1]; + + return idr_alloc(&data->idr, control, 0, 0, GFP_KERNEL); +} + +static const struct of_device_id eswin_reset_dt_ids[] =3D { + { + .compatible =3D "eswin,eic7700-reset", + }, + { /* sentinel */ } +}; + +static int eswin_reset_probe(struct platform_device *pdev) +{ + struct eswin_reset_data *data; + struct device *dev =3D &pdev->dev; + + data =3D devm_kzalloc(&pdev->dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D syscon_node_to_regmap(dev->of_node); + if (IS_ERR(data->regmap)) + return dev_err_probe(dev, PTR_ERR(data->regmap), "failed to get regmap!\= n"); + + platform_set_drvdata(pdev, data); + + data->rcdev.owner =3D THIS_MODULE; + data->rcdev.ops =3D &eswin_reset_ops; + data->rcdev.of_node =3D pdev->dev.of_node; + data->rcdev.of_reset_n_cells =3D 2; + data->rcdev.of_xlate =3D eswin_reset_of_xlate; + data->rcdev.dev =3D &pdev->dev; + data->dev =3D &pdev->dev; + idr_init(&data->idr); + + /* clear boot flag so u84 and scpu could be reseted by software */ + regmap_set_bits(data->regmap, SYSCRG_CLEAR_BOOT_INFO_OFFSET, + CLEAR_BOOT_FLAG_BIT); + msleep(50); + + return devm_reset_controller_register(&pdev->dev, &data->rcdev); +} + +static void eswin_reset_remove(struct platform_device *pdev) +{ + struct eswin_reset_data *data =3D platform_get_drvdata(pdev); + + idr_destroy(&data->idr); +} + +static struct platform_driver eswin_reset_driver =3D { + .probe =3D eswin_reset_probe, + .remove =3D eswin_reset_remove, + .driver =3D { + .name =3D "eswin-reset", + .of_match_table =3D eswin_reset_dt_ids, + }, +}; + +static int __init eswin_reset_init(void) +{ + return platform_driver_register(&eswin_reset_driver); +} +arch_initcall(eswin_reset_init); --=20 2.17.1