From nobody Mon Oct 20 09:40:48 2025 Received: from mail-pl1-f177.google.com (mail-pl1-f177.google.com [209.85.214.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC9D202997 for ; Wed, 4 Jun 2025 17:16:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.177 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749057388; cv=none; b=MtKl9LFaPe6IBslJMxD2Wjvm168dpwPZ6zljP9PCOpgD2DGjS5wnP4TPoSYNJX1UV/bJnkcTe/ndAKWauLZGwPD25JSbu4dGFC+Sd8eKU42TFxNFZg2hTExdfHexFpmVKYc9DMqKO/BpU+L1ZZnTjLHsyLVYS+ORB+94sODc51g= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749057388; c=relaxed/simple; bh=ynTUDLBp2gEKhFeiYfxgOCPe6wht1rOzpyg0Vu3jGXs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=R7I6qxdis4yKeB2AuL3gyxhj9CRz68hIiHXbq3D2LjH1rQnbQQIPv+Bctc7qjWgpFe3ntjWZqDSYNEJA7r8Ul+xDb/pu0YgA4TOGqeP96uuHgbRYe6NfjgIvW4Xnhe1HzZbYr/4aVeayxtCnDpPvHVFhwzQXhPObFvxjH6t+ssc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com; spf=pass smtp.mailfrom=rivosinc.com; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b=bGMRT4jX; arc=none smtp.client-ip=209.85.214.177 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=rivosinc.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=rivosinc-com.20230601.gappssmtp.com header.i=@rivosinc-com.20230601.gappssmtp.com header.b="bGMRT4jX" Received: by mail-pl1-f177.google.com with SMTP id d9443c01a7336-234bfe37cccso1148645ad.0 for ; Wed, 04 Jun 2025 10:16:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20230601.gappssmtp.com; s=20230601; t=1749057385; x=1749662185; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Ome3u7rmCNb01KyjL0hHySpySbFvJDab/QcqkVOgxo4=; b=bGMRT4jXUFfL6pialkPmDofJUp7aaUhI5yJDVHaddRB7MYV7qPIJyBC6KWl/QdSKEo gxn41IhyEkEm9r0y7HmhHkawBcWnplkzf4ls17WbrvqV/UDR6GizCkso6LuBFxxcG/MG EsxaPasXuyu0lZJ6WWSapIQFtQu9miOva+jyD6kTOMe45PnQpvwmV28Qsz7q6CUdc4Zz NbUB64izqER6F72h0KQK00i2+aQ0PCGi6MtIIxBRocjGvWcDaOSVd0jsVTstg1lAWeqc JOyQVgrFhYmhr1SpVZWtC//nkeIiVjz7v4jh6OTn2jSdmFjGcmQuc6miCEOPBRtuUHD9 w//A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749057385; x=1749662185; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Ome3u7rmCNb01KyjL0hHySpySbFvJDab/QcqkVOgxo4=; b=t6fzqioucWui1PuixYH8THZow/d30tG7FWkKIj2nFQb78oL5C2kZYakK8wQbMv7Wyl l+LBpLKev647/xFJWO/bF/7k47HT9aBRodGVJ2nvnaOMRs/OCkzgMwbUFW/0Pptu0y+3 ldsThVLjAF77r7GFb/RAcTHrLgYJ4P+FPCFJVKKxusE5JHdYghxvog98SmBwfDaO6TxR 5BWe0dfloMGLvXr2iiTEIqSGgOqUmtoWxRn9acihKyfVzp7UCviGRxKKaGX0OAHRe3CH 67VuSRRQ3XbzrphQd7ge+iT+D1R8URT73g+4JHXnf2U54WlPzLOHVRM5xSORDh7edtH5 aDLA== X-Gm-Message-State: AOJu0YyiW60dYOv1kWZlr9LrfqXjrbdicICb1ntn8FZklga6rsBuIMat ciLXisq8+DSdIRdPz748TUK0lZzqGZ8vOUMmtk0davQDwf0UIip8eOWJcf14lO9YmVw= X-Gm-Gg: ASbGncv6NBuKAp/9mEqGgeMcVeR3gVxASVweAgyi4JrogG2fm6R6463NZilVzCf5AQY rQmsrhy3NE3VeX+eppJvynssU7buUDr7W6AKOehi0E/S612zOXbE6phjQfoicymDho54+WZWwhj vITRcuEImMh+hQT00BkiF+VtJBPELvbwAp95uIbnjg/zgMK06wC3E17ss/vajorm5k9+AOnlM0J A1sNppDsIJ/8Zf0SxvhzcJ/VBYBybJagByT7O/4V2sSrzvVWoekMeRMeqpqE43UwmwWXnVPie3+ UmE8kNdz3MQXP6ISSop3N29U4paF/MbxNbFc0LwOWJm4SNqMtsDOj/KG4Qu06nFrQK3J6AzX X-Google-Smtp-Source: AGHT+IHOq7jdfe1QXesVQTTYh9pdMzuQq9fifPPejLKBYzrKsJ2+M42lgYFnihYLRnJ8kIRxucrJ3w== X-Received: by 2002:a17:903:1b45:b0:234:d292:be84 with SMTP id d9443c01a7336-235e110dc8dmr60521145ad.10.1749057385225; Wed, 04 Jun 2025 10:16:25 -0700 (PDT) Received: from debug.ba.rivosinc.com ([64.71.180.162]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3124e2e9c9fsm9178972a91.30.2025.06.04.10.16.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 10:16:24 -0700 (PDT) From: Deepak Gupta Date: Wed, 04 Jun 2025 10:15:28 -0700 Subject: [PATCH v17 04/27] riscv: zicfiss / zicfilp extension csr and bit definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-v5_user_cfi_series-v17-4-4565c2cf869f@rivosinc.com> References: <20250604-v5_user_cfi_series-v17-0-4565c2cf869f@rivosinc.com> In-Reply-To: <20250604-v5_user_cfi_series-v17-0-4565c2cf869f@rivosinc.com> To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org, "H. Peter Anvin" , Andrew Morton , "Liam R. Howlett" , Vlastimil Babka , Lorenzo Stoakes , Paul Walmsley , Palmer Dabbelt , Albert Ou , Conor Dooley , Rob Herring , Krzysztof Kozlowski , Arnd Bergmann , Christian Brauner , Peter Zijlstra , Oleg Nesterov , Eric Biederman , Kees Cook , Jonathan Corbet , Shuah Khan , Jann Horn , Conor Dooley , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross Cc: linux-kernel@vger.kernel.org, linux-fsdevel@vger.kernel.org, linux-mm@kvack.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org, alistair.francis@wdc.com, richard.henderson@linaro.org, jim.shu@sifive.com, andybnac@gmail.com, kito.cheng@sifive.com, charlie@rivosinc.com, atishp@rivosinc.com, evan@rivosinc.com, cleger@rivosinc.com, alexghiti@rivosinc.com, samitolvanen@google.com, broonie@kernel.org, rick.p.edgecombe@intel.com, rust-for-linux@vger.kernel.org, Deepak Gupta X-Mailer: b4 0.13.0 zicfiss and zicfilp extension gets enabled via b3 and b2 in *envcfg CSR. menvcfg controls enabling for S/HS mode. henvcfg control enabling for VS while senvcfg controls enabling for U/VU mode. zicfilp extension extends *status CSR to hold `expected landing pad` bit. A trap or interrupt can occur between an indirect jmp/call and target instr. `expected landing pad` bit from CPU is recorded into xstatus CSR so that when supervisor performs xret, `expected landing pad` state of CPU can be restored. zicfiss adds one new CSR - CSR_SSP: CSR_SSP contains current shadow stack pointer. Signed-off-by: Deepak Gupta Reviewed-by: Charlie Jenkins --- arch/riscv/include/asm/csr.h | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/arch/riscv/include/asm/csr.h b/arch/riscv/include/asm/csr.h index 6fed42e37705..2f49b9663640 100644 --- a/arch/riscv/include/asm/csr.h +++ b/arch/riscv/include/asm/csr.h @@ -18,6 +18,15 @@ #define SR_MPP _AC(0x00001800, UL) /* Previously Machine */ #define SR_SUM _AC(0x00040000, UL) /* Supervisor User Memory Access */ =20 +/* zicfilp landing pad status bit */ +#define SR_SPELP _AC(0x00800000, UL) +#define SR_MPELP _AC(0x020000000000, UL) +#ifdef CONFIG_RISCV_M_MODE +#define SR_ELP SR_MPELP +#else +#define SR_ELP SR_SPELP +#endif + #define SR_FS _AC(0x00006000, UL) /* Floating-point Status */ #define SR_FS_OFF _AC(0x00000000, UL) #define SR_FS_INITIAL _AC(0x00002000, UL) @@ -212,6 +221,8 @@ #define ENVCFG_PMM_PMLEN_16 (_AC(0x3, ULL) << 32) #define ENVCFG_CBZE (_AC(1, UL) << 7) #define ENVCFG_CBCFE (_AC(1, UL) << 6) +#define ENVCFG_LPE (_AC(1, UL) << 2) +#define ENVCFG_SSE (_AC(1, UL) << 3) #define ENVCFG_CBIE_SHIFT 4 #define ENVCFG_CBIE (_AC(0x3, UL) << ENVCFG_CBIE_SHIFT) #define ENVCFG_CBIE_ILL _AC(0x0, UL) @@ -230,6 +241,11 @@ #define SMSTATEEN0_HSENVCFG (_ULL(1) << SMSTATEEN0_HSENVCFG_SHIFT) #define SMSTATEEN0_SSTATEEN0_SHIFT 63 #define SMSTATEEN0_SSTATEEN0 (_ULL(1) << SMSTATEEN0_SSTATEEN0_SHIFT) +/* + * zicfiss user mode csr + * CSR_SSP holds current shadow stack pointer. + */ +#define CSR_SSP 0x011 =20 /* mseccfg bits */ #define MSECCFG_PMM ENVCFG_PMM --=20 2.43.0