From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f41.google.com (mail-ed1-f41.google.com [209.85.208.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CC87218B47E for ; Wed, 4 Jun 2025 15:25:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050748; cv=none; b=hpqLJSzpn2UTNTFY+5bZnVoW7IdzhjxWdXPlcCB1zD03dp2CRE+5rEPk5aS/iGujTgl9swCPXUhpGmgp5b3GtOlyE3r1lY5dp8o8AzOaPN1euWVvsRqmEnQ918iA81uCwD/XXEn5qFEU/gCScfM5Jr99Ee1MIfu4/C5LpJtg9PY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050748; c=relaxed/simple; bh=/zu0WY1mTLJkmQKe0QzKVdlleBAaRvg5u4/DVEDJoYs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qri1V1PaNRJeHSmjs+a4X4gyMDZ8KNcIS0fBXJ/Kt+7O4yucm/ftNMEOCg+KVFOPtMDC9A2tiuw2RHCTtKymUy8v321ebatDWabw9CCo8KQCdC5iqOt9NU4vW0cnK2xKenvrfzCXSPku3GEV9HfbLL7oqlRYICgqSLkyRREioeY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=qI8omZnY; arc=none smtp.client-ip=209.85.208.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qI8omZnY" Received: by mail-ed1-f41.google.com with SMTP id 4fb4d7f45d1cf-5efe8d9ebdfso13503486a12.3 for ; Wed, 04 Jun 2025 08:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050745; x=1749655545; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Tj36HcfLXbrHMi0m60w9d5+4mHUGkz0YH63xXCl7mlk=; b=qI8omZnYK63Gb3gfqVrMQYrcAeOkEb7jdjavka/WAWHIxL/QL5ypm1bm5xzQsrx2DV ljun/e+RnC0KerzAN1vGJ07NRXgwlz+wbzV+WsH3g8pzg3UrZfamdIySsqhV9aWnzXrB V3vbLMhg9JfSP/rSmTuu6iYGxwXw6KW5pT9DaJ1TBTqs583OYDJ+blmh80W9BZvWb6dE mEDCsvZuY0zj7+rwBxMs05Le9ZmeX9pY4At4EzMURjgqoo18iXr7m5Ztkgd5WE1pV9W6 mR0QY7S4KwByWpvk92AiVpT4jS9MUKHA/2jHtwD1S4UTYUagd/Txp563a9yt3lzQDSGf 5VoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050745; x=1749655545; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Tj36HcfLXbrHMi0m60w9d5+4mHUGkz0YH63xXCl7mlk=; b=Voo73aya+hD+ERUnML0ytvvGLU8fYAJMFfM2lXCDBH1M/c4i/o36I8zCKzJ7PhtIEB g/DRNKnxNOA6HfVSdH7BSmW2k8lNFlpkNefb9+NZNpm0sVZHHbeNnrxD36fqV+A/c/ZW xNEHpor6PTOab4E4yJ9vwgN/8h7J3PnJzrqlVmLpbL/HfKw2Q+SyOSGFSQLczZkq1C37 T235m2twE+yNDRUlFxC3vfWJDSlb7I3K/edPgpL0TXJld+BNDRTNpgXQaCED13gY5/ok hqN1kaaDaXwjbutA2pyHGyn//bQJalILD1nRktZnc17pgkbH790uU1jRR2mJKCFmxz3l CNfw== X-Forwarded-Encrypted: i=1; AJvYcCUZDygcKxuI0mMkA1pq9+9wF//iAr4I6XpVLT4g3LbCm71qnhXsl2jKM5HuEmmQEVoQWGXXKFEqFoweNZI=@vger.kernel.org X-Gm-Message-State: AOJu0YzC4Pf4ltCy3dACzTNwlmyOrpBXMcHaI4RNToiKhpI9OscmOiyS RA75aEsG1Blf2bgeB839EIRP3A8Br6tLffVCop3mtH7RGl7yt/Qm5UitZ+8xFCnIkxQ= X-Gm-Gg: ASbGncsBP63J994HSRGx1JGKNLSaV1+TYOD0JDnkM/SNlQV8bI3n81M6Iqs8dgU22d+ 0CRyHMUDQ3nEJ2Wr/seskwQVonPgXRbGBVA4qbo0A3gG4/zHjGQh+YPePt51o2aoToh4sHQzft7 QFzXClMumATSgsiu3EvlSQ0irxKGGhiygnzfjUcoAZ4zOWGKcN6c6Uu0WwYCaqyb8F5G/GRwdNy 9/fGPQlIOm26Lh/j4YingYzp/D7qLJzAD7EcCakPxLXBYlnOz+6J3VgEK765cRG37wz5sLCnF1C lBxeIRd6Ko23PJEJdN+uQcnuiqNKD5F7G1t2EXrNf5nu1rUJzsQeXwGsdGZbVrfy2ejS8+3XVjg 2WCntLZt/fF5bFqwvTsqgrxB3qtAoR8w7YYdxbkifwy+tRw== X-Google-Smtp-Source: AGHT+IHDbl+PPXNilHwRHoApPiua2emH1u8FPEEM6gtKEx+PJ/5CtghVWo7/Vf4dwmLj4wdHx4mOIQ== X-Received: by 2002:a05:6402:510a:b0:602:120c:f8d8 with SMTP id 4fb4d7f45d1cf-606ea179fb9mr3445618a12.18.1749050744799; Wed, 04 Jun 2025 08:25:44 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:44 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:40 +0100 Subject: [PATCH 01/17] dt-bindings: firmware: google,gs101-acpm-ipc: convert regulators to lowercase Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-1-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Using lowercase for the buck and ldo nodenames is preferred, as evidenced e.g. in [1]. Convert the example here to lowercase before we add any bindings describing the s2mpg1x regulators that will enforce the spelling. Link: https://lore.kernel.org/all/20250223-mysterious-infrared-civet-e5bcbf= @krzk-bin/ [1] Signed-off-by: Andr=C3=A9 Draszik --- Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml | 4 = ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index 9785aac3b5f34955bbfe2718eec48581d050954f..62a3a7dac5bd250a7f216c72f33= 15cd9632d93e1 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -64,7 +64,7 @@ examples: interrupts-extended =3D <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; =20 regulators { - LDO1 { + ldo1m { regulator-name =3D "vdd_ldo1"; regulator-min-microvolt =3D <700000>; regulator-max-microvolt =3D <1300000>; @@ -73,7 +73,7 @@ examples: =20 // ... =20 - BUCK1 { + buck8m { regulator-name =3D "vdd_mif"; regulator-min-microvolt =3D <450000>; regulator-max-microvolt =3D <1300000>; --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4D3111917D6 for ; Wed, 4 Jun 2025 15:25:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050751; cv=none; b=Dhhe8faSOR2SHQL257NI2uMQurpANLWnxabK6d+ZInbiZCq1/I+dJpPpqhk4Pu3T2kTFa6Hs/dUzgr9clZsApt304eri9MBojpOY/kICXfbEJsuzOsfAjjKUosMwswlrJHGwC8FMnKw3hE7sQq+mtSlxpMQ5NvZh85UGPfBWmaw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050751; c=relaxed/simple; bh=tb3rroKay4WoCawP75y+rMOWHLoXWxx0UmTY54Zml58=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bwAZ1B+rJVSTgXtGQBnWg9diILzlDAgvjbLwE5NOnOboHNyrBNXXgB2jQZYXUV9h+Vwd2uYfbJ0qGqTut/oDAPRo3t6YsTfKGCpjk0l5H/VPLLcSH4Qa0fLYj91430yGFxW4AUk8FKF3YWAcmP86m0XSe/RDAyGQ1w1TE+7plsA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=PqG/MkE5; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="PqG/MkE5" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-606fdbd20afso1477123a12.1 for ; Wed, 04 Jun 2025 08:25:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050745; x=1749655545; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=LsPj87HjS8BwizaOPE7vMLxiKmx0PFqGIoSdAB4ijFI=; b=PqG/MkE5kdiVigWqtpZcE6LV/rgfEIDBVSlfzQjrrL3Jd3ovZft4bkHT2Sk4U4mTJd /Q0dfEwn93l8bXNckfpMTJjTwrVSenDvT3Chm7jMhNYc2ElfS2SCZgt+XhFpxyDRBqJs 7L+QV27Ux5RflCDu1/agh9cyvKXGjdbJwIZzYlUfFVt7rRppXTjstuzNphxFE4i4idlL 6VZBjxRv3+KBJyA7r95j84zkZu2UAseGEOtBXexauCdkWGI866/QGxsE4SWyx8wjkFen cFzXSIgXgFq2LUg0j02br5VJNA8g80YPKxIXc6pcyHW+spKHlHUCAtW7RcLDQGii83lr 0eIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050745; x=1749655545; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=LsPj87HjS8BwizaOPE7vMLxiKmx0PFqGIoSdAB4ijFI=; b=TVmjbHBHaB8b9ARUS33hAgJ4L0TKkW7/PWfTFA01MyokpuLTJLOpKsASmDVZVJa1wm GS+m/z3qv224q3dTGxq80QhSIq0dFhCzXcaJNNTyrhD+tYfUmGo/5jspnob+kr1u6XP/ c5uDsRdn/JGE7U9ehHrrhVE03LtVwwR8DYBWKV5fiq8SAIW87XeLUbW6GF+SjkY7mJbJ av7KAkQB02QEbTDFgLb0rTz5zghxjd9f/H1QtXBsxadiyGMwG8z5qQqBYWPzTbT+sQUd MYaCdT1gnrD93f0JpOGxaVW9guH2kuonNtSNyXHPQNFmmRmv/Cgb3hr176+QhwmF1qdn FSBw== X-Forwarded-Encrypted: i=1; AJvYcCUH3rd78uYigZBOmIOR6Sxgqba8R6fQbUEiqdj24KjLCh9bXYnPIc+NIc/8AjoMH8LsmxYOs9W91D1VII4=@vger.kernel.org X-Gm-Message-State: AOJu0YyxIVUnaDN+GQbOxMFDBs050JXEIlRDrzZYke2HGxYeqMDJZM77 uYgMYpyo+ZkgMIXJC/PSZpWzTmULFudHSWYmTpjrrwsDPubcxRd7NKPn3jnQzPNHXFI= X-Gm-Gg: ASbGncsX+u4Ld0y+hfXFaEShEyBG01pn0tbxD8JPQmwbPOVJQ8soBlOUJkGrl3kz/Y5 CP+Pw/V4Z50ooGTSjqyeOsLaVaaik6r6jKNfWXHigCtx1E+psnmKSiR7FRCo1IdVUrGtn1WPSVa 3WgVugwq8gc0Wjb0V1QzEYgnLqw+zfrAwT5vBW7/e48CctuYgYTRBcfLeo7XIIF5NQAXXBgb5pX NpeOZ2ENDRDX38bJjsG8xDue4xkGWj4Fc0ps2fMCv5n/jOJUR5hP/6AN6cqagTIhsuQvA9rwmt7 kuwJLmCIR0Uk72Fd4g52phFKuYA3gwoYDGMZPzKgrWwNu4ClSRsmUIujJWp7nxnq5P3gfQWG12K Q+G46Yj2TZ8auzMRMzUzLL4RuBvSPtDlRZK3PQ9TlZ9TLdQ== X-Google-Smtp-Source: AGHT+IGhug7cxl/cassO/IyqM1BYqI+HrlsCLUeenObP/OwkoMoie1gUxelDQw1up4SjYw8ESiGKSQ== X-Received: by 2002:a05:6402:26d0:b0:604:5cae:4031 with SMTP id 4fb4d7f45d1cf-606ea191815mr3688677a12.28.1749050745442; Wed, 04 Jun 2025 08:25:45 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:45 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:41 +0100 Subject: [PATCH 02/17] regulator: dt-bindings: add s2mpg10-pmic regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-2-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG10 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, RTC, clock outputs, and additional GPIOs interfaces. It has 10 buck and 31 LDO rails. Several of these can either be controlled via software or via external signals, e.g. input pins connected to a main processor's GPIO pins. Add documentation related to the regulator (buck & ldo) parts like devicetree definitions, regulator naming patterns, and additional properties. S2MPG10 is typically used as the main-PMIC together with an S2MPG11 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the rails with an 'm'. Signed-off-by: Andr=C3=A9 Draszik --- .../regulator/samsung,s2mpg10-regulator.yaml | 147 +++++++++++++++++= ++++ MAINTAINERS | 1 + .../regulator/samsung,s2mpg10-regulator.h | 48 +++++++ 3 files changed, 196 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mpg10-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mpg10-= regulator.yaml new file mode 100644 index 0000000000000000000000000000000000000000..42dadf8a2ef606d85d66dca2470= d44871f2d8d4b --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mpg10-regulator= .yaml @@ -0,0 +1,147 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpg10-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPG10 Power Management IC regulators + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is part of the device tree bindings for the S2MG10 Power Management= IC + (PMIC). + + The S2MPG10 PMIC provides 10 buck and 31 LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +definitions: + s2mpg10-ext-control: + properties: + samsung,ext-control: + description: | + These rails can be controlled via one of several possible extern= al + (hardware) signals. If so, this property configures the signal t= he PMIC + should monitor. For S2MPG10 rails where external control is poss= ible other + than ldo20m, the following values generally corresponding to the + respective on-chip pin are valid: + - 0 # S2MPG10_PCTRLSEL_ON - always on + - 1 # S2MPG10_PCTRLSEL_PWREN - PWREN pin + - 2 # S2MPG10_PCTRLSEL_PWREN_TRG - PWREN_TRG bit in MIMICKING_= CTRL + - 3 # S2MPG10_PCTRLSEL_PWREN_MIF - PWREN_MIF pin + - 4 # S2MPG10_PCTRLSEL_PWREN_MIF_TRG - PWREN_MIF_TRG bit in MI= MICKING_CTRL + - 5 # S2MPG10_PCTRLSEL_AP_ACTIVE_N - ~AP_ACTIVE_N pin + - 6 # S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG - ~AP_ACTIVE_N_TRG bit = in MIMICKING_CTRL + - 7 # S2MPG10_PCTRLSEL_CPUCL1_EN - CPUCL1_EN pin + - 8 # S2MPG10_PCTRLSEL_CPUCL1_EN2 - CPUCL1_EN & PWREN pins + - 9 # S2MPG10_PCTRLSEL_CPUCL2_EN - CPUCL2_EN pin + - 10 # S2MPG10_PCTRLSEL_CPUCL2_EN2 - CPUCL2_E2 & PWREN pins + - 11 # S2MPG10_PCTRLSEL_TPU_EN - TPU_EN pin + - 12 # S2MPG10_PCTRLSEL_TPU_EN2 - TPU_EN & ~AP_ACTIVE_N pins + - 13 # S2MPG10_PCTRLSEL_TCXO_ON - TCXO_ON pin + - 14 # S2MPG10_PCTRLSEL_TCXO_ON2 - TCXO_ON & ~AP_ACTIVE_N pins + + For S2MPG10 ldo20m, the following values are valid + - 0 # S2MPG10_PCTRLSEL_LDO20M_ON - always on + - 1 # S2MPG10_PCTRLSEL_LDO20M_EN_SFR - VLDO20M_EN & LDO20M_SFR + - 2 # S2MPG10_PCTRLSEL_LDO20M_EN - VLDO20M_EN pin + - 3 # S2MPG10_PCTRLSEL_LDO20M_SFR - LDO20M_SFR in LDO_CTRL1 re= gister + - 4 # S2MPG10_PCTRLSEL_LDO20M_OFF - disable + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 14 + + samsung,ext-control-gpios: + description: | + For rails where external control is done via a GPIO, this option= al + property describes the GPIO line used. + + maxItems: 1 + + dependentRequired: + samsung,ext-control-gpios: [ "samsung,ext-control" ] + +patternProperties: + # 10 bucks + "^buck([1-9]|10)m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single buck regulator. + + properties: + regulator-ramp-delay: + enum: [6250, 12500, 25000] + default: 6250 + + allOf: + - $ref: "#/definitions/s2mpg10-ext-control" + + # 13 standard LDOs + "^ldo([12]|2[1-9]|3[0-1])m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + properties: + regulator-ramp-delay: false + + # 14 LDOs with possible external control + "^ldo([3-9]|1[046-9]|20)m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + properties: + regulator-ramp-delay: false + + allOf: + - $ref: "#/definitions/s2mpg10-ext-control" + + # 4 LDOs with ramp support and possible external control + "^ldo1[1235]m$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + properties: + regulator-ramp-delay: + enum: [6250, 12500] + default: 6250 + + allOf: + - $ref: "#/definitions/s2mpg10-ext-control" + +additionalProperties: false + +allOf: + - if: + anyOf: + - required: [buck8m] + - required: [buck9m] + then: + patternProperties: + "^buck[8-9]m$": + properties: + samsung,ext-control: false + + - if: + required: + - ldo20m + then: + properties: + ldo20m: + properties: + samsung,ext-control: + maximum: 4 diff --git a/MAINTAINERS b/MAINTAINERS index 1615a93528bdfffa421eb8cad259fecd1488fc51..3fc6bd0dd15a504c498e56d4257= 31b5234dce63a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22006,6 +22006,7 @@ F: drivers/mfd/sec*.[ch] F: drivers/regulator/s2m*.c F: drivers/regulator/s5m*.c F: drivers/rtc/rtc-s5m.c +F: include/dt-bindings/regulator/samsung,s2m*.h F: include/linux/mfd/samsung/ =20 SAMSUNG S3C24XX/S3C64XX SOC SERIES CAMIF DRIVER diff --git a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h b/in= clude/dt-bindings/regulator/samsung,s2mpg10-regulator.h new file mode 100644 index 0000000000000000000000000000000000000000..1d4e34a756efa46afeb9f018c3e= 8644ebc373b07 --- /dev/null +++ b/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h @@ -0,0 +1,48 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright 2021 Google LLC + * Copyright 2025 Linaro Ltd. + * + * Device Tree binding constants for the Samsung S2MPG1x PMIC regulators + */ + +#ifndef _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H +#define _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H + +/* + * Several regulators may be controlled via external signals instead of via + * software. These constants describe the possible signals for such regula= tors + * and generally correspond to the respecitve on-chip pins. The constants + * suffixed with _TRG enable control using the respective bits in the + * MIMICKING_CTRL register instead. + * + * S2MPG10 regulators supporting these are: + * - buck1m .. buck7m buck10m + * - ldo3m .. ldo19m + * + * ldo20m supports external control, but using a different set of control + * signals. + */ +#define S2MPG10_PCTRLSEL_ON 0x0 /* always on */ +#define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */ +#define S2MPG10_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKIN= G_CTRL */ +#define S2MPG10_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */ +#define S2MPG10_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMI= CKING_CTRL */ +#define S2MPG10_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */ +#define S2MPG10_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in M= IMICKING_CTRL */ +#define S2MPG10_PCTRLSEL_CPUCL1_EN 0x7 /* CPUCL1_EN pin */ +#define S2MPG10_PCTRLSEL_CPUCL1_EN2 0x8 /* CPUCL1_EN & PWREN pins */ +#define S2MPG10_PCTRLSEL_CPUCL2_EN 0x9 /* CPUCL2_EN pin */ +#define S2MPG10_PCTRLSEL_CPUCL2_EN2 0xa /* CPUCL2_E2 & PWREN pins */ +#define S2MPG10_PCTRLSEL_TPU_EN 0xb /* TPU_EN pin */ +#define S2MPG10_PCTRLSEL_TPU_EN2 0xc /* TPU_EN & ~AP_ACTIVE_N pin= s */ +#define S2MPG10_PCTRLSEL_TCXO_ON 0xd /* TCXO_ON pin */ +#define S2MPG10_PCTRLSEL_TCXO_ON2 0xe /* TCXO_ON & ~AP_ACTIVE_N pi= ns */ + +#define S2MPG10_PCTRLSEL_LDO20M_ON 0x0 /* always on */ +#define S2MPG10_PCTRLSEL_LDO20M_EN_SFR 0x1 /* LDO20M_EN & LDO20M_SFR */ +#define S2MPG10_PCTRLSEL_LDO20M_EN 0x2 /* VLDO20M_EN pin */ +#define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTR= L1 register */ +#define S2MPG10_PCTRLSEL_LDO20M_OFF 0x4 /* disable */ + +#endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */ --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EFB4C192D83 for ; Wed, 4 Jun 2025 15:25:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050750; cv=none; b=OgDEO3Pq1kPPOG6BmqT++XtO5F2nWI4oioTZbZRIr2KmLh8UYBJY9cXoqwSklFOQlLWrT5clfWcAvTlNibX2lry/xhLiw6idBfeq4KJ6lP0ljVi5gQsMRq7m1k6hcsbA1qsKKE1ZlxFRrMk1FeMbKNe9cte9XRO6SOKrdbRv98s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050750; c=relaxed/simple; bh=i7LYP+2b/HhCF2Z1/IxiMY41qTXY9usnHls789FLRiY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=JG1Bu9CMMbTb9sYNYQLgOTiGvipxYDiBBFLTfKa5OGoSbsMeBCUg/uM8Uhy/dOAEyMeKPC8YCRF7c+bADlbrBjhqfl/6GhJ5XohjnwCIS5hvaBBjsdAF2AUe3zIS2oHRb4a1+SwG03JSP9xGeUzqXen25e34vzJ0RW5nQzSCBbU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KbyHrIEY; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KbyHrIEY" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-606bbe60c01so3622730a12.2 for ; Wed, 04 Jun 2025 08:25:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050746; x=1749655546; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=y/Nuhjkvj2i8BYs2yY8o0DBKFzqmFzKeDEHJy4UYUW4=; b=KbyHrIEYUN26mnkqWSrWSJd5KNb4MpWT217AzQ8UD1twgK0n2hXlsZ1n1uH9x/12zp EuNyRt2g08UFW6eZoOVMJrlKBTlx90fjwksopv0KI6IdpqQJFiAr8AMQyw5HUvh9NzJA G4H+vg++OFqqWp/U6f1oZeqVhsMKFa5VzRr1ZYrIlLBs2ADdp1LIvHYtrdGi7EW0ASoZ 1u+lkngxb81NswwMp6pEf/TPoiBxsXpKXAoEykVMKWtIbWjvqOoETdzQUs2UwAl+JdAN acTKLIubHDJs+aRKYCf4lk31T+t7Rx8B3Mbw7sryu5v8Cnf9WibdLAScD8A175rUTQ3l djSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050746; x=1749655546; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=y/Nuhjkvj2i8BYs2yY8o0DBKFzqmFzKeDEHJy4UYUW4=; b=GdbjkkUqVNe70E2eNxKw8K2MJbelhuo7IpVtCfBjUj/BeuRLQsNPsgyc8PENT2AQYo ouh9H7yPMRdBK/sZUXpPiFkgTd6syVBHo6N0ClvKJ7sf3Sk1yqFkfcUncIQIOT4oeNKg eNBFC97v/036iMSLn3mEz4pAr+rlHqIVswZjkDxv3hq6yS0co1Xy5HZ+IFt24ltjt2Lg CSznsVYgejfz+JWFeTIekUsJJl+hZaidpGIGVzH6uXaBusnPYqGSzL6c87L9nFUbUDsO rSQOB5LkusaMVxIR8MKpUD9frXLvTgpAPSTwm3h1ZQttduYf1uM/oXjMXu0YHW/wOF2e p6PA== X-Forwarded-Encrypted: i=1; AJvYcCU7JBjaDV0bRuqQHptu1tCKQUPWI7xfuULTZDZ6ebVhaA2re0wQrzQu+BbOletPCmy2iCG9JUmxiqrx1Sc=@vger.kernel.org X-Gm-Message-State: AOJu0YyuMOy+HT43QfeWkSfjm8dJHGafIPew57rs9OI1o+o11IrOKPrH JMpNAWrqvvY2/IE8DJ/AJxnF9eY6Jp3R5Y1kSCG3acNO1FBf13Yqjs0qYIfC1sXry6w= X-Gm-Gg: ASbGncvqaClieg6mTO3WRgmW/9fRicg3KLUHZBAHz7Q4m52eE+zjAN68JwkVt2KEMkJ 1Dlt1mw1nQu9MlmgsKe6EOhwQH47rVVrOsyl9k9to9CP1T31pGxuQYYszC9XHQUPJnc0/uLZJfu 0KmQ2QRO8w5oNdXRRYIhcMhJKK6iwSZWymlivkW7BFWdOxJHv89GEpg8NkatJcHihZkBAB28P31 mn8jULhKmWDQRtnBTWQE1HNWfWR4dyqgCesufNjGjJvlCBh8HSAm89jxawTEhNMUscvHhCajcj7 /3ZmCYUQf3jcCfFSkKJzJL3KcOJi7jNB3TQ4ylJ8/0dChd7bF7kT5hPYaPReNTXLCv8Wt+UfsT2 8oglSE838nqvWhdxwyZau0nNNKS2SZx5hAVg= X-Google-Smtp-Source: AGHT+IGNeOInImc3IiLEgN6dgTSjuYlEJ0cGTX8zNFDeGDe2e91LE/P2zcqlG80knQ7jcN+ctu99FA== X-Received: by 2002:a05:6402:50c9:b0:601:a681:4d5c with SMTP id 4fb4d7f45d1cf-606ea15f66fmr3407522a12.32.1749050746101; Wed, 04 Jun 2025 08:25:46 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:45 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:42 +0100 Subject: [PATCH 03/17] regulator: dt-bindings: add s2mpg11-pmic regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-3-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG11 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, and power meters. It typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. S2MPG11 has 12 buck, 1 buck-boost, and 15 LDO rails. Several of these can either be controlled via software or via external signals, e.g. input pins connected to a main processor's GPIO pins. Add documentation related to the regulator (buck & ldo) parts like devicetree definitions, regulator naming patterns, and additional properties. Since S2MPG11 is typically used as the sub-PMIC together with an S2MP10 as the main-PMIC, the datasheet and the binding both suffix the rails with an 's'. Signed-off-by: Andr=C3=A9 Draszik --- Note: checkpatch suggests to update MAINTAINERS, but the new file is covered already due to using a wildcard. --- .../regulator/samsung,s2mpg11-regulator.yaml | 150 +++++++++++++++++= ++++ .../regulator/samsung,s2mpg10-regulator.h | 18 +++ 2 files changed, 168 insertions(+) diff --git a/Documentation/devicetree/bindings/regulator/samsung,s2mpg11-re= gulator.yaml b/Documentation/devicetree/bindings/regulator/samsung,s2mpg11-= regulator.yaml new file mode 100644 index 0000000000000000000000000000000000000000..f2d596642501c197e2911ee3b9c= aac189cf541a4 --- /dev/null +++ b/Documentation/devicetree/bindings/regulator/samsung,s2mpg11-regulator= .yaml @@ -0,0 +1,150 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/regulator/samsung,s2mpg11-regulator.yam= l# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Samsung S2MPG11 Power Management IC regulators + +maintainers: + - Andr=C3=A9 Draszik + +description: | + This is part of the device tree bindings for the S2MG11 Power Management= IC + (PMIC). + + The S2MPG11 PMIC provides 12 buck, 1 buck-boost, and 15 LDO regulators. + + See also Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml for + additional information and example. + +definitions: + s2mpg11-ext-control: + properties: + samsung,ext-control: + description: | + These rails can be controlled via one of several possible extern= al + (hardware) signals. If so, this property configures the signal t= he PMIC + should monitor. The following values generally corresponding to = the + respective on-chip pin are valid: + - 0 # S2MPG11_PCTRLSEL_ON - always on + - 1 # S2MPG11_PCTRLSEL_PWREN - PWREN pin + - 2 # S2MPG11_PCTRLSEL_PWREN_TRG - PWREN_TRG bit in MIMICKING_= CTRL + - 3 # S2MPG11_PCTRLSEL_PWREN_MIF - PWREN_MIF pin + - 4 # S2MPG11_PCTRLSEL_PWREN_MIF_TRG - PWREN_MIF_TRG bit in MI= MICKING_CTRL + - 5 # S2MPG11_PCTRLSEL_AP_ACTIVE_N - ~AP_ACTIVE_N pin + - 6 # S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG - ~AP_ACTIVE_N_TRG bit = in MIMICKING_CTRL + - 7 # S2MPG11_PCTRLSEL_G3D_EN - G3D_EN pin + - 8 # S2MPG11_PCTRLSEL_G3D_EN2 - G3D_EN & ~AP_ACTIVE_N pins + - 9 # S2MPG11_PCTRLSEL_AOC_VDD - AOC_VDD pin + - 10 # S2MPG11_PCTRLSEL_AOC_RET - AOC_RET pin + - 11 # S2MPG11_PCTRLSEL_UFS_EN - UFS_EN pin + - 12 # S2MPG11_PCTRLSEL_LDO13S_EN - VLDO13S_EN pin + + $ref: /schemas/types.yaml#/definitions/uint32 + minimum: 0 + maximum: 12 + + samsung,ext-control-gpios: + description: | + For rails where external control is done via a GPIO, this option= al + property describes the GPIO line used. + + maxItems: 1 + + dependentRequired: + samsung,ext-control-gpios: [ "samsung,ext-control" ] + +properties: + buckboost: + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for the buck-boost regulator. + + properties: + regulator-ramp-delay: false + +patternProperties: + # 12 bucks + "^buck(([1-9]|10)s|[ad])$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single buck regulator. + + properties: + regulator-ramp-delay: + enum: [6250, 12500, 25000] + default: 6250 + + allOf: + - $ref: "#/definitions/s2mpg11-ext-control" + + # 11 standard LDOs + "^ldo([3-79]|1[01245])s$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + properties: + regulator-ramp-delay: false + + # 2 LDOs with possible external control + "^ldo(8|13)s$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for single LDO regulator. + + properties: + regulator-ramp-delay: false + + allOf: + - $ref: "#/definitions/s2mpg11-ext-control" + + # 2 LDOs with ramp support and possible external control + "^ldo[12]s$": + type: object + $ref: regulator.yaml# + unevaluatedProperties: false + description: + Properties for a single LDO regulator. + + properties: + regulator-ramp-delay: + enum: [6250, 12500] + default: 6250 + + allOf: + - $ref: "#/definitions/s2mpg11-ext-control" + +additionalProperties: false + +allOf: + - if: + anyOf: + - required: [buck4s] + - required: [buck6s] + - required: [buck7s] + - required: [buck10s] + - required: [buckboost] + then: + patternProperties: + "^buck([467]|10|boost)s$": + properties: + samsung,ext-control: false + + - if: + required: + - buckboost + then: + properties: + buckboost: + properties: + regulator-ramp-delay: false diff --git a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h b/in= clude/dt-bindings/regulator/samsung,s2mpg10-regulator.h index 1d4e34a756efa46afeb9f018c3e8644ebc373b07..0203946b7215eca615c27482be9= 06c3100b899ee 100644 --- a/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h +++ b/include/dt-bindings/regulator/samsung,s2mpg10-regulator.h @@ -22,6 +22,10 @@ * * ldo20m supports external control, but using a different set of control * signals. + * + * S2MPG11 regulators supporting these are: + * - buck1s .. buck3s buck5s buck8s buck9s bucka buckd + * - ldo1s ldo2s ldo8s ldo13s */ #define S2MPG10_PCTRLSEL_ON 0x0 /* always on */ #define S2MPG10_PCTRLSEL_PWREN 0x1 /* PWREN pin */ @@ -45,4 +49,18 @@ #define S2MPG10_PCTRLSEL_LDO20M_SFR 0x3 /* LDO20M_SFR bit in LDO_CTR= L1 register */ #define S2MPG10_PCTRLSEL_LDO20M_OFF 0x4 /* disable */ =20 +#define S2MPG11_PCTRLSEL_ON 0x0 /* always on */ +#define S2MPG11_PCTRLSEL_PWREN 0x1 /* PWREN pin */ +#define S2MPG11_PCTRLSEL_PWREN_TRG 0x2 /* PWREN_TRG bit in MIMICKIN= G_CTRL */ +#define S2MPG11_PCTRLSEL_PWREN_MIF 0x3 /* PWREN_MIF pin */ +#define S2MPG11_PCTRLSEL_PWREN_MIF_TRG 0x4 /* PWREN_MIF_TRG bit in MIMI= CKING_CTRL */ +#define S2MPG11_PCTRLSEL_AP_ACTIVE_N 0x5 /* ~AP_ACTIVE_N pin */ +#define S2MPG11_PCTRLSEL_AP_ACTIVE_N_TRG 0x6 /* ~AP_ACTIVE_N_TRG bit in M= IMICKING_CTRL */ +#define S2MPG11_PCTRLSEL_G3D_EN 0x7 /* G3D_EN pin */ +#define S2MPG11_PCTRLSEL_G3D_EN2 0x8 /* G3D_EN & ~AP_ACTIVE_N pin= s */ +#define S2MPG11_PCTRLSEL_AOC_VDD 0x9 /* AOC_VDD pin */ +#define S2MPG11_PCTRLSEL_AOC_RET 0xa /* AOC_RET pin */ +#define S2MPG11_PCTRLSEL_UFS_EN 0xb /* UFS_EN pin */ +#define S2MPG11_PCTRLSEL_LDO13S_EN 0xc /* VLDO13S_EN pin */ + #endif /* _DT_BINDINGS_REGULATOR_SAMSUNG_S2MPG10_H */ --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B322C19CC11 for ; Wed, 4 Jun 2025 15:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050757; cv=none; b=XQk+EWOhcxzbbe1zvZtV8JsSQ0NAJkUr0i5BNZD7JgKkWC5ARQUbeAnnbfW3RY/wkfRn+72lE7S0S5Fbwyb4EFoC5p2hYu1OyPGjMQzn2wq42j9un/2ndAIK/MMx2GzoRiWdjGhCnplYaT2a6qbC0+EdV05kpsGzaAsAm2iuxZU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050757; c=relaxed/simple; bh=bSQGBA37BpSgsJdlJNGFk9NhBYGGguunmVcoDXGfnjE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ft7z1at9u3t4Ip8HKCMWkWHdnNUweHa7t0Ck0QZe0agbPXYmgMnIs6arDMN70WLd7jMJq3ks9Bbb8qcv3C9tlrJp35iWJtD8XOxkgbHyQB4g6C5/vu3I/gfToXxiWRwHOsq+rJpw+Z+URylkKztii/Amn0umSOnDoqJAbnH57Bc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=DGFX2T4L; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="DGFX2T4L" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-6049431b0e9so11192113a12.0 for ; Wed, 04 Jun 2025 08:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050752; x=1749655552; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=OVsIds4atv9b1Ndpam+Ic3xTK6Dfgv1Ul4T9xSV77wk=; b=DGFX2T4L2ZSmj6paX1JwvA40YP3nsWpLH0f5OAvJkqhTD7f3GyzGcU7z7Hh6IseysM VXt/UXiZl19ISEP9RJ0IYYzoKAlvf4uU+oERlo7JFVfTe+Vph9NfZDfO+CaNvDlKS5wX PwhmPgbVHnwPjufawdDCHegbm4pkB1HVzwMHG6kHwRKIEOgz+Pr1vZyiP9GpjnPdB4MY QeoidF9MLpVKIfs8xrN0kKLs9IDTisc1LUtVJTX/AG+xflu3AXPsu7+nt4A3flDtaYzI msmOm2gBJ6USXX5BK49hNtNaz3chcW0KDck5j5lPP/7121j349A1xOAECFgyg6046f1g FLPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050752; x=1749655552; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=OVsIds4atv9b1Ndpam+Ic3xTK6Dfgv1Ul4T9xSV77wk=; b=AgD4bBHUL5szGozgYyTMJJaahz3jNcvY8/ZcgiAcUMU2DMESHdOXCwQtohFCrx+v72 9K5oCrS8ZS0lyBqPGlG1j0HPjJKo778QQplczmjjRLI8mUZc+XmZk+Io/svb34un57J+ S+5alt6ggAGiyAIRDgH3Sv3evNrco29OmfJT/SpgvNI9ztIgpxDXTBzKn5cfk2BMzdy0 UYVXtGPIIhuxJ5SJHJ6ImHF6KEyuene4Eq7NQcqy3y+YPuh8yryHcCeR46K28E061TcE dIeqQGCj6Rc/EigTUPEZaprgC5ZfxFSWDHAKd7J6RFq8ilEEde5vYUbTlCDHOjRm+ZSk SXMQ== X-Forwarded-Encrypted: i=1; AJvYcCU6rIEchv3dHtyTliwvhNXDVrOYgcyxrNvsD5NMVCEDFM6EFZ26J1JT39v9ne4P3k5WsWNWli79NADijos=@vger.kernel.org X-Gm-Message-State: AOJu0YwUvgIUi8HqmRyVQvyWlLCYEEW45ZWNrdnrwYhhxYIONpz2+0dX K+Ly4p6BMXrUq7P8jDPUMTZKnLxfI5CTkYRtCvztUwfkyk/NQoONTk6emEGMzrigOig= X-Gm-Gg: ASbGncsq5gWNYqVgKjLUDXTmkCJAm/Ar/ikJq1jX41Ao1Y5NusMih9qY8LzQHH4STdz CLiD6tVUnfPWlFFBpBHtro9cDHzh7K5oL0x5V7uZTnnmNWuLT7ZieIgq9RD5FjPdd855wFUa66O evQfuU8Y5z9fTMFr9CgTytXJ68PQ+rYr6RPygeiqo5myr8OuGpxaiAkI1YMQ5omDOoEDEboOgJc Bl3S5oO89gQtq3DsaiosdZIs/9OMtdRyU3SX5pefMMeFuN1tAqkYrlyr2uxOO1XBXJPbbqQ0L1E tv7JRIf+YbVxtyRCKMPvGyYdIRPbK3qjF3jUxqy1n8fIaB0ZT2e8hgUt9RUp9c5MTdw0E2SEqCo m5uftJNzPJeP/fWxyMAVnQplwRRAnqokjYZU= X-Google-Smtp-Source: AGHT+IGmpFLzdEaYYr7iQUhbbgsCIhZWT7QbCctj4zySD94PvS5LvY7Sr6dL7NlPVuoHoEkdg0F3SA== X-Received: by 2002:a05:6402:34cb:b0:606:a26c:6f50 with SMTP id 4fb4d7f45d1cf-606e944ea6bmr3149657a12.5.1749050746634; Wed, 04 Jun 2025 08:25:46 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:46 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:43 +0100 Subject: [PATCH 04/17] dt-bindings: mfd: samsung,s2mps11: add s2mpg10-pmic regulators Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-4-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Add a regulators node to the s2mpg10-pmic to describe the regulators available on this PMIC. Additionally, describe the supply inputs of the regulator rails, with the supply names matching the datasheet. Note 1: S2MPG10 is typically used as the main-PMIC together with an S2MPG11 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the supplies with an 'm'. Note 2: The binding needs to switch from 'additionalProperties' to 'unevaluatedProperties', to allow adding the specific -supply properties for S2MPG10 only, as otherwise we'd have to resort to a global wildcard with negating inside each of the compatible matches. Signed-off-by: Andr=C3=A9 Draszik --- .../devicetree/bindings/mfd/samsung,s2mps11.yaml | 33 ++++++++++++++++++= +++- 1 file changed, 32 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml b/D= ocumentation/devicetree/bindings/mfd/samsung,s2mps11.yaml index d6b9e29147965b6d8eef786b0fb5b5f198ab69ab..0b834a02368f7867a2d093cbb3a= 9f374bb2acf41 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml @@ -67,7 +67,7 @@ required: - compatible - regulators =20 -additionalProperties: false +unevaluatedProperties: false =20 allOf: - if: @@ -78,9 +78,40 @@ allOf: then: properties: reg: false + + regulators: + $ref: /schemas/regulator/samsung,s2mpg10-regulator.yaml + samsung,s2mps11-acokb-ground: false samsung,s2mps11-wrstbi-ground: false =20 + patternProperties: + "^vinb([1-9]|10)m-supply$": + description: + Phandle to the power supply for each buck rail of this PMIC. T= here + is a 1:1 mapping of supply to rail, e.g. vinb1m-supply supplies + buck1m. + + "^vinl([1-9]|1[0-5])m-supply$": + description: | + Phandle to the power supply for one or multiple LDO rails of t= his + PMIC. The mapping of supply to rail(s) is as follows + vinl1m - ldo13m + vinl2m - ldo15m + vinl3m - ldo1m, ldo5m, ldo7m + vinl4m - ldo3m, ldo8m + vinl5m - ldo16m + vinl6m - ldo17m + vinl7m - ldo6m, ldo11m, ldo24m, ldo28m + vinl8m - ldo12m + vinl9m - ldo2m, ldo4m + vinl10m - ldo9m, ldo14m, ldo18m, 19m, ldo20m, ldo25m + vinl11m - ldo23m, ldo31m + vinl12m - ldo29m + vinl13m - ldo30m + vinl14m - ldo21m + vinl15m - ldo10m, ldo22m, ldo26m, ldo27m + oneOf: - required: [interrupts] - required: [interrupts-extended] --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f45.google.com (mail-ed1-f45.google.com [209.85.208.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9341B19D08F for ; Wed, 4 Jun 2025 15:25:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050751; cv=none; b=jZXAv2qxmL2y6zjjauFL3BvTUEPp3l4WfErgkwu10wEw4ejdJgdmlBYhWkVyoeMpEH4T6hRz31xHPR67kGxE/tDvLMu+umw8Qdg7NySYcKYwI1Sx6opkk4UKiB0vfRV31E1mfX7E6JYgCLKx/fKY7uOstwMc1rbw+Vp1dnYIAfg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050751; c=relaxed/simple; bh=AJLbutT5f80u713gohP/P4oFnY0KLyNPkjsRDaAt050=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=o3OMfeJV7qQbimwSSmGPfrLitGnCpn0/IaRWG/GcQFhK5gAAPWC2q2vrdj1xprBtiMpyEh5pOxUpZdwAhn8sE8EYh7eZhxsPNAbZkAtMV5s9BRBNUSgpw8588pviH4z/rbeBjDnI+EDt6+S3mSNPEamEelD4v/Z2FXNMUVq0Dnc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=oY+sXTUS; arc=none smtp.client-ip=209.85.208.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="oY+sXTUS" Received: by mail-ed1-f45.google.com with SMTP id 4fb4d7f45d1cf-606741e8e7cso5908244a12.1 for ; Wed, 04 Jun 2025 08:25:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050748; x=1749655548; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=KXs2zA73ZRuBPLzY+I20lVoCbiqQa8Pw8YT+g/k8k0Q=; b=oY+sXTUSMmseGBluOqETW0Zj8coxx/IaSM0V/MNyb7xbL4qEi3Xj27Ej05lAZQzA+w IAC2+kGnZ5OeinpsrAIviaAVcVlH4zZN2LtmxHGkGKh7CiuhFShA4Gu57EVkXxSv5vIy FtYmafPI60dYcaQPaloxTEKx1/tmbR22+GyjAA1SotuxSFIrC1EoO6lJF5/wtdoIB/VZ +fpKuBXTUViaYzxBrEAVfVsk4CjIcrdBD3Y4ymmVFB3cpRPTBpwezrKv7P0o6tT+7809 G5u7SWkwsUhekFTz6sGDzNQ52gSoNy+SjW+xvuS0rhIQJ3w+2IYU1a7pmX5QXbOWVvv+ e3gg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050748; x=1749655548; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=KXs2zA73ZRuBPLzY+I20lVoCbiqQa8Pw8YT+g/k8k0Q=; b=Qv+sNo/EpcU1bnGm5KCQuCSsvRhBUCid+51mS0gW7HKNY96lHkXKBFTyKalTcl5aWt Awle43V0ttY2kx3bz5POAGIqZfSB/zSuDjLF02ZuSZnKAwyO2DyZyfiKzrtRBaucT7Gh YqfhKXEzcVC+SeJvV6Av8g2Do5IxOIvTccLReYO1IKaGu09ranhyUkzgl4L4yJNS7VaO qRqaWrv9Wc+TfV7KCq/MOPlwcz4kcD+Fxvl6R1giWMqFZUGj0mGdhypA9jUV11RsPd2N i7Y14gWwTw77uMAJCPl06xRKXXnsRBHeD1C+VZU+6Pu7KQd1/jkTwHaPkplYAQ0oMU8w A7tA== X-Forwarded-Encrypted: i=1; AJvYcCWT1M/hr5zU2q2U+uO8NxYz9AV0Dw1xaCJQYolj0UMN64jcMytjoVaZrtNHMtpTngGIslQAgj5+ppKvhGA=@vger.kernel.org X-Gm-Message-State: AOJu0YyKv3xwutr/gW1tdgRRfDP8sK6ysQGoNKD2Tcup9DrL0g/7meFJ c6ipf1JUqqHi0N2xXTrzz2cxBnqyR9htHFHC5zSxFEziGfzgVUVyweYV/oBqEFPxJkw= X-Gm-Gg: ASbGncsr3ymhoZTY6UCwbqKsfUlFPkRfrATSH6vVpv20wp9+INvU/MvumnVjLabnLfJ qB0vQBWj5STD2353TW6IzG248RM5GIqbv54pv2Vo/zA+hRl1Ir7XuEhXXjDpdZ6YqNDfNtbGlOg Bsc66qKYAVE4G8ZjNmauRTUXTrO7qTCOWY/+PXgLW4DbMFVMZgDWN785MzhCB/1sVhv+5n5mwUU CXZ8IrxyuRfO1elHdObSHH28DCKB5m87yki7jum1kfXU0abx+yaj+IBKMIPHSpxR/rRzFsPdBJ9 UpvlcJSdUwY4hDXDDeBwPogr+TbDY9GwpVNY+B7kdrE0S4m0lYXvJr92mjbPBLLSMCzg03j/zfy lalKHC860jm5af8tRx0wDbV6O+f+gyHcTOsk= X-Google-Smtp-Source: AGHT+IEpnyZ5RcSizQ8OwBQIqB98hY8tFDyFT8RcDjsboJfv/HhXCPW14p5ZpmW4M5LV1bKLv8xaOw== X-Received: by 2002:a05:6402:84d:b0:604:e99e:b78f with SMTP id 4fb4d7f45d1cf-606ea3b00f1mr3402513a12.16.1749050747900; Wed, 04 Jun 2025 08:25:47 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:47 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:44 +0100 Subject: [PATCH 05/17] dt-bindings: mfd: samsung,s2mps11: add s2mpg11-pmic Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-5-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The Samsung S2MPG11 PMIC is similar to the existing S2MPG10 PMIC supported by this binding. It is a Power Management IC for mobile applications with buck converters, various LDOs, and power meters and typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. Like S2MPG10, communication is not via I2C, but via the Samsung ACPM firmware, it therefore doesn't need a 'reg' property but needs to be a child of the ACPM firmware node instead. Add the PMIC, the regulators node, and the supply inputs of the regulator rails, with the supply names matching the datasheet. Note: S2MPG11 is typically used as the sub-PMIC together with an S2MPG10 PMIC in a main/sub configuration, hence the datasheet and the binding both suffix the supplies with an 's'. Signed-off-by: Andr=C3=A9 Draszik --- .../devicetree/bindings/mfd/samsung,s2mps11.yaml | 70 ++++++++++++++++++= ---- 1 file changed, 58 insertions(+), 12 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml b/D= ocumentation/devicetree/bindings/mfd/samsung,s2mps11.yaml index 0b834a02368f7867a2d093cbb3a9f374bb2acf41..f859a7e4a962a6013712ac6c62d= d04eeadc5e0f4 100644 --- a/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml +++ b/Documentation/devicetree/bindings/mfd/samsung,s2mps11.yaml @@ -21,6 +21,7 @@ properties: compatible: enum: - samsung,s2mpg10-pmic + - samsung,s2mpg11-pmic - samsung,s2mps11-pmic - samsung,s2mps13-pmic - samsung,s2mps14-pmic @@ -70,21 +71,46 @@ required: unevaluatedProperties: false =20 allOf: + - if: + not: + properties: + compatible: + const: samsung,s2mpg10-pmic + then: + properties: + system-power-controller: false + - if: properties: compatible: contains: - const: samsung,s2mpg10-pmic + enum: + - samsung,s2mpg10-pmic + - samsung,s2mpg11-pmic then: properties: reg: false + samsung,s2mps11-acokb-ground: false + samsung,s2mps11-wrstbi-ground: false + + oneOf: + - required: [interrupts] + - required: [interrupts-extended] + + else: + required: + - reg =20 + - if: + properties: + compatible: + contains: + const: samsung,s2mpg10-pmic + then: + properties: regulators: $ref: /schemas/regulator/samsung,s2mpg10-regulator.yaml =20 - samsung,s2mps11-acokb-ground: false - samsung,s2mps11-wrstbi-ground: false - patternProperties: "^vinb([1-9]|10)m-supply$": description: @@ -112,16 +138,36 @@ allOf: vinl14m - ldo21m vinl15m - ldo10m, ldo22m, ldo26m, ldo27m =20 - oneOf: - - required: [interrupts] - - required: [interrupts-extended] - - else: + - if: properties: - system-power-controller: false + compatible: + contains: + const: samsung,s2mpg11-pmic + then: + properties: + regulators: + $ref: /schemas/regulator/samsung,s2mpg11-regulator.yaml =20 - required: - - reg + patternProperties: + "^vinb(([1-9]|10)s|[abd])-supply$": + description: + Phandle to the power supply for each buck rail of this PMIC. T= here + is a 1:1 mapping of numbered supply to rail, e.g. vinb1s-supply + supplies buck1s. The remaining mapping is as follows + vinba - bucka + vinbb - buck boost + vinbd - buckd + + "^vinl[1-6]s-supply$": + description: | + Phandle to the power supply for one or multiple LDO rails of t= his + PMIC. The mapping of supply to rail(s) is as follows + vinl1s - ldo1s, ldo2s + vinl2s - ldo8s, ldo9s + vinl3s - ldo3s, ldo5s, ldo7s, ldo15s + vinl4s - ldo10s, ldo11s, ldo12s, ldo14s + vinl5s - ldo4s, ldo6s + vinl6s - ldo13s =20 - if: properties: --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 42AA91A0711 for ; Wed, 4 Jun 2025 15:25:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050753; cv=none; b=JBJZnhXUX/7gm/WoxgteBJ2wLWel4DV2EBkGdurcjU2+CJgnnqBNIJEKbmJxHInehs/EsqUPgNO0dIr6KsTLlz75XadNew38k1PqfVHoGrDcJlg/S5x9ZqJ0unebTs1CLeGOVRC67d7jXGV0C9OWitIEAIWitr7worrtUTwJ4nc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050753; c=relaxed/simple; bh=j0GuHj7/ZWHalZNJJKYALf4n+0SGhUawk93aep6mVzU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=XXH4N/IfSaChsgQxrI2ZNFNdLNfNpB0hWd5FT1M4TPFVTfYL96iRq1aXo5t63Esnh2zagiwNfCbuxPocsoHlmEimU/IrqQ9X8RDp3VrUJ5fTqAe+zO129F1czAvztlTeXnLHU48WKfKg4GT7mSy+jUUZ5I9k2uFM/vsbNd/jTG0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=TOxSmiuu; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="TOxSmiuu" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-60461fc88d7so14038256a12.0 for ; Wed, 04 Jun 2025 08:25:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050748; x=1749655548; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0u44+fUCPUbXjNG3Yeye3uYWIaUqk694d8ypWgEWxmc=; b=TOxSmiuuOIVEo/F08dulkHvZzIp0ij1IJ0DnYwF7gj1HIoaTBeVKZ/FnmNKC7HDoTs OB1QQTuA8lHSpE+ARFwqX/mGp7NeoRjpzM+96CY+n5CSZsRdTHGihy6XxLWrRaCCfz1e TsbVg9iDGHvfn8NhfyfxYNG/RH4oQa0vneZEqhP2EMRoAxBVIi/+uecvq951VvbUM6iL fpNC7D/d+RfghTH9MJ9ZmEywlS9YNDJsPgzkE6/u2HJLOUEuWA41t2hRrBamcTO7kCeH mhSxTsmKnchlDVD0eE9H2RWyeXR7bv0et5X7QvNwP0Q8IkzlCk8ymanrSGUw/p/gwr1M ZxoA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050748; x=1749655548; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0u44+fUCPUbXjNG3Yeye3uYWIaUqk694d8ypWgEWxmc=; b=cJTHsoegDM5gJi4SLqXlkJmqoktbPeOeeTYXEVoq598rI2cqBZpXg/aKr8lANvwPwb vpmCU/mb8fdkCAnk/nhXd7Xy8G3fcdb2pWz1exHDVVePyq2WC1gh/uHtp7S21hV7XEYP c5QLueNgfayDhRzlPMCWaKlIpmx0gs/UpT12kaKZ4rri8JyJDmSweeSK3fC/crBY0AXC YelMeldR2n4dwC5ifH8BoDcKuIV8Jv/mvn+Jdu2e+p05/HJcar3a7D6VS2Bmq+U/NOdP xS8i7bZjH/izGvrwr677vTKXZmErifzh3KtcZvhZBzcRNABjNh4H6J1FSByMegUwJlLz Gnpg== X-Forwarded-Encrypted: i=1; AJvYcCU4n+0+AQZKMmI7VgNRAJUJe78IOFm5mNxDM7GeQyLsbgSWZDYNwGoIFynlsyaE8UsoF9wWl2jHC5hV0OM=@vger.kernel.org X-Gm-Message-State: AOJu0YwnFI6VIYU3j9p8mJEaWAD6YuvpfP4BSbrFgLk7jIkFV1fs4ukQ 1A/bCDrSsA22xNg27zR+/VUqJqCaigC3B50hXA4hz6pKlm2IzfXBmFauzTXi9sSiW0M= X-Gm-Gg: ASbGncuPOMA+FxtXZBU/6P2sCoDVdAuXL8aIu2Ksh9DwRZskFlDzIZWZKS69uaTLLxx /txcl3BkUsBVyX16VJcJqJh/G473aiwSorwuPhY5uMJiBermrS3NbVtdh2PaamYNfO3bIMufNgF zlozuVuCIr1YNAtXFDteItoqW9K+KyalE7+JJOlGrAaNsFUydmLveLrf0VYMKk+pw/bOqy4mi/Z mxVm8yodgh2/O9TJezE6Of4b0+qLeloZVkns3VYnLNum9MFWnPquEjdjdQ7dgipAhkBcqF4ZNlC ucRTrqJdviOwUAMweGBRCyLz6Ew4Kwc1l/ihodbqb6KrMViJFxm1blDPAa4dIW+4RZcQS95y3y2 oCPPE6LB9uZq4xa9Iu07Lsj82c2Pi4pVfM5Y= X-Google-Smtp-Source: AGHT+IHNAC7ImHn1/O1ztYLzbmZYe73jvmUwIhXjFO7kKauTSDKLz6MSUnHCtZ7LDe45RKA4CdqcaA== X-Received: by 2002:a05:6402:26cd:b0:606:b6ba:3595 with SMTP id 4fb4d7f45d1cf-606f0fd23d5mr2931176a12.32.1749050748489; Wed, 04 Jun 2025 08:25:48 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:48 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:45 +0100 Subject: [PATCH 06/17] dt-bindings: firmware: google,gs101-acpm-ipc: update PMIC examples Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-6-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 In a typical system using the Samsung S2MPG10 PMIC, an S2MPG11 is used as a sub-PMIC. The interface for both is the ACPM firmware protocol, so update the example here to describe the connection for both. Signed-off-by: Andr=C3=A9 Draszik --- .../bindings/firmware/google,gs101-acpm-ipc.yaml | 40 ++++++++++++++++++= ++-- 1 file changed, 37 insertions(+), 3 deletions(-) diff --git a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-i= pc.yaml b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.= yaml index 62a3a7dac5bd250a7f216c72f3315cd9632d93e1..408cf84e426b80b6c06e69fda87= d0f8bfc61498d 100644 --- a/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml +++ b/Documentation/devicetree/bindings/firmware/google,gs101-acpm-ipc.yaml @@ -36,6 +36,15 @@ properties: compatible: const: samsung,s2mpg10-pmic =20 + pmic2: + description: Child node describing the sub PMIC. + type: object + additionalProperties: true + + properties: + compatible: + const: samsung,s2mpg11-pmic + shmem: description: List of phandle pointing to the shared memory (SHM) area. The memory @@ -52,7 +61,9 @@ additionalProperties: false =20 examples: - | + #include #include + #include =20 power-management { compatible =3D "google,gs101-acpm-ipc"; @@ -63,12 +74,20 @@ examples: compatible =3D "samsung,s2mpg10-pmic"; interrupts-extended =3D <&gpa0 6 IRQ_TYPE_LEVEL_LOW>; =20 + vinl3m-supply =3D <&buck8m>; + regulators { ldo1m { regulator-name =3D "vdd_ldo1"; regulator-min-microvolt =3D <700000>; regulator-max-microvolt =3D <1300000>; - regulator-always-on; + }; + + ldo20m { + regulator-name =3D "vdd_ldo1"; + regulator-min-microvolt =3D <700000>; + regulator-max-microvolt =3D <1300000>; + samsung,ext-control =3D ; }; =20 // ... @@ -77,8 +96,23 @@ examples: regulator-name =3D "vdd_mif"; regulator-min-microvolt =3D <450000>; regulator-max-microvolt =3D <1300000>; - regulator-always-on; - regulator-boot-on; + regulator-ramp-delay =3D <6250>; + }; + }; + }; + + pmic2 { + compatible =3D "samsung,s2mpg11-pmic"; + interrupts-extended =3D <&gpa0 7 IRQ_TYPE_LEVEL_LOW>; + + vinl1s-supply =3D <&buck8m>; + vinl2s-supply =3D <&buck6s>; + + regulators { + buckd { + regulator-ramp-delay =3D <6250>; + samsung,ext-control =3D ; + samsung,ext-control-gpios =3D <&gpp0 1 GPIO_ACTIVE_HIG= H>; }; }; }; --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 70D1F1A2C25 for ; Wed, 4 Jun 2025 15:25:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050752; cv=none; b=cwCWcOo4tGItkiv75ThCoRJ3bdppm/iNRNEbdUAw1QITfYfgACKHjrpmL++YvV5NCP8FlXLHkOLrvJX13pBx3dsK+gdrntN5U9XImU9RXmwFlb6voR9hd+q6TcMwJzUJPhvs7+UKcK45e4GJC0idGN1O+XiIzg/PewcXioLxTHw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050752; c=relaxed/simple; bh=Gj+OkGgY96XAKccd1qEAmfoB1fWuf6GgMzaQtMdSNXA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=oP6IjAbHL+5b951Ai5hnIS18PBlLeQQld5GvZo2zHju2BxwKnjz5CclSqgybi058S2I3XdisQby/kMoqP36rJpUpa3V1cfxq+6tFJv9JwVTL68O8aiZ4LE5dbcE0I4etm1FMJSnILubBeN4O8Kw5P7FKuKmFMMRhwOc+jroDO+k= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Rs12x5s5; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Rs12x5s5" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-60462000956so12098264a12.0 for ; Wed, 04 Jun 2025 08:25:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050749; x=1749655549; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=GivaCqfw+oHHkwskzA0HrsGk/OrrGEk7Uk/oqYQ1tlk=; b=Rs12x5s5l6bap5cohSEG0hwzOkM2u4ZFJIn1/fqrDhrh2yJhCN78E9YRt9Gqhyjfup WaijkXC040eioUZrbQigqq6c03xz0vtgISmGXcmiS65ZVIxjnny3HN45CE3049u9tOJC p3A60+hCOVoV7SUOnhJwsyYdYaIGco5oHqs3tqtJ563s5h0o+I5kAboV9Yz3okA9q1MB fx9i3T0SQqd33L8P1qcWcxmqOvg4xV5R5v4o6fYRBE/WItVrIy0DX945bHlP3Gab0JhP qobqEY3e5ND2S4wTUtJ8E0FFZVKnNpcepTbGcDkgIz1qcsRQKT+oINW6GlDhHOrdIZhT jnjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050749; x=1749655549; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=GivaCqfw+oHHkwskzA0HrsGk/OrrGEk7Uk/oqYQ1tlk=; b=wLUM5uJaThkcQJsKkIVpIx00Yh2iMeBZTgaq8eerUBUJQQIGVUR99sYFMxCaa7uBel GtkRxYgsXAOjVvlDOHfVSGngxxRJZfwSxc3B6KH/nWD3QseAU9PRJrV0WLZYBtoNs3wM 0YSOu+A06C02q1rrI/gFYPGJG+b1gkkI8nMxObmlRwlF0xal0dYV4sBX2jJ942tNMiyM rQfNGgFeFBASIayk9fvW92fBd67/q0ICesVtBsTftwz0Ij5x/6MtKtH2s2snry1Ho/Oz H9r0eCpumjQkOihhSmX6dLxvvGjgEB7enWqoOSlVtKhtvavxoCBz9CeFdzt7uqzTcfPQ YmgQ== X-Forwarded-Encrypted: i=1; AJvYcCUz/V9ntTWFZGb8TRBldVXuXFo21qzqz8vMhO8hp15d8G8UjSeP2eIndXhTUpZnyDiJvrP4FyS1JARr930=@vger.kernel.org X-Gm-Message-State: AOJu0YzSwuA9adsebJeDuiRSxZLKCIYwZTbMi37yadyiLHeBhynSrUTl CRPXQ5AcfdUXNss0jBKMU+WyMbKB5KoYk5bKncalMZR0OxA3Z/ErLZmGosu+PZ7TOaE= X-Gm-Gg: ASbGncuMLre97qELgUGy5dwRoz2odgQUO8c2BWgmLVuhly4g45NiEUzLvNqH4okS3/o WU0kHnJ+G6fBAPUzVg5uUifG3Kq1g4FDInumeFqyBu0rUViKCD9XbOGOw6ws7ddJt3VYRkYgKsC hd3PnS6swbib6BxjgIPWjZbbyKmX3PYRm3n5P7TeyrKwPo9uqt2HgSkXbOkL7hdMuGTGVKM6c9a v1WJ9dozaAbe2to4lb+vGq+VRE/6QvEJGi2fEJDHdrFVDOOVAMTpP4EhsQ7x+Ytk7WXrfLGVTCM Q6/iYzenT5hPfsmDrI4HkA0edt/MdyG/dCfEG1LY2O/+mKnwjPB8E3ugEQ+G6QPSZganKaCjwHo 0RKlwfY9IwR9zfTsI3UIFc3lIxSNhKzxFhD0= X-Google-Smtp-Source: AGHT+IGV8hMofF63zCcJFZH5e/p1yvyUoeRTRE3SZ/3LkqyGQ9VGgvqlN/UR+F68PovdxN0Atb8y8w== X-Received: by 2002:a05:6402:1ecf:b0:606:4d43:e647 with SMTP id 4fb4d7f45d1cf-606ea16e715mr3425583a12.24.1749050748992; Wed, 04 Jun 2025 08:25:48 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:48 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:46 +0100 Subject: [PATCH 07/17] mfd: sec-common: Instantiate s2mpg10 bucks and ldos separately Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-7-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Bucks can conceivably be used as supplies for LDOs, which means we need to instantiate them separately from each other so that the supply- consumer links can be resolved successfully at probe time. By doing so, the kernel will defer and retry instantiating the LDOs once BUCKs have been created while without this change, it can be impossible to mark BUCKs as LDO supplies. This becomes particularly an issue with the upcoming support for the S2MPG11 PMIC, where typically certain S2MP10/11 buck rails supply certain S2MP11/10 LDO rails. The platform_device's ::id field is used to inform the regulator driver which type of regulators (buck or ldo) to instantiate. Signed-off-by: Andr=C3=A9 Draszik --- drivers/mfd/sec-common.c | 4 +++- include/linux/mfd/samsung/s2mpg10.h | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index 42d55e70e34c8d7cd68cddaecc88017e259365b4..8a1694c6ed8708397a51ebd4a49= c22387d7e3495 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -14,6 +14,7 @@ #include #include #include +#include #include #include #include @@ -35,7 +36,8 @@ static const struct mfd_cell s2dos05_devs[] =3D { =20 static const struct mfd_cell s2mpg10_devs[] =3D { MFD_CELL_NAME("s2mpg10-meter"), - MFD_CELL_NAME("s2mpg10-regulator"), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_REGULATOR_CELL= _ID_BUCKS), + MFD_CELL_BASIC("s2mpg10-regulator", NULL, NULL, 0, S2MPG10_REGULATOR_CELL= _ID_LDOS), MFD_CELL_NAME("s2mpg10-rtc"), MFD_CELL_OF("s2mpg10-clk", NULL, NULL, 0, 0, "samsung,s2mpg10-clk"), MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"), diff --git a/include/linux/mfd/samsung/s2mpg10.h b/include/linux/mfd/samsun= g/s2mpg10.h index 9f5919b89a3c286bf1cd6b3ef0e74bc993bff01a..3e8bc65078472518c5e77f8bd19= 9ee403eda18ea 100644 --- a/include/linux/mfd/samsung/s2mpg10.h +++ b/include/linux/mfd/samsung/s2mpg10.h @@ -8,6 +8,11 @@ #ifndef __LINUX_MFD_S2MPG10_H #define __LINUX_MFD_S2MPG10_H =20 +enum s2mpg10_regulator_mfd_cell_id { + S2MPG10_REGULATOR_CELL_ID_BUCKS =3D 1, + S2MPG10_REGULATOR_CELL_ID_LDOS =3D 2, +}; + /* Common registers (type 0x000) */ enum s2mpg10_common_reg { S2MPG10_COMMON_CHIPID, --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0718418B47E for ; Wed, 4 Jun 2025 15:25:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.218.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050757; cv=none; b=moudFhl1H9L6tCCVn3dgotcK/MAQqu0kt/vNpSffTiXijm6OugR12uZj82hJiCjl6/1aCYfJyEIL2w2tgaQ9d2Gvkv9SakcUnCFq8ia9VC9MiMr7oOHyj7Dx26UAHmsQnk/tDZbtGrs9c1rkiu07AU//LVeTeCI4pjzEaMTp6bQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050757; c=relaxed/simple; bh=hEZQpjBK7E4S4fNhXRiHmozkj65EBLBzpWmQesVJVXY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=p/j4NnAo8o3/7g/Xt4WdIXvFm1GiIOcTS1KxeAHv1/YSrQiaJ1pMsEPyjUnBEIWr8pDbY8vGXmBxZx5CiCAhBnQC8eDnuUn2m4rgTc+ny28SGsMTlTx4fDKelP7EfAYJtaHrksSpvISScc7swodhN2dvY2usk5COCzYcyC/FrOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SJpuLOao; arc=none smtp.client-ip=209.85.218.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SJpuLOao" Received: by mail-ej1-f41.google.com with SMTP id a640c23a62f3a-acb5ec407b1so1092368666b.1 for ; Wed, 04 Jun 2025 08:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050751; x=1749655551; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=WSCk1RCEvOr7TDmN41Gm/t/3PTvQDV7fG4m/TbYxnM4=; b=SJpuLOaon3Cr+cl4zOdlPJQlrzncJdgmiY6i2JuXEQN45dGElW5R/wJRYwePhbAUjE plsmev73G8jNqnF1jaoD14uXQYHXwnNlAya7SCZc+4gxNmjwb3N232kVbPDmVYn3khex eAT/WOVn+QuQpItDiMhoRraMC3OcHbBHbErX7qxNHkvdd1EAZmySk4NFBBks6qieSZeD gNLQAVxZg3cXModP4f1kM2h1vpQ9YF7ih5VPK9RAHW7L+GmmvSaserZjc0dbhO5tTs7y xoE8UXq9MeQWMCmaWunwtOwy+5sqxOSxwyLPX8whHD7cN1tlEUroqhh15z+BAOh3tnNV yqrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050751; x=1749655551; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=WSCk1RCEvOr7TDmN41Gm/t/3PTvQDV7fG4m/TbYxnM4=; b=oeDASmRouisbEoFLcvsu0g+HLTsQDu0yA2ILTXrFxyqLqsS4XWdQwMpZjQdyWCHRCm rmsZ9PVOA/zZCcFcxpqKshf7pk5+imBPSg+2IeSDaBHQgOmF6pNAB0G3tipBi3MrTDdX V8dV3sVo7uQFFbPP4TFWx6qup5etwAp41MqzA8rjrmsMpS+R1a/CpYaZUECAWVkHyCsl pkqblL8Kb70BT7tjMI3uF/oAvzweCUnuh2AXBHJ0DcSxSU7U8e8f3N9uPv2CryA/1fcO uYQeh7gGfpmz0bovNSUAD8AL7ERhTu1RtXgF/+9p6Epk0O/q15Smq2xibNCn9gN32fci djfQ== X-Forwarded-Encrypted: i=1; AJvYcCVPBnLLvgnL8o+eMWOdwEg9FP3vS0erGrq9BsfeKPjQ7jBpkhHyQ5c45xKElDwqguL+ViVmWbeLijZ/Kp0=@vger.kernel.org X-Gm-Message-State: AOJu0YyjIWTVtXzmPqxhLO2y8gdzOrJPZcoCirMpktCyeUPvHwCJkqVl 774j9AOp797jvfHj5fTaGN8jp8WCeCtC2zkq7Gjik1S0j66OZdIvEOZvYZJF2ikYLuk= X-Gm-Gg: ASbGncul3RsP5663K5IwbYK/aaq8P5pr4Id7RhkD5/1RIxoVTJckNjxZC+o9pgsYGXg 8VIYNOyo5w5wqKGY2u1u+8R8Mjzk9f1msYVBsfzCZDk4U0h09q44utVv5BGVSL82ilufCJuMHXY oyeg1NFwWmtpmtTsf07odgnoDgRUO5pAr1vUSHiMtXK353s0qvGki9i10frsDfzL6fEM8J9ojv5 S/suZScgdqcr0u0kPy5lQAIjs3Sb0ReZ58dbBOXn+E2tMHto4XaskWB3MzbAxbgcMX91R7Jy5e1 g1CoYmjy++kpnznMfC0WvC3EIKpbHCFJNLuKrhVfhenFgIAiv43rQfuWLt/h2P8VaBlgv3tJaU3 vAb9idjaxiry4rnTBzWtPt/tCqCW0AluBQpA= X-Google-Smtp-Source: AGHT+IHxs49fPL3OhZlxz0pual1n3oAnI4X+vf8MtzzY07OyKvdLSmHWEZvMEza0KI0jlSsYkWJ2/g== X-Received: by 2002:a17:907:9713:b0:add:ed3a:e792 with SMTP id a640c23a62f3a-addf8fb3ademr280186766b.47.1749050749542; Wed, 04 Jun 2025 08:25:49 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:49 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:47 +0100 Subject: [PATCH 08/17] mfd: sec: Add support for S2MPG11 PMIC via ACPM Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-8-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Add support for Samsung's S2MPG11 PMIC, which is a Power Management IC for mobile applications with buck converters, various LDOs, and power meters. It typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. Like S2MPG10, communication is not via I2C, but via the Samsung ACPM firmware. Note: The firmware uses the ACPM channel ID and the Speedy channel ID to select the PMIC address. Since these are firmware properties, they can not be retrieved from DT, but instead are deducted from the compatible for now. Signed-off-by: Andr=C3=A9 Draszik --- Note: checkpatch suggests to update MAINTAINERS, but the new file is covered already due to using a wildcard. --- drivers/mfd/sec-acpm.c | 213 +++++++++++++++++- drivers/mfd/sec-common.c | 18 +- drivers/mfd/sec-irq.c | 67 +++++- include/linux/mfd/samsung/core.h | 1 + include/linux/mfd/samsung/irq.h | 99 +++++++++ include/linux/mfd/samsung/s2mpg11.h | 420 ++++++++++++++++++++++++++++++++= ++++ 6 files changed, 807 insertions(+), 11 deletions(-) diff --git a/drivers/mfd/sec-acpm.c b/drivers/mfd/sec-acpm.c index 8b31c816d65b86c54a108fa994384abfac0e7da4..b44af6f8b1cdfcb75cf9d4c55c9= d973a88fd510c 100644 --- a/drivers/mfd/sec-acpm.c +++ b/drivers/mfd/sec-acpm.c @@ -13,6 +13,7 @@ #include #include #include +#include #include #include #include @@ -216,6 +217,155 @@ static const struct regmap_config s2mpg10_regmap_conf= ig_meter =3D { .cache_type =3D REGCACHE_FLAT, }; =20 +static const struct regmap_range s2mpg11_common_registers[] =3D { + regmap_reg_range(0x00, 0x02), /* CHIP_ID_S, INT, INT_MASK */ + regmap_reg_range(0x0a, 0x0c), /* Speedy control */ + regmap_reg_range(0x1a, 0x27), /* Debug */ +}; + +static const struct regmap_range s2mpg11_common_ro_registers[] =3D { + regmap_reg_range(0x00, 0x01), /* CHIP_ID_S, INT */ + regmap_reg_range(0x25, 0x27), /* Debug */ +}; + +static const struct regmap_range s2mpg11_common_nonvolatile_registers[] = =3D { + regmap_reg_range(0x00, 0x00), /* CHIP_ID_S */ + regmap_reg_range(0x02, 0x02), /* INT_MASK */ + regmap_reg_range(0x0a, 0x0c), /* Speedy control */ +}; + +static const struct regmap_range s2mpg11_common_precious_registers[] =3D { + regmap_reg_range(0x01, 0x01), /* INT */ +}; + +static const struct regmap_access_table s2mpg11_common_wr_table =3D { + .yes_ranges =3D s2mpg11_common_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_common_registers), + .no_ranges =3D s2mpg11_common_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_common_ro_registers), +}; + +static const struct regmap_access_table s2mpg11_common_rd_table =3D { + .yes_ranges =3D s2mpg11_common_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_common_registers), +}; + +static const struct regmap_access_table s2mpg11_common_volatile_table =3D { + .no_ranges =3D s2mpg11_common_nonvolatile_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_common_nonvolatile_registers), +}; + +static const struct regmap_access_table s2mpg11_common_precious_table =3D { + .yes_ranges =3D s2mpg11_common_precious_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_common_precious_registers), +}; + +static const struct regmap_config s2mpg11_regmap_config_common =3D { + .name =3D "common", + .reg_bits =3D ACPM_ADDR_BITS, + .val_bits =3D 8, + .max_register =3D S2MPG11_COMMON_SPD_DEBUG4, + .wr_table =3D &s2mpg11_common_wr_table, + .rd_table =3D &s2mpg11_common_rd_table, + .volatile_table =3D &s2mpg11_common_volatile_table, + .precious_table =3D &s2mpg11_common_precious_table, + .num_reg_defaults_raw =3D S2MPG11_COMMON_SPD_DEBUG4 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct regmap_range s2mpg11_pmic_registers[] =3D { + regmap_reg_range(0x00, 0x5a), /* All PMIC registers */ + regmap_reg_range(0x5c, 0xb7), /* All PMIC registers */ +}; + +static const struct regmap_range s2mpg11_pmic_ro_registers[] =3D { + regmap_reg_range(0x00, 0x05), /* INTx */ + regmap_reg_range(0x0c, 0x0d), /* STATUS OFFSRC */ + regmap_reg_range(0x98, 0x98), /* GPIO input */ +}; + +static const struct regmap_range s2mpg11_pmic_nonvolatile_registers[] =3D { + regmap_reg_range(0x06, 0x0b), /* INTxM */ +}; + +static const struct regmap_range s2mpg11_pmic_precious_registers[] =3D { + regmap_reg_range(0x00, 0x05), /* INTx */ +}; + +static const struct regmap_access_table s2mpg11_pmic_wr_table =3D { + .yes_ranges =3D s2mpg11_pmic_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_pmic_registers), + .no_ranges =3D s2mpg11_pmic_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_pmic_ro_registers), +}; + +static const struct regmap_access_table s2mpg11_pmic_rd_table =3D { + .yes_ranges =3D s2mpg11_pmic_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_pmic_registers), +}; + +static const struct regmap_access_table s2mpg11_pmic_volatile_table =3D { + .no_ranges =3D s2mpg11_pmic_nonvolatile_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_pmic_nonvolatile_registers), +}; + +static const struct regmap_access_table s2mpg11_pmic_precious_table =3D { + .yes_ranges =3D s2mpg11_pmic_precious_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_pmic_precious_registers), +}; + +static const struct regmap_config s2mpg11_regmap_config_pmic =3D { + .name =3D "pmic", + .reg_bits =3D ACPM_ADDR_BITS, + .val_bits =3D 8, + .max_register =3D S2MPG11_PMIC_LDO_SENSE2, + .wr_table =3D &s2mpg11_pmic_wr_table, + .rd_table =3D &s2mpg11_pmic_rd_table, + .volatile_table =3D &s2mpg11_pmic_volatile_table, + .precious_table =3D &s2mpg11_pmic_precious_table, + .num_reg_defaults_raw =3D S2MPG11_PMIC_LDO_SENSE2 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + +static const struct regmap_range s2mpg11_meter_registers[] =3D { + regmap_reg_range(0x00, 0x3e), /* Meter config */ + regmap_reg_range(0x40, 0x8a), /* Meter data */ + regmap_reg_range(0x8d, 0x9c), /* Meter data */ +}; + +static const struct regmap_range s2mpg11_meter_ro_registers[] =3D { + regmap_reg_range(0x40, 0x9c), /* Meter data */ +}; + +static const struct regmap_access_table s2mpg11_meter_wr_table =3D { + .yes_ranges =3D s2mpg11_meter_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_meter_registers), + .no_ranges =3D s2mpg11_meter_ro_registers, + .n_no_ranges =3D ARRAY_SIZE(s2mpg11_meter_ro_registers), +}; + +static const struct regmap_access_table s2mpg11_meter_rd_table =3D { + .yes_ranges =3D s2mpg11_meter_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_meter_registers), +}; + +static const struct regmap_access_table s2mpg11_meter_volatile_table =3D { + .yes_ranges =3D s2mpg11_meter_ro_registers, + .n_yes_ranges =3D ARRAY_SIZE(s2mpg11_meter_ro_registers), +}; + +static const struct regmap_config s2mpg11_regmap_config_meter =3D { + .name =3D "meter", + .reg_bits =3D ACPM_ADDR_BITS, + .val_bits =3D 8, + .max_register =3D S2MPG11_METER_LPF_DATA_NTC7_2, + .wr_table =3D &s2mpg11_meter_wr_table, + .rd_table =3D &s2mpg11_meter_rd_table, + .volatile_table =3D &s2mpg11_meter_volatile_table, + .num_reg_defaults_raw =3D S2MPG11_METER_LPF_DATA_NTC7_2 + 1, + .cache_type =3D REGCACHE_FLAT, +}; + struct sec_pmic_acpm_shared_bus_context { const struct acpm_handle *acpm; unsigned int acpm_chan_id; @@ -325,16 +475,22 @@ static struct regmap *sec_pmic_acpm_regmap_init(struc= t device *dev, return regmap; } =20 -static void sec_pmic_acpm_mask_common_irqs(void *regmap_common) +static void sec_pmic_acpm_mask_common_s2mpg10_irqs(void *regmap_common) { regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COMMON_INT_S= RC); } =20 +static void sec_pmic_acpm_mask_common_s2mpg11_irqs(void *regmap_common) +{ + regmap_write(regmap_common, S2MPG11_COMMON_INT_MASK, S2MPG11_COMMON_INT_S= RC); +} + static int sec_pmic_acpm_probe(struct platform_device *pdev) { struct regmap *regmap_common, *regmap_pmic, *regmap; const struct sec_pmic_acpm_platform_data *pdata; struct sec_pmic_acpm_shared_bus_context *shared_ctx; + void (*masq_irqs_handler)(void *data); const struct acpm_handle *acpm; struct device *dev =3D &pdev->dev; int ret, irq; @@ -365,7 +521,19 @@ static int sec_pmic_acpm_probe(struct platform_device = *pdev) return PTR_ERR(regmap_common); =20 /* Mask all interrupts from 'common' block, until successful init */ - ret =3D regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COMM= ON_INT_SRC); + switch (pdata->device_type) { + case S2MPG10: + ret =3D regmap_write(regmap_common, S2MPG10_COMMON_INT_MASK, S2MPG10_COM= MON_INT_SRC); + break; + + case S2MPG11: + ret =3D regmap_write(regmap_common, S2MPG11_COMMON_INT_MASK, S2MPG11_COM= MON_INT_SRC); + break; + + default: + return dev_err_probe(dev, -EINVAL, "Unsupported device type %d\n", + pdata->device_type); + } if (ret) return dev_err_probe(dev, ret, "failed to mask common block interrupts\n= "); =20 @@ -374,10 +542,12 @@ static int sec_pmic_acpm_probe(struct platform_device= *pdev) if (IS_ERR(regmap_pmic)) return PTR_ERR(regmap_pmic); =20 - regmap =3D sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCES= STYPE_RTC, - pdata->regmap_cfg_rtc, true); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); + if (pdata->regmap_cfg_rtc) { + regmap =3D sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCE= SSTYPE_RTC, + pdata->regmap_cfg_rtc, true); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + } =20 regmap =3D sec_pmic_acpm_regmap_init(dev, shared_ctx, SEC_PMIC_ACPM_ACCES= STYPE_METER, pdata->regmap_cfg_meter, true); @@ -392,13 +562,28 @@ static int sec_pmic_acpm_probe(struct platform_device= *pdev) devm_device_init_wakeup(dev); =20 /* Unmask PMIC interrupt from 'common' block, now that everything is in p= lace. */ - ret =3D regmap_clear_bits(regmap_common, S2MPG10_COMMON_INT_MASK, - S2MPG10_COMMON_INT_SRC_PMIC); + switch (pdata->device_type) { + case S2MPG10: + ret =3D regmap_clear_bits(regmap_common, S2MPG10_COMMON_INT_MASK, + S2MPG10_COMMON_INT_SRC_PMIC); + masq_irqs_handler =3D sec_pmic_acpm_mask_common_s2mpg10_irqs; + break; + + case S2MPG11: + ret =3D regmap_clear_bits(regmap_common, S2MPG11_COMMON_INT_MASK, + S2MPG11_COMMON_INT_SRC_PMIC); + masq_irqs_handler =3D sec_pmic_acpm_mask_common_s2mpg11_irqs; + break; + + default: + return dev_err_probe(dev, -EINVAL, "Unsupported device type %d\n", + pdata->device_type); + } if (ret) return dev_err_probe(dev, ret, "failed to unmask PMIC interrupt\n"); =20 /* Mask all interrupts from 'common' block on shutdown */ - ret =3D devm_add_action_or_reset(dev, sec_pmic_acpm_mask_common_irqs, reg= map_common); + ret =3D devm_add_action_or_reset(dev, masq_irqs_handler, regmap_common); if (ret) return ret; =20 @@ -420,8 +605,18 @@ static const struct sec_pmic_acpm_platform_data s2mpg1= 0_data =3D { .regmap_cfg_meter =3D &s2mpg10_regmap_config_meter, }; =20 +static const struct sec_pmic_acpm_platform_data s2mpg11_data =3D { + .device_type =3D S2MPG11, + .acpm_chan_id =3D 2, + .speedy_channel =3D 1, + .regmap_cfg_common =3D &s2mpg11_regmap_config_common, + .regmap_cfg_pmic =3D &s2mpg11_regmap_config_pmic, + .regmap_cfg_meter =3D &s2mpg11_regmap_config_meter, +}; + static const struct of_device_id sec_pmic_acpm_of_match[] =3D { { .compatible =3D "samsung,s2mpg10-pmic", .data =3D &s2mpg10_data, }, + { .compatible =3D "samsung,s2mpg11-pmic", .data =3D &s2mpg11_data, }, { }, }; MODULE_DEVICE_TABLE(of, sec_pmic_acpm_of_match); diff --git a/drivers/mfd/sec-common.c b/drivers/mfd/sec-common.c index 8a1694c6ed8708397a51ebd4a49c22387d7e3495..497dcbb907c4e94db3be43c498f= 70996d72f13f6 100644 --- a/drivers/mfd/sec-common.c +++ b/drivers/mfd/sec-common.c @@ -43,6 +43,13 @@ static const struct mfd_cell s2mpg10_devs[] =3D { MFD_CELL_OF("s2mpg10-gpio", NULL, NULL, 0, 0, "samsung,s2mpg10-gpio"), }; =20 +static const struct mfd_cell s2mpg11_devs[] =3D { + MFD_CELL_NAME("s2mpg11-meter"), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG10_REGULATOR_CELL= _ID_BUCKS), + MFD_CELL_BASIC("s2mpg11-regulator", NULL, NULL, 0, S2MPG10_REGULATOR_CELL= _ID_LDOS), + MFD_CELL_OF("s2mpg11-gpio", NULL, NULL, 0, 0, "samsung,s2mpg11-gpio"), +}; + static const struct mfd_cell s2mps11_devs[] =3D { MFD_CELL_NAME("s2mps11-regulator"), MFD_CELL_NAME("s2mps14-rtc"), @@ -86,8 +93,13 @@ static void sec_pmic_dump_rev(struct sec_pmic_dev *sec_p= mic) unsigned int val; =20 /* For s2mpg1x, the revision is in a different regmap */ - if (sec_pmic->device_type =3D=3D S2MPG10) + switch (sec_pmic->device_type) { + case S2MPG10: + case S2MPG11: return; + default: + break; + } =20 /* For each device type, the REG_ID is always the first register */ if (!regmap_read(sec_pmic->regmap_pmic, S2MPS11_REG_ID, &val)) @@ -192,6 +204,10 @@ int sec_pmic_probe(struct device *dev, int device_type= , unsigned int irq, sec_devs =3D s2mpg10_devs; num_sec_devs =3D ARRAY_SIZE(s2mpg10_devs); break; + case S2MPG11: + sec_devs =3D s2mpg11_devs; + num_sec_devs =3D ARRAY_SIZE(s2mpg11_devs); + break; case S2MPS11X: sec_devs =3D s2mps11_devs; num_sec_devs =3D ARRAY_SIZE(s2mps11_devs); diff --git a/drivers/mfd/sec-irq.c b/drivers/mfd/sec-irq.c index c5c80b1ba104e6c5a55b442d2f10a8554201a961..a04e46144baae6a195a84df56c5= 3e399e3875e3d 100644 --- a/drivers/mfd/sec-irq.c +++ b/drivers/mfd/sec-irq.c @@ -11,6 +11,7 @@ #include #include #include +#include #include #include #include @@ -73,6 +74,58 @@ static const struct regmap_irq s2mpg10_irqs[] =3D { REGMAP_IRQ_REG(S2MPG10_IRQ_PWR_WARN_CH7, 5, S2MPG10_IRQ_PWR_WARN_CH7_MASK= ), }; =20 +static const struct regmap_irq s2mpg11_irqs[] =3D { + REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONF, 0, S2MPG11_IRQ_PWRONF_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWRONR, 0, S2MPG11_IRQ_PWRONR_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUT_MIF, 0, S2MPG11_IRQ_PIF_TIMEOUT_MI= F_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PIF_TIMEOUTS, 0, S2MPG11_IRQ_PIF_TIMEOUTS_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_WTSR, 0, S2MPG11_IRQ_WTSR_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_ABNORMAL_STOP, 0, S2MPG11_IRQ_SPD_ABNORMAL= _STOP_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_PARITY_ERR, 0, S2MPG11_IRQ_SPD_PARITY_ERR_= MASK), + + REGMAP_IRQ_REG(S2MPG11_IRQ_140C, 1, S2MPG11_IRQ_INT140C_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_120C, 1, S2MPG11_IRQ_INT120C_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_TSD, 1, S2MPG11_IRQ_TSD_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_WRST, 1, S2MPG11_IRQ_WRST_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_CYCLE_DONE, 1, S2MPG11_IRQ_NTC_CYCLE_DONE_= MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_PMETER_OVERF, 1, S2MPG11_IRQ_PMETER_OVERF_MASK= ), + + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B1S, 2, S2MPG11_IRQ_OCP_B1S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B2S, 2, S2MPG11_IRQ_OCP_B2S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B3S, 2, S2MPG11_IRQ_OCP_B3S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B4S, 2, S2MPG11_IRQ_OCP_B4S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B5S, 2, S2MPG11_IRQ_OCP_B5S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B6S, 2, S2MPG11_IRQ_OCP_B6S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B7S, 2, S2MPG11_IRQ_OCP_B7S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B8S, 2, S2MPG11_IRQ_OCP_B8S_MASK), + + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B9S, 3, S2MPG11_IRQ_OCP_B9S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_B10S, 3, S2MPG11_IRQ_OCP_B10S_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BDS, 3, S2MPG11_IRQ_OCP_BDS_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BAS, 3, S2MPG11_IRQ_OCP_BAS_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_OCP_BBS, 3, S2MPG11_IRQ_OCP_BBS_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_WLWP_ACC, 3, S2MPG11_IRQ_WLWP_ACC_MASK), + REGMAP_IRQ_REG(S2MPG11_IRQ_SPD_SRP_PKT_RST, 3, S2MPG11_IRQ_SPD_SRP_PKT_RS= T_MASK), + + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH0, 4, S2MPG11_IRQ_PWR_WARN_CH0_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH1, 4, S2MPG11_IRQ_PWR_WARN_CH1_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH2, 4, S2MPG11_IRQ_PWR_WARN_CH2_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH3, 4, S2MPG11_IRQ_PWR_WARN_CH3_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH4, 4, S2MPG11_IRQ_PWR_WARN_CH4_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH5, 4, S2MPG11_IRQ_PWR_WARN_CH5_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH6, 4, S2MPG11_IRQ_PWR_WARN_CH6_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_PWR_WARN_CH7, 4, S2MPG11_IRQ_PWR_WARN_CH7_MASK= ), + + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH0, 5, S2MPG11_IRQ_NTC_WARN_CH0_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH1, 5, S2MPG11_IRQ_NTC_WARN_CH1_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH2, 5, S2MPG11_IRQ_NTC_WARN_CH2_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH3, 5, S2MPG11_IRQ_NTC_WARN_CH3_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH4, 5, S2MPG11_IRQ_NTC_WARN_CH4_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH5, 5, S2MPG11_IRQ_NTC_WARN_CH5_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH6, 5, S2MPG11_IRQ_NTC_WARN_CH6_MASK= ), + REGMAP_IRQ_REG(S2MPG11_IRQ_NTC_WARN_CH7, 5, S2MPG11_IRQ_NTC_WARN_CH7_MASK= ), +}; + static const struct regmap_irq s2mps11_irqs[] =3D { REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONF, 0, S2MPS11_IRQ_PWRONF_MASK), REGMAP_IRQ_REG(S2MPS11_IRQ_PWRONR, 0, S2MPS11_IRQ_PWRONR_MASK), @@ -180,7 +233,7 @@ static const struct regmap_irq s5m8767_irqs[] =3D { REGMAP_IRQ_REG(S5M8767_IRQ_WTSR, 2, S5M8767_IRQ_WTSR_MASK), }; =20 -/* All S2MPG10 interrupt sources are read-only and don't require clearing = */ +/* All S2MPG1x interrupt sources are read-only and don't require clearing = */ static const struct regmap_irq_chip s2mpg10_irq_chip =3D { .name =3D "s2mpg10", .irqs =3D s2mpg10_irqs, @@ -190,6 +243,15 @@ static const struct regmap_irq_chip s2mpg10_irq_chip = =3D { .mask_base =3D S2MPG10_PMIC_INT1M, }; =20 +static const struct regmap_irq_chip s2mpg11_irq_chip =3D { + .name =3D "s2mpg11", + .irqs =3D s2mpg11_irqs, + .num_irqs =3D ARRAY_SIZE(s2mpg11_irqs), + .num_regs =3D 6, + .status_base =3D S2MPG11_PMIC_INT1, + .mask_base =3D S2MPG11_PMIC_INT1M, +}; + static const struct regmap_irq_chip s2mps11_irq_chip =3D { .name =3D "s2mps11", .irqs =3D s2mps11_irqs, @@ -270,6 +332,9 @@ int sec_irq_init(struct sec_pmic_dev *sec_pmic) case S2MPG10: sec_irq_chip =3D &s2mpg10_irq_chip; break; + case S2MPG11: + sec_irq_chip =3D &s2mpg11_irq_chip; + break; case S2MPS11X: sec_irq_chip =3D &s2mps11_irq_chip; break; diff --git a/include/linux/mfd/samsung/core.h b/include/linux/mfd/samsung/c= ore.h index d785e101fe795a5d8f9cccf4ccc4232437e89416..f5fba117bea61b3e3fb308759dc= 2748f6dd01dfb 100644 --- a/include/linux/mfd/samsung/core.h +++ b/include/linux/mfd/samsung/core.h @@ -40,6 +40,7 @@ enum sec_device_type { S2DOS05, S2MPA01, S2MPG10, + S2MPG11, S2MPS11X, S2MPS13X, S2MPS14X, diff --git a/include/linux/mfd/samsung/irq.h b/include/linux/mfd/samsung/ir= q.h index b4805cbd949bd605004bd88cf361109d1cbbc3bf..08b1ab33bad48194491fef88d48= d5d0027e06a7c 100644 --- a/include/linux/mfd/samsung/irq.h +++ b/include/linux/mfd/samsung/irq.h @@ -160,6 +160,105 @@ enum s2mpg10_irq { S2MPG10_IRQ_NR, }; =20 +enum s2mpg11_irq { + /* PMIC */ + S2MPG11_IRQ_PWRONF, + S2MPG11_IRQ_PWRONR, + S2MPG11_IRQ_PIF_TIMEOUT_MIF, + S2MPG11_IRQ_PIF_TIMEOUTS, + S2MPG11_IRQ_WTSR, + S2MPG11_IRQ_SPD_ABNORMAL_STOP, + S2MPG11_IRQ_SPD_PARITY_ERR, +#define S2MPG11_IRQ_PWRONF_MASK BIT(0) +#define S2MPG11_IRQ_PWRONR_MASK BIT(1) +#define S2MPG11_IRQ_PIF_TIMEOUT_MIF_MASK BIT(3) +#define S2MPG11_IRQ_PIF_TIMEOUTS_MASK BIT(4) +#define S2MPG11_IRQ_WTSR_MASK BIT(5) +#define S2MPG11_IRQ_SPD_ABNORMAL_STOP_MASK BIT(6) +#define S2MPG11_IRQ_SPD_PARITY_ERR_MASK BIT(7) + + S2MPG11_IRQ_140C, + S2MPG11_IRQ_120C, + S2MPG11_IRQ_TSD, + S2MPG11_IRQ_WRST, + S2MPG11_IRQ_NTC_CYCLE_DONE, + S2MPG11_IRQ_PMETER_OVERF, +#define S2MPG11_IRQ_INT140C_MASK BIT(0) +#define S2MPG11_IRQ_INT120C_MASK BIT(1) +#define S2MPG11_IRQ_TSD_MASK BIT(2) +#define S2MPG11_IRQ_WRST_MASK BIT(5) +#define S2MPG11_IRQ_NTC_CYCLE_DONE_MASK BIT(6) +#define S2MPG11_IRQ_PMETER_OVERF_MASK BIT(7) + + S2MPG11_IRQ_OCP_B1S, + S2MPG11_IRQ_OCP_B2S, + S2MPG11_IRQ_OCP_B3S, + S2MPG11_IRQ_OCP_B4S, + S2MPG11_IRQ_OCP_B5S, + S2MPG11_IRQ_OCP_B6S, + S2MPG11_IRQ_OCP_B7S, + S2MPG11_IRQ_OCP_B8S, +#define S2MPG11_IRQ_OCP_B1S_MASK BIT(0) +#define S2MPG11_IRQ_OCP_B2S_MASK BIT(1) +#define S2MPG11_IRQ_OCP_B3S_MASK BIT(2) +#define S2MPG11_IRQ_OCP_B4S_MASK BIT(3) +#define S2MPG11_IRQ_OCP_B5S_MASK BIT(4) +#define S2MPG11_IRQ_OCP_B6S_MASK BIT(5) +#define S2MPG11_IRQ_OCP_B7S_MASK BIT(6) +#define S2MPG11_IRQ_OCP_B8S_MASK BIT(7) + + S2MPG11_IRQ_OCP_B9S, + S2MPG11_IRQ_OCP_B10S, + S2MPG11_IRQ_OCP_BDS, + S2MPG11_IRQ_OCP_BAS, + S2MPG11_IRQ_OCP_BBS, + S2MPG11_IRQ_WLWP_ACC, + S2MPG11_IRQ_SPD_SRP_PKT_RST, +#define S2MPG11_IRQ_OCP_B9S_MASK BIT(0) +#define S2MPG11_IRQ_OCP_B10S_MASK BIT(1) +#define S2MPG11_IRQ_OCP_BDS_MASK BIT(2) +#define S2MPG11_IRQ_OCP_BAS_MASK BIT(3) +#define S2MPG11_IRQ_OCP_BBS_MASK BIT(4) +#define S2MPG11_IRQ_WLWP_ACC_MASK BIT(5) +#define S2MPG11_IRQ_SPD_SRP_PKT_RST_MASK BIT(7) + + S2MPG11_IRQ_PWR_WARN_CH0, + S2MPG11_IRQ_PWR_WARN_CH1, + S2MPG11_IRQ_PWR_WARN_CH2, + S2MPG11_IRQ_PWR_WARN_CH3, + S2MPG11_IRQ_PWR_WARN_CH4, + S2MPG11_IRQ_PWR_WARN_CH5, + S2MPG11_IRQ_PWR_WARN_CH6, + S2MPG11_IRQ_PWR_WARN_CH7, +#define S2MPG11_IRQ_PWR_WARN_CH0_MASK BIT(0) +#define S2MPG11_IRQ_PWR_WARN_CH1_MASK BIT(1) +#define S2MPG11_IRQ_PWR_WARN_CH2_MASK BIT(2) +#define S2MPG11_IRQ_PWR_WARN_CH3_MASK BIT(3) +#define S2MPG11_IRQ_PWR_WARN_CH4_MASK BIT(4) +#define S2MPG11_IRQ_PWR_WARN_CH5_MASK BIT(5) +#define S2MPG11_IRQ_PWR_WARN_CH6_MASK BIT(6) +#define S2MPG11_IRQ_PWR_WARN_CH7_MASK BIT(7) + + S2MPG11_IRQ_NTC_WARN_CH0, + S2MPG11_IRQ_NTC_WARN_CH1, + S2MPG11_IRQ_NTC_WARN_CH2, + S2MPG11_IRQ_NTC_WARN_CH3, + S2MPG11_IRQ_NTC_WARN_CH4, + S2MPG11_IRQ_NTC_WARN_CH5, + S2MPG11_IRQ_NTC_WARN_CH6, + S2MPG11_IRQ_NTC_WARN_CH7, +#define S2MPG11_IRQ_NTC_WARN_CH0_MASK BIT(0) +#define S2MPG11_IRQ_NTC_WARN_CH1_MASK BIT(1) +#define S2MPG11_IRQ_NTC_WARN_CH2_MASK BIT(2) +#define S2MPG11_IRQ_NTC_WARN_CH3_MASK BIT(3) +#define S2MPG11_IRQ_NTC_WARN_CH4_MASK BIT(4) +#define S2MPG11_IRQ_NTC_WARN_CH5_MASK BIT(5) +#define S2MPG11_IRQ_NTC_WARN_CH6_MASK BIT(6) +#define S2MPG11_IRQ_NTC_WARN_CH7_MASK BIT(7) + + S2MPG11_IRQ_NR, +}; + enum s2mps11_irq { S2MPS11_IRQ_PWRONF, S2MPS11_IRQ_PWRONR, diff --git a/include/linux/mfd/samsung/s2mpg11.h b/include/linux/mfd/samsun= g/s2mpg11.h new file mode 100644 index 0000000000000000000000000000000000000000..e4de7665f19fdb05dc4fcb83752= 728013d7a79ff --- /dev/null +++ b/include/linux/mfd/samsung/s2mpg11.h @@ -0,0 +1,420 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2015 Samsung Electronics + * Copyright 2020 Google Inc + * Copyright 2025 Linaro Ltd. + */ + +#ifndef __LINUX_MFD_S2MPG11_H +#define __LINUX_MFD_S2MPG11_H + +/* Common registers (type 0x000) */ +enum s2mpg11_common_reg { + S2MPG11_COMMON_CHIPID, + S2MPG11_COMMON_INT, + S2MPG11_COMMON_INT_MASK, + S2MPG11_COMMON_SPD_CTRL1 =3D 0x0a, + S2MPG11_COMMON_SPD_CTRL2, + S2MPG11_COMMON_SPD_CTRL3, + S2MPG11_COMMON_MON1SEL =3D 0x1a, + S2MPG11_COMMON_MON2SEL, + S2MPG11_COMMON_MONR, + S2MPG11_COMMON_DEBUG_CTRL1, + S2MPG11_COMMON_DEBUG_CTRL2, + S2MPG11_COMMON_DEBUG_CTRL3, + S2MPG11_COMMON_DEBUG_CTRL4, + S2MPG11_COMMON_DEBUG_CTRL5, + S2MPG11_COMMON_DEBUG_CTRL6, + S2MPG11_COMMON_TEST_MODE1, + S2MPG11_COMMON_SPD_DEBUG1, + S2MPG11_COMMON_SPD_DEBUG2, + S2MPG11_COMMON_SPD_DEBUG3, + S2MPG11_COMMON_SPD_DEBUG4, +}; + +/* For S2MPG11_COMMON_INT and S2MPG11_COMMON_INT_MASK */ +#define S2MPG11_COMMON_INT_SRC GENMASK(2, 0) +#define S2MPG11_COMMON_INT_SRC_PMIC BIT(0) + +/* PMIC registers (type 0x100) */ +enum s2mpg11_pmic_reg { + S2MPG11_PMIC_INT1, + S2MPG11_PMIC_INT2, + S2MPG11_PMIC_INT3, + S2MPG11_PMIC_INT4, + S2MPG11_PMIC_INT5, + S2MPG11_PMIC_INT6, + S2MPG11_PMIC_INT1M, + S2MPG11_PMIC_INT2M, + S2MPG11_PMIC_INT3M, + S2MPG11_PMIC_INT4M, + S2MPG11_PMIC_INT5M, + S2MPG11_PMIC_INT6M, + S2MPG11_PMIC_STATUS1, + S2MPG11_PMIC_OFFSRC, + S2MPG11_PMIC_COMMON_CTRL1, + S2MPG11_PMIC_COMMON_CTRL2, + S2MPG11_PMIC_COMMON_CTRL3, + S2MPG11_PMIC_MIMICKING_CTRL, + S2MPG11_PMIC_B1S_CTRL, + S2MPG11_PMIC_B1S_OUT1, + S2MPG11_PMIC_B1S_OUT2, + S2MPG11_PMIC_B2S_CTRL, + S2MPG11_PMIC_B2S_OUT1, + S2MPG11_PMIC_B2S_OUT2, + S2MPG11_PMIC_B3S_CTRL, + S2MPG11_PMIC_B3S_OUT1, + S2MPG11_PMIC_B3S_OUT2, + S2MPG11_PMIC_B4S_CTRL, + S2MPG11_PMIC_B4S_OUT, + S2MPG11_PMIC_B5S_CTRL, + S2MPG11_PMIC_B5S_OUT, + S2MPG11_PMIC_B6S_CTRL, + S2MPG11_PMIC_B6S_OUT1, + S2MPG11_PMIC_B6S_OUT2, + S2MPG11_PMIC_B7S_CTRL, + S2MPG11_PMIC_B7S_OUT1, + S2MPG11_PMIC_B7S_OUT2, + S2MPG11_PMIC_B8S_CTRL, + S2MPG11_PMIC_B8S_OUT1, + S2MPG11_PMIC_B8S_OUT2, + S2MPG11_PMIC_B9S_CTRL, + S2MPG11_PMIC_B9S_OUT1, + S2MPG11_PMIC_B9S_OUT2, + S2MPG11_PMIC_B10S_CTRL, + S2MPG11_PMIC_B10S_OUT, + S2MPG11_PMIC_BUCKD_CTRL, + S2MPG11_PMIC_BUCKD_OUT, + S2MPG11_PMIC_BUCKA_CTRL, + S2MPG11_PMIC_BUCKA_OUT, + S2MPG11_PMIC_BB_CTRL, + S2MPG11_PMIC_BB_OUT1, + S2MPG11_PMIC_BB_OUT2, + S2MPG11_PMIC_BUCK1S_USONIC, + S2MPG11_PMIC_BUCK2S_USONIC, + S2MPG11_PMIC_BUCK3S_USONIC, + S2MPG11_PMIC_BUCK4S_USONIC, + S2MPG11_PMIC_BUCK5S_USONIC, + S2MPG11_PMIC_BUCK6S_USONIC, + S2MPG11_PMIC_BUCK7S_USONIC, + S2MPG11_PMIC_BUCK8S_USONIC, + S2MPG11_PMIC_BUCK9S_USONIC, + S2MPG11_PMIC_BUCK10S_USONIC, + S2MPG11_PMIC_BUCKD_USONIC, + S2MPG11_PMIC_BUCKA_USONIC, + S2MPG11_PMIC_BB_USONIC, + S2MPG11_PMIC_L1S_CTRL1, + S2MPG11_PMIC_L1S_CTRL2, + S2MPG11_PMIC_L2S_CTRL1, + S2MPG11_PMIC_L2S_CTRL2, + S2MPG11_PMIC_L3S_CTRL, + S2MPG11_PMIC_L4S_CTRL, + S2MPG11_PMIC_L5S_CTRL, + S2MPG11_PMIC_L6S_CTRL, + S2MPG11_PMIC_L7S_CTRL, + S2MPG11_PMIC_L8S_CTRL, + S2MPG11_PMIC_L9S_CTRL, + S2MPG11_PMIC_L10S_CTRL, + S2MPG11_PMIC_L11S_CTRL, + S2MPG11_PMIC_L12S_CTRL, + S2MPG11_PMIC_L13S_CTRL, + S2MPG11_PMIC_L14S_CTRL, + S2MPG11_PMIC_L15S_CTRL, + S2MPG11_PMIC_LDO_CTRL1, + S2MPG11_PMIC_LDO_DSCH1, + S2MPG11_PMIC_LDO_DSCH2, + S2MPG11_PMIC_DVS_RAMP1, + S2MPG11_PMIC_DVS_RAMP2, + S2MPG11_PMIC_DVS_RAMP3, + S2MPG11_PMIC_DVS_RAMP4, + S2MPG11_PMIC_DVS_RAMP5, + S2MPG11_PMIC_DVS_RAMP6, + /* Nothing @ 0x5a */ + S2MPG11_PMIC_DVS_SYNC_CTRL1 =3D 0x5c, + S2MPG11_PMIC_DVS_SYNC_CTRL2, + S2MPG11_PMIC_OFF_CTRL1, + S2MPG11_PMIC_OFF_CTRL2, + S2MPG11_PMIC_OFF_CTRL3, + S2MPG11_PMIC_SEQ_CTRL1, + S2MPG11_PMIC_SEQ_CTRL2, + S2MPG11_PMIC_SEQ_CTRL3, + S2MPG11_PMIC_SEQ_CTRL4, + S2MPG11_PMIC_SEQ_CTRL5, + S2MPG11_PMIC_SEQ_CTRL6, + S2MPG11_PMIC_SEQ_CTRL7, + S2MPG11_PMIC_SEQ_CTRL8, + S2MPG11_PMIC_SEQ_CTRL9, + S2MPG11_PMIC_SEQ_CTRL10, + S2MPG11_PMIC_SEQ_CTRL11, + S2MPG11_PMIC_SEQ_CTRL12, + S2MPG11_PMIC_SEQ_CTRL13, + S2MPG11_PMIC_SEQ_CTRL14, + S2MPG11_PMIC_SEQ_CTRL15, + S2MPG11_PMIC_SEQ_CTRL16, + S2MPG11_PMIC_SEQ_CTRL17, + S2MPG11_PMIC_SEQ_CTRL18, + S2MPG11_PMIC_SEQ_CTRL19, + S2MPG11_PMIC_SEQ_CTRL20, + S2MPG11_PMIC_SEQ_CTRL21, + S2MPG11_PMIC_SEQ_CTRL22, + S2MPG11_PMIC_SEQ_CTRL23, + S2MPG11_PMIC_SEQ_CTRL24, + S2MPG11_PMIC_SEQ_CTRL25, + S2MPG11_PMIC_SEQ_CTRL26, + S2MPG11_PMIC_SEQ_CTRL27, + S2MPG11_PMIC_OFF_SEQ_CTRL1, + S2MPG11_PMIC_OFF_SEQ_CTRL2, + S2MPG11_PMIC_OFF_SEQ_CTRL3, + S2MPG11_PMIC_OFF_SEQ_CTRL4, + S2MPG11_PMIC_OFF_SEQ_CTRL5, + S2MPG11_PMIC_OFF_SEQ_CTRL6, + S2MPG11_PMIC_OFF_SEQ_CTRL7, + S2MPG11_PMIC_OFF_SEQ_CTRL8, + S2MPG11_PMIC_OFF_SEQ_CTRL9, + S2MPG11_PMIC_OFF_SEQ_CTRL10, + S2MPG11_PMIC_OFF_SEQ_CTRL11, + S2MPG11_PMIC_OFF_SEQ_CTRL12, + S2MPG11_PMIC_OFF_SEQ_CTRL13, + S2MPG11_PMIC_OFF_SEQ_CTRL14, + S2MPG11_PMIC_OFF_SEQ_CTRL15, + S2MPG11_PMIC_OFF_SEQ_CTRL16, + S2MPG11_PMIC_OFF_SEQ_CTRL17, + S2MPG11_PMIC_PCTRLSEL1, + S2MPG11_PMIC_PCTRLSEL2, + S2MPG11_PMIC_PCTRLSEL3, + S2MPG11_PMIC_PCTRLSEL4, + S2MPG11_PMIC_PCTRLSEL5, + S2MPG11_PMIC_PCTRLSEL6, + S2MPG11_PMIC_DCTRLSEL1, + S2MPG11_PMIC_DCTRLSEL2, + S2MPG11_PMIC_DCTRLSEL3, + S2MPG11_PMIC_DCTRLSEL4, + S2MPG11_PMIC_DCTRLSEL5, + S2MPG11_PMIC_GPIO_CTRL1, + S2MPG11_PMIC_GPIO_CTRL2, + S2MPG11_PMIC_GPIO_CTRL3, + S2MPG11_PMIC_GPIO_CTRL4, + S2MPG11_PMIC_GPIO_CTRL5, + S2MPG11_PMIC_GPIO_CTRL6, + S2MPG11_PMIC_GPIO_CTRL7, + S2MPG11_PMIC_B2S_OCP_WARN, + S2MPG11_PMIC_B2S_OCP_WARN_X, + S2MPG11_PMIC_B2S_OCP_WARN_Y, + S2MPG11_PMIC_B2S_OCP_WARN_Z, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_X, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Y, + S2MPG11_PMIC_B2S_SOFT_OCP_WARN_Z, + S2MPG11_PMIC_BUCK_OCP_EN1, + S2MPG11_PMIC_BUCK_OCP_EN2, + S2MPG11_PMIC_BUCK_OCP_PD_EN1, + S2MPG11_PMIC_BUCK_OCP_PD_EN2, + S2MPG11_PMIC_BUCK_OCP_CTRL1, + S2MPG11_PMIC_BUCK_OCP_CTRL2, + S2MPG11_PMIC_BUCK_OCP_CTRL3, + S2MPG11_PMIC_BUCK_OCP_CTRL4, + S2MPG11_PMIC_BUCK_OCP_CTRL5, + S2MPG11_PMIC_BUCK_OCP_CTRL6, + S2MPG11_PMIC_BUCK_OCP_CTRL7, + S2MPG11_PMIC_PIF_CTRL, + S2MPG11_PMIC_BUCK_HR_MODE1, + S2MPG11_PMIC_BUCK_HR_MODE2, + S2MPG11_PMIC_FAULTOUT_CTRL, + S2MPG11_PMIC_LDO_SENSE1, + S2MPG11_PMIC_LDO_SENSE2, +}; + +/* Meter registers (type 0xa00) */ +enum s2mpg11_meter_reg { + S2MPG11_METER_CTRL1, + S2MPG11_METER_CTRL2, + S2MPG11_METER_CTRL3, + S2MPG11_METER_CTRL4, + S2MPG11_METER_CTRL5, + S2MPG11_METER_BUCKEN1, + S2MPG11_METER_BUCKEN2, + S2MPG11_METER_MUXSEL0, + S2MPG11_METER_MUXSEL1, + S2MPG11_METER_MUXSEL2, + S2MPG11_METER_MUXSEL3, + S2MPG11_METER_MUXSEL4, + S2MPG11_METER_MUXSEL5, + S2MPG11_METER_MUXSEL6, + S2MPG11_METER_MUXSEL7, + S2MPG11_METER_LPF_C0_0, + S2MPG11_METER_LPF_C0_1, + S2MPG11_METER_LPF_C0_2, + S2MPG11_METER_LPF_C0_3, + S2MPG11_METER_LPF_C0_4, + S2MPG11_METER_LPF_C0_5, + S2MPG11_METER_LPF_C0_6, + S2MPG11_METER_LPF_C0_7, + S2MPG11_METER_NTC_LPF_C0_0, + S2MPG11_METER_NTC_LPF_C0_1, + S2MPG11_METER_NTC_LPF_C0_2, + S2MPG11_METER_NTC_LPF_C0_3, + S2MPG11_METER_NTC_LPF_C0_4, + S2MPG11_METER_NTC_LPF_C0_5, + S2MPG11_METER_NTC_LPF_C0_6, + S2MPG11_METER_NTC_LPF_C0_7, + S2MPG11_METER_PWR_WARN0, + S2MPG11_METER_PWR_WARN1, + S2MPG11_METER_PWR_WARN2, + S2MPG11_METER_PWR_WARN3, + S2MPG11_METER_PWR_WARN4, + S2MPG11_METER_PWR_WARN5, + S2MPG11_METER_PWR_WARN6, + S2MPG11_METER_PWR_WARN7, + S2MPG11_METER_NTC_L_WARN0, + S2MPG11_METER_NTC_L_WARN1, + S2MPG11_METER_NTC_L_WARN2, + S2MPG11_METER_NTC_L_WARN3, + S2MPG11_METER_NTC_L_WARN4, + S2MPG11_METER_NTC_L_WARN5, + S2MPG11_METER_NTC_L_WARN6, + S2MPG11_METER_NTC_L_WARN7, + S2MPG11_METER_NTC_H_WARN0, + S2MPG11_METER_NTC_H_WARN1, + S2MPG11_METER_NTC_H_WARN2, + S2MPG11_METER_NTC_H_WARN3, + S2MPG11_METER_NTC_H_WARN4, + S2MPG11_METER_NTC_H_WARN5, + S2MPG11_METER_NTC_H_WARN6, + S2MPG11_METER_NTC_H_WARN7, + S2MPG11_METER_PWR_HYS1, + S2MPG11_METER_PWR_HYS2, + S2MPG11_METER_PWR_HYS3, + S2MPG11_METER_PWR_HYS4, + S2MPG11_METER_NTC_HYS1, + S2MPG11_METER_NTC_HYS2, + S2MPG11_METER_NTC_HYS3, + S2MPG11_METER_NTC_HYS4, + /* Nothing @ 0x3f */ + S2MPG11_METER_ACC_DATA_CH0_1 =3D 0x40, + S2MPG11_METER_ACC_DATA_CH0_2, + S2MPG11_METER_ACC_DATA_CH0_3, + S2MPG11_METER_ACC_DATA_CH0_4, + S2MPG11_METER_ACC_DATA_CH0_5, + S2MPG11_METER_ACC_DATA_CH0_6, + S2MPG11_METER_ACC_DATA_CH1_1, + S2MPG11_METER_ACC_DATA_CH1_2, + S2MPG11_METER_ACC_DATA_CH1_3, + S2MPG11_METER_ACC_DATA_CH1_4, + S2MPG11_METER_ACC_DATA_CH1_5, + S2MPG11_METER_ACC_DATA_CH1_6, + S2MPG11_METER_ACC_DATA_CH2_1, + S2MPG11_METER_ACC_DATA_CH2_2, + S2MPG11_METER_ACC_DATA_CH2_3, + S2MPG11_METER_ACC_DATA_CH2_4, + S2MPG11_METER_ACC_DATA_CH2_5, + S2MPG11_METER_ACC_DATA_CH2_6, + S2MPG11_METER_ACC_DATA_CH3_1, + S2MPG11_METER_ACC_DATA_CH3_2, + S2MPG11_METER_ACC_DATA_CH3_3, + S2MPG11_METER_ACC_DATA_CH3_4, + S2MPG11_METER_ACC_DATA_CH3_5, + S2MPG11_METER_ACC_DATA_CH3_6, + S2MPG11_METER_ACC_DATA_CH4_1, + S2MPG11_METER_ACC_DATA_CH4_2, + S2MPG11_METER_ACC_DATA_CH4_3, + S2MPG11_METER_ACC_DATA_CH4_4, + S2MPG11_METER_ACC_DATA_CH4_5, + S2MPG11_METER_ACC_DATA_CH4_6, + S2MPG11_METER_ACC_DATA_CH5_1, + S2MPG11_METER_ACC_DATA_CH5_2, + S2MPG11_METER_ACC_DATA_CH5_3, + S2MPG11_METER_ACC_DATA_CH5_4, + S2MPG11_METER_ACC_DATA_CH5_5, + S2MPG11_METER_ACC_DATA_CH5_6, + S2MPG11_METER_ACC_DATA_CH6_1, + S2MPG11_METER_ACC_DATA_CH6_2, + S2MPG11_METER_ACC_DATA_CH6_3, + S2MPG11_METER_ACC_DATA_CH6_4, + S2MPG11_METER_ACC_DATA_CH6_5, + S2MPG11_METER_ACC_DATA_CH6_6, + S2MPG11_METER_ACC_DATA_CH7_1, + S2MPG11_METER_ACC_DATA_CH7_2, + S2MPG11_METER_ACC_DATA_CH7_3, + S2MPG11_METER_ACC_DATA_CH7_4, + S2MPG11_METER_ACC_DATA_CH7_5, + S2MPG11_METER_ACC_DATA_CH7_6, + S2MPG11_METER_ACC_COUNT_1, + S2MPG11_METER_ACC_COUNT_2, + S2MPG11_METER_ACC_COUNT_3, + S2MPG11_METER_LPF_DATA_CH0_1, + S2MPG11_METER_LPF_DATA_CH0_2, + S2MPG11_METER_LPF_DATA_CH0_3, + S2MPG11_METER_LPF_DATA_CH1_1, + S2MPG11_METER_LPF_DATA_CH1_2, + S2MPG11_METER_LPF_DATA_CH1_3, + S2MPG11_METER_LPF_DATA_CH2_1, + S2MPG11_METER_LPF_DATA_CH2_2, + S2MPG11_METER_LPF_DATA_CH2_3, + S2MPG11_METER_LPF_DATA_CH3_1, + S2MPG11_METER_LPF_DATA_CH3_2, + S2MPG11_METER_LPF_DATA_CH3_3, + S2MPG11_METER_LPF_DATA_CH4_1, + S2MPG11_METER_LPF_DATA_CH4_2, + S2MPG11_METER_LPF_DATA_CH4_3, + S2MPG11_METER_LPF_DATA_CH5_1, + S2MPG11_METER_LPF_DATA_CH5_2, + S2MPG11_METER_LPF_DATA_CH5_3, + S2MPG11_METER_LPF_DATA_CH6_1, + S2MPG11_METER_LPF_DATA_CH6_2, + S2MPG11_METER_LPF_DATA_CH6_3, + S2MPG11_METER_LPF_DATA_CH7_1, + S2MPG11_METER_LPF_DATA_CH7_2, + S2MPG11_METER_LPF_DATA_CH7_3, + /* Nothing @ 0x8b 0x8c */ + S2MPG11_METER_LPF_DATA_NTC0_1 =3D 0x8d, + S2MPG11_METER_LPF_DATA_NTC0_2, + S2MPG11_METER_LPF_DATA_NTC1_1, + S2MPG11_METER_LPF_DATA_NTC1_2, + S2MPG11_METER_LPF_DATA_NTC2_1, + S2MPG11_METER_LPF_DATA_NTC2_2, + S2MPG11_METER_LPF_DATA_NTC3_1, + S2MPG11_METER_LPF_DATA_NTC3_2, + S2MPG11_METER_LPF_DATA_NTC4_1, + S2MPG11_METER_LPF_DATA_NTC4_2, + S2MPG11_METER_LPF_DATA_NTC5_1, + S2MPG11_METER_LPF_DATA_NTC5_2, + S2MPG11_METER_LPF_DATA_NTC6_1, + S2MPG11_METER_LPF_DATA_NTC6_2, + S2MPG11_METER_LPF_DATA_NTC7_1, + S2MPG11_METER_LPF_DATA_NTC7_2, +}; + +/* S2MPG11 regulator IDs */ +enum s2mpg11_regulators { + S2MPG11_LDO1, + S2MPG11_LDO2, + S2MPG11_LDO3, + S2MPG11_LDO4, + S2MPG11_LDO5, + S2MPG11_LDO6, + S2MPG11_LDO7, + S2MPG11_LDO8, + S2MPG11_LDO9, + S2MPG11_LDO10, + S2MPG11_LDO11, + S2MPG11_LDO12, + S2MPG11_LDO13, + S2MPG11_LDO14, + S2MPG11_LDO15, + S2MPG11_BUCK1, + S2MPG11_BUCK2, + S2MPG11_BUCK3, + S2MPG11_BUCK4, + S2MPG11_BUCK5, + S2MPG11_BUCK6, + S2MPG11_BUCK7, + S2MPG11_BUCK8, + S2MPG11_BUCK9, + S2MPG11_BUCK10, + S2MPG11_BUCKD, + S2MPG11_BUCKA, + S2MPG11_BUCKBOOST, + S2MPG11_REGULATOR_MAX, +}; + +#endif /* __LINUX_MFD_S2MPG11_H */ --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA0C81AF0B4 for ; Wed, 4 Jun 2025 15:25:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050753; cv=none; b=k4q2mLKSDDMgXZQbyODPgx9RljiSRVnjU+WXnewfMfSANU8FfXg8a7sgemZUV/6qtyVWfF4As9Nrxyxy9GhbLNz++wUT/TfFjX677uy5UCKBuYJ6xvErxTeH1B2d0jc4q9mmqJR/4OxWPunO99pCcAuJIu0fPHN6QU7sLRQQRxo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050753; c=relaxed/simple; bh=ZloWrNFeMmVe3/HDuD1aXKWP+8PNEOlvbHUi95SknjM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bTCRqNB1r9seJjNBRo2DD+oVkih1/uaFvFqvWMcPQNQ4VHCxquCBsWqpov9MdNrRhsliXXCbfZINCTd48PQC6BIlmh+QcKrzqeGMOGsyFu+kjj8sXl810EXAH6CdtQAdAf++RkSpK7H5s32RNoCoeGibIpqUwOexaH7BgAtkuQ4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cEEDtvhr; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cEEDtvhr" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-601dfef6a8dso11559567a12.1 for ; Wed, 04 Jun 2025 08:25:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050750; x=1749655550; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=RK6fDlVurrAhSO63sHrDo/ZYoV5lV5EQ9BPN02YtAuw=; b=cEEDtvhr+N7PEGXPEhrUeFyCa2qMbNtm/P0Ohq03cvSAEPWkKTQWaWgvMzPAwZ3viP zRE3yGsRYKJMYizY12jupVh2sj3akcOfCWdc/140wTbE2OBIDZWodN3ul+idJosE70Wl BY/6GrHREpcUeewuFqLXsOvtYOV1JaskxSaHVUbsJyyOHlWHBLbNi0mNS/pfnmupNFSA tXt9l0KeJhXI7DAkb0Zl2aQOo6P5IA35b9XKeGqJJURCP+AVdn4so4fa8Ezk3m3TXbqv 4dhlX32QPgpnBAjxfTJCg3PHnfEAX3Ig3NsyaNCKZKqNb2OwczUasGSt2lB0HXxTLiRm QM1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050750; x=1749655550; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=RK6fDlVurrAhSO63sHrDo/ZYoV5lV5EQ9BPN02YtAuw=; b=k9gxveYlgfSoX0x44IduClkhDBY+nx6Dn4D0BYrN/ND89gQMKDhF9VWXRA0r50fsC3 PHqL9YcnHIuqBzdN6Lp/1ir8HHABV/Pi6FDchEISsQie+tSBs9LmmcG9dw+3NxNyjVf5 sfxLyY3/16Y7mzRUR9uNZ2OcEmdN0PZG5Xvxf/tsuKnyr2lq3SUdTH4u8CAPOYk1UlVi lFMBC6zkMdgytqfAMQ0ltbCOYruZh43jlkCay4d7iYohiD9w4Sm4WTb0eiBtzq70zQmd nO3IhhMDtp9ZOLoN+RAS0qEweicwfMip7jNEU2fHW7wqkoh9ECvbNyULr67U44PMlq4Y OqIg== X-Forwarded-Encrypted: i=1; AJvYcCX6f8uc4d1XZRu9X01vaKaqt8aSGFx8K1YX7/a+MBXsLzJADqJBxEqWtR47dcEpXhgf65Bmn4lGDnxGWgQ=@vger.kernel.org X-Gm-Message-State: AOJu0YxbwUa01VhUsatyqwIEShnPB/XbFuxr8ml+8yowYKrZv7ZMxqTU 8gTuZl3orC7G0worfTmJLzZVJN4bxz7w5YhA9vCkffa/3qOddOafQCDDJuXAGJXH/Is= X-Gm-Gg: ASbGncthwN44XXe6Gar5fvXdbuFBFiZA7i4tdx03F/bJm7dOsZZuhzFVotj8etMlWwV 6iEcex1fHa+lkMArUFxI5IzHtiBYZ35Mree52JkKm5Gbqz4Sr3kERAJTutcyGZD49vHioPkJ2qW mBhmo+SNU/1KR0Q+9eXGBCwZHe9nOCfzFQmmKrtzClpaaKTsIp3wYsys6UFCh3SrRDa9giRrHIp aFcQmKNczIhPfduKlLbsw3CHWaGLMGkUIKv70vhC57H8OB7/zgqXf3fNWfZv4sFpz/C7G4JniMh GQIffZMWXvxBkHq4zuXYYHAVnWKYiCG27lIkmCJYyzvlyjF6IeuZKKwB5G3s7DdJ6SOyYoxhTRa osAw0RIxwqpwJx3YyfnW1DjcNqH9EpI/sDO3/c7ID07aPSw== X-Google-Smtp-Source: AGHT+IGie5OT/C4dKIZS01jGdu9pcMB4S96GfIIlXrVLkYBNWiD38sd2vviPzRoeqlZOJ6SG51yRIg== X-Received: by 2002:a05:6402:1d49:b0:601:31e6:698d with SMTP id 4fb4d7f45d1cf-606ea190c59mr3038407a12.23.1749050750307; Wed, 04 Jun 2025 08:25:50 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:49 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:48 +0100 Subject: [PATCH 09/17] regulator: s2mps11: drop two needless variable initialisations Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-9-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The initialisations being removed are needless, as both variables are being assigned values unconditionally further down. Additionally, doing this eager init here might lead to preventing the compiler from issuing a warning if a future code change actually forgets to assign a useful value in some code path. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 04ae9c6150bd5ae9dba47b9b3cfcfb62e4698b6d..1f51fbc6c7b6e158f9707c04d9f= 030b9eee5e842 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1207,8 +1207,8 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) struct sec_pmic_dev *iodev =3D dev_get_drvdata(pdev->dev.parent); struct regulator_config config =3D { }; struct s2mps11_info *s2mps11; - unsigned int rdev_num =3D 0; - int i, ret =3D 0; + unsigned int rdev_num; + int i, ret; const struct regulator_desc *regulators; =20 s2mps11 =3D devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info), --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f49.google.com (mail-ed1-f49.google.com [209.85.208.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B47E11C1AB4 for ; Wed, 4 Jun 2025 15:25:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050756; cv=none; b=OvpmCakFaSOmMhX7eXpFw6lN0e3LiT28xPQwKKtfAhOYcBUVEe50WJ5udv/UqXCrb2ttuFtUsTFpXfjaU+4OoaFEfdfAh2HfEmw9qIDWL+0KMs5yrTILsnCrfmliDh0fH7E+lIxcN/fEA5nBWiGHu4KzBPvXAXY/Q/0JgU6ga9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050756; c=relaxed/simple; bh=c2aRLM4UNSTnoEX6tceyJE+UXM8XBojhYH6J3V4X4cc=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SN+CjlMEGmEyfUnkaHF5G0bf/vfHasoHAF1W5YJUwWXn+pjxCjg4aYIXpGyH4zeaLlUISLskDPnPydezLWzxtpDLrDW9lT50cPIG6/RiFVRvBTjKvz/Unyt+OrXaakDZQ+pQLm415GsgVHw/VDvFW0sv1EX2U2W1/pbqkDYaCgI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RCTdkX5y; arc=none smtp.client-ip=209.85.208.49 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RCTdkX5y" Received: by mail-ed1-f49.google.com with SMTP id 4fb4d7f45d1cf-60702d77c60so1282740a12.3 for ; Wed, 04 Jun 2025 08:25:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050751; x=1749655551; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Nr/ud4zCPtVSNmlxUwtSLJlr6giftd88C51EN2S0gME=; b=RCTdkX5y6y61cZ1/PjbmEFR4csWju1gNFmE54iz2BB5eDX4D1FXMr/SI6PQCIdqxJT SF412z/fJheyqeizghdYJMKsUFjck4D4FnZcP3RsxgMBhqj6Xv3+B3YsZqY4Z5f7VCvt dCaOUZ1RHULFMxVzzZdGyVZpeBDyS/8WKsyCbSvn3I+BcnuhTL4ZOyuI6bcUc9tisMr3 GN/zEaRCE95NokJO0KeXqcha40ceRDbwyZZ96PlgXAVNIJqvKuoF9U/2KhmFQ/8MPj4w Cfp7bHxSJjsjDpX9RZE4sYF5lP3NcxrXZGnlfTubwqgchwTOWE/fheqU3wasEaCzZBCq AZjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050751; x=1749655551; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Nr/ud4zCPtVSNmlxUwtSLJlr6giftd88C51EN2S0gME=; b=Epxr7wiIw9KVP6IUUh1zYciMTF4IAGrXruyq9lB75RWh1f3bdHQlAYPMIeRCYu9ST1 NaBW0ZzmgpMGhX1KTglPDF+BAhCfFeUYx76v7bZduW5Dy8LpuayJglFEgKYkpyIIppe+ DXBNbdhaTmiUMnzE+eN4uUu25H0jieNLsIjEKwoXyOWO/qciOBcZ4eFiE+cZt0MDFQZG U5gZd4vvQ0PUZ/WHH4gyuKgO4MAG7bUvAqbMFdIg09KSFGWhT4aVifBn2o4FDnKjZaz3 GFlSClroQpuonjz0oWGtFNlGHvEWGk5HGX7dkiSs29HVGg6zHAB2X7G9FLi6LwFTQETE z3DQ== X-Forwarded-Encrypted: i=1; AJvYcCU5mK3Q78nEAdjJ8pwZVgyJN7mS5BkOwx2+PMns0QsKI1UyWT+OPx7Hvlx37RgaFeLX42cqywGU6UNwlN0=@vger.kernel.org X-Gm-Message-State: AOJu0YyLkljSHwLC6OEc+rB8P/OOjvMerSauA76UXUFIXWbkxDJqVQCu nFakyDu+E9QaGHSbZF9NU1+yaCh+6cGh5j51/kmtycM6jWdiJk285fvhuoH0MTtZRLw= X-Gm-Gg: ASbGncvknL15Ytp7qjTOzjWIiSA1V4XQWyQUO+xK0S3BDA2t3LEBkersYB46BVz78Mu 9NuAFopeglsZ/sFoqjkxROLNNjMKq2j90Y1zaTxaw8UttMrg+8qbiBkae2ry/GdJf2EkLIIHCcV jdNSoSPdFXDt/AuvWg1cO2OtGcoBK0KUduH0fetn1G8Ebym5Z7i4gPg01qneZYbDEmcA/zPSFr9 yQNeKbI/euzgErEA1lct3Lw0EcFN0iHPbTBGa/mLLDPf87wLRf8l/ONAlW4AHfHp1WxfNVtD0WG W7dJfuiFeYpKgilTGJ0SaM1i01mjf4ZJvx4AEHV2MBJ91/GUNWhhFFST1PD98+Ae4Dbr3HFs+ua HTDRO/k870RG/dwbZtSyn0I8zB/B7pgxqyIs= X-Google-Smtp-Source: AGHT+IFqvldrqbeuGwwG4MXV9h4Mso8s2QOVanNgW1TR6F0t21NbLRfi956cnkhEqPoH4VqrXxVIDA== X-Received: by 2002:a05:6402:40ca:b0:601:89d4:968e with SMTP id 4fb4d7f45d1cf-606f0ed4379mr2974440a12.27.1749050750975; Wed, 04 Jun 2025 08:25:50 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:50 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:49 +0100 Subject: [PATCH 10/17] regulator: s2mps11: use dev_err_probe() where appropriate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-10-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 dev_err_probe() exists to simplify code and harmonise error messages, there's no reason not to use it here. While at it, harmonise some error messages to add regulator name and ID like in other messages in this driver, and update messages to be more similar to other child-drivers of this PMIC (e.g. RTC). Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 29 ++++++++++++++--------------- 1 file changed, 14 insertions(+), 15 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 1f51fbc6c7b6e158f9707c04d9f030b9eee5e842..30586e9884bfb998ff07e314881= 3344b307506c0 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -1249,9 +1249,9 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) BUILD_BUG_ON(S2MPS_REGULATOR_MAX < ARRAY_SIZE(s2mpu05_regulators)); break; default: - dev_err(&pdev->dev, "Invalid device type: %u\n", - s2mps11->dev_type); - return -EINVAL; + return dev_err_probe(&pdev->dev, -ENODEV, + "Unsupported device type %d\n", + s2mps11->dev_type); } =20 s2mps11->ext_control_gpiod =3D devm_kcalloc(&pdev->dev, rdev_num, @@ -1290,21 +1290,20 @@ static int s2mps11_pmic_probe(struct platform_devic= e *pdev) devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod); regulator =3D devm_regulator_register(&pdev->dev, ®ulators[i], &config); - if (IS_ERR(regulator)) { - dev_err(&pdev->dev, "regulator init failed for %d\n", - i); - return PTR_ERR(regulator); - } + if (IS_ERR(regulator)) + return dev_err_probe(&pdev->dev, PTR_ERR(regulator), + "regulator init failed for %d/%s\n", + regulators[i].id, + regulators[i].name); =20 if (config.ena_gpiod) { ret =3D s2mps14_pmic_enable_ext_control(s2mps11, - regulator); - if (ret < 0) { - dev_err(&pdev->dev, - "failed to enable GPIO control over %s: %d\n", - regulator->desc->name, ret); - return ret; - } + regulator); + if (ret < 0) + return dev_err_probe(&pdev->dev, ret, + "failed to enable GPIO control over %d/%s\n", + regulator->desc->id, + regulator->desc->name); } } =20 --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f53.google.com (mail-ed1-f53.google.com [209.85.208.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B32E01A0BF1 for ; Wed, 4 Jun 2025 15:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050759; cv=none; b=E5+T8xtjUUzrvT11Dsn03Ftg49vYM4PMEivkQ5hbOgUcURhBK+CZjkA/ViUocTQTP0Da9QtQoDW7PdBl1jplAamnZJH9E5crWDtfiKGaKvSBZHDiwg2iHXsYYewcMShkLndecfOiReTcxdP/YjNNjQHwDfHX2n9hLgYWtriFqDY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050759; c=relaxed/simple; bh=lnf7SEVDxo8nwqagFSOE0flwSyB56hz5pHr1gz36EtA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=jSG8NWzQ9yRvGXvMKQ6Ztnnw5p2yRv43keXev7VQB/+Cxq2hFpPeY+ULu1mCSloVn+rUmdLODMyMsFyn7zswkbz6PF3Yjinp6aMJpEtITTpkVXx3SDE55mi8rnFOm3jqt+RfHrzCi8C1xyqJcJ8IixY4aGDvqw+We1ywv8thIt4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ya1/okbZ; arc=none smtp.client-ip=209.85.208.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ya1/okbZ" Received: by mail-ed1-f53.google.com with SMTP id 4fb4d7f45d1cf-602039559d8so13164960a12.1 for ; Wed, 04 Jun 2025 08:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050752; x=1749655552; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=38adGzUOIG34FHDZWkeIubpSpyQdC1frANBQcuzE93c=; b=ya1/okbZSAusMFUHDZMXTrDnzvX9hwD1lm9KJy3HetiEYsam4c5lZ/B1MVV4XRtZcu qa6Rrfb8D4jBXaLwubGTrj/A2CwRGFCqiIQgy8ES6T3H7R+KjQ25HaLhSfmQcuqLjJNM N07gs6rJ0KxzZY9KQk/Mwy143+pSps1PYF6F9NGF63JwpcxFkly3s4yRJQ4e5kqbPtvz K50DJYL6ayx2PANFDgTxiKoLjEjAzs4AX6hUdVjn1sUEYUmS3Ha1R9eEkzOZ0Z6icP6m ttjUhCTcc7tZiFmtZnWzDuIfzBWHKBU7V5zn3ogDLV/5pkSxzpdNgGyFCVMzoLbeuoDO ZzgQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050752; x=1749655552; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=38adGzUOIG34FHDZWkeIubpSpyQdC1frANBQcuzE93c=; b=cQrqXWEW9YYFEygFE6jUYZPeFzswy8BonFOYV2ENg+2z4MzwNY6KB2C0zO1PAjeZ9h LY7aljvWlkkmSuyNQxzSTmlHle5Wp38DB2Sb+XFHZAl1YE3GyFf7WGoj2pQ2gxzoJxOg jFKejWg3N/XY1bGh2xoDs/QpCK4+x1FGfuY/cA8SpYvnPK1dHHWYk74yteznLEw6v0NP uL0OdRZM/AVjpuFabML82UrxGouYPOB4wU/owJl7HS+4JpJiX9KHAWWXrpo55MOF8R3Z 0sqBmLbJsXZ09ZJiLPQ0r6507mIgB3T8LpbjQwgof6W5JjsohkM6R6p//oqf0oWF854L bhcA== X-Forwarded-Encrypted: i=1; AJvYcCWn7sqbx9mK30FKdIWdiM4DVirvyy8X+KbCjiRBC9SMETcPsUM7TIRTwqLOIL4FbuapRiNt4uYZUl8xPFg=@vger.kernel.org X-Gm-Message-State: AOJu0YzZlFkQ39HzarJSD+gaQH6zl7livPO7o1mw1BGSCMzBGbvCln7c Nnf74r0N9NJhQtns7x/LNkZCdpYKKZi4WjpSI74g8hCu6Jy8XKdu1eqy/lyxsF+jd9k= X-Gm-Gg: ASbGncurLCTGHGeeCCq9hXHFjSihStTvFzldlxHxFEWHHElzgofrvrgEY3MN23aAAd6 c94vukQW2zhcsS+dgSw5cjowsWCnBSShbDzFoJC67UcYW0RGEIV/DDcGoXsc+u4lS5CmeHn9Qms s2TomzhRYAJuUJ7MSICY2MyUS00JUIDf0Ty9WVCAlgegqrh4hqElBrQYy+gLxTXI8VotraIv2TQ gNnxmrZiEZoZNScNF+TMT37+f75XmZ6kkKhcq+VrDUvhPyColFANQ9flaUDOpJSHh0k1aPxOwaJ S6Vq2gf0Pn0DknbQz8MlZris7rBWiEZrmqz4tZ3SihHIxfbVnWNMwTbJjm6n3R+WYTfGCMiuGeR Z7Ocyr1p3uvoyxn8sJ/b7ZfnMj05o0MmuMfw= X-Google-Smtp-Source: AGHT+IHcuU+oqnxD9k5MrhyhDNTB0nxGiQIySmeHVPqdMikKo4QyRZSVRbG5YZsds1z4NiykU4LgMg== X-Received: by 2002:a05:6402:1e8f:b0:602:ef0a:cef8 with SMTP id 4fb4d7f45d1cf-606ea3b6b7emr3477295a12.18.1749050751682; Wed, 04 Jun 2025 08:25:51 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:51 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:50 +0100 Subject: [PATCH 11/17] regulator: s2mps11: update node parsing (allow -supply properties) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-11-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 For the upcoming S2MPG10 and S2MPG11 support, we need to be able to parse -supply properties in the PMIC's DT node. This currently doesn't work, because the code here currently points the regulator core at each individual regulator sub-node, and therefore the regulator core is unable to find the -supply properties. Update the code to simply let the regulator core handle all the parsing by adding the ::of_match and ::regulators_node members to all existing regulator descriptions, by adding ::of_parse_cb() to those regulators which support the vendor-specific samsung,ext-control-gpios to parse it (S2MPS14), and by dropping the explicit call to of_regulator_match(). Configuring the PMIC to respect the external control GPIOs via s2mps14_pmic_enable_ext_control() is left outside ::of_parse_cb() because the regulator core ignores errors other than -EPROBE_DEFER from that callback, while the code currently fails probe on register write errors and I believe it should stay that way. The driver can now avoid the devm_gpiod_unhinge() dance due to simpler error handling of GPIO descriptor acquisition. This change also has the advantage of reducing runtime memory consumption by quite a bit as the driver doesn't need to allocate a 'struct of_regulator_match' and a 'struct gpio_desc *' for each regulator for all PMICs as the regulator core does that. This saves 40+8 bytes on arm64 for each individual regulator on all supported PMICs (even on non-S2MPS14 due to currently unnecessarily allocating the extra memory unconditionally). With the upcoming S2MP10 and S2MPG11 support, this amounts to 1640+328 and 1120+224 bytes respectively. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 192 ++++++++++++++++++++++++----------------= ---- 1 file changed, 105 insertions(+), 87 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 30586e9884bfb998ff07e3148813344b307506c0..d3739526add3c966eb2979b9be2= e543b5ad9d89a 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -40,12 +40,6 @@ struct s2mps11_info { * the suspend mode was enabled. */ DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX); - - /* - * Array (size: number of regulators) with GPIO-s for external - * sleep control. - */ - struct gpio_desc **ext_control_gpiod; }; =20 static int get_ramp_delay(int ramp_delay) @@ -244,7 +238,7 @@ static int s2mps11_regulator_enable(struct regulator_de= v *rdev) case S2MPS14X: if (test_bit(rdev_id, s2mps11->suspend_state)) val =3D S2MPS14_ENABLE_SUSPEND; - else if (s2mps11->ext_control_gpiod[rdev_id]) + else if (rdev->ena_pin) val =3D S2MPS14_ENABLE_EXT_CONTROL; else val =3D rdev->desc->enable_mask; @@ -334,6 +328,58 @@ static int s2mps11_regulator_set_suspend_disable(struc= t regulator_dev *rdev) rdev->desc->enable_mask, state); } =20 +static int s2mps11_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + const struct s2mps11_info *s2mps11 =3D config->driver_data; + struct gpio_desc *ena_gpiod; + int ret; + + if (s2mps11->dev_type =3D=3D S2MPS14X) + switch (desc->id) { + case S2MPS14_LDO10: + case S2MPS14_LDO11: + case S2MPS14_LDO12: + break; + + default: + return 0; + } + else + return 0; + + ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), + "samsung,ext-control", 0, + GPIOD_OUT_HIGH | + GPIOD_FLAGS_BIT_NONEXCLUSIVE, + "s2mps11-regulator"); + if (IS_ERR(ena_gpiod)) { + ret =3D PTR_ERR(ena_gpiod); + + /* Ignore all errors except probe defer. */ + if (ret =3D=3D -EPROBE_DEFER) + return ret; + + if (ret =3D=3D -ENOENT) + dev_info(config->dev, + "No entry for control GPIO for %d/%s in node %pOF\n", + desc->id, desc->name, np); + else + dev_warn_probe(config->dev, ret, + "Failed to get control GPIO for %d/%s in node %pOF\n", + desc->id, desc->name, np); + return 0; + } + + dev_info(config->dev, "Using GPIO for ext-control over %d/%s\n", + desc->id, desc->name); + + config->ena_gpiod =3D ena_gpiod; + + return 0; +} + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -362,6 +408,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_ldo(num, step) { \ .name =3D "LDO"#num, \ .id =3D S2MPS11_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -378,6 +426,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck1_4(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS11_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -395,6 +445,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck5 { \ .name =3D "BUCK5", \ .id =3D S2MPS11_BUCK5, \ + .of_match =3D of_match_ptr("BUCK5"), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -412,6 +464,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck67810(num, min, step, min_sel, voltages= ) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS11_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -429,6 +483,8 @@ static const struct regulator_ops s2mps11_buck_ops =3D { #define regulator_desc_s2mps11_buck9 { \ .name =3D "BUCK9", \ .id =3D S2MPS11_BUCK9, \ + .of_match =3D of_match_ptr("BUCK9"), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps11_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -502,6 +558,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_ldo(num, min, step, min_sel) { \ .name =3D "LDO"#num, \ .id =3D S2MPS13_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -518,6 +576,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_buck(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS13_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -535,6 +595,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_buck7(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS13_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -552,6 +614,8 @@ static const struct regulator_ops s2mps14_reg_ops; #define regulator_desc_s2mps13_buck8_10(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS13_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -634,6 +698,9 @@ static const struct regulator_ops s2mps14_reg_ops =3D { #define regulator_desc_s2mps14_ldo(num, min, step) { \ .name =3D "LDO"#num, \ .id =3D S2MPS14_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mps11_of_parse_cb, \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -649,6 +716,9 @@ static const struct regulator_ops s2mps14_reg_ops =3D { #define regulator_desc_s2mps14_buck(num, min, step, min_sel) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS14_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mps11_of_parse_cb, \ .ops =3D &s2mps14_reg_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -725,6 +795,8 @@ static const struct regulator_ops s2mps15_reg_buck_ops = =3D { #define regulator_desc_s2mps15_ldo(num, range) { \ .name =3D "LDO"#num, \ .id =3D S2MPS15_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps15_reg_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -740,6 +812,8 @@ static const struct regulator_ops s2mps15_reg_buck_ops = =3D { #define regulator_desc_s2mps15_buck(num, range) { \ .name =3D "BUCK"#num, \ .id =3D S2MPS15_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mps15_reg_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -835,60 +909,6 @@ static int s2mps14_pmic_enable_ext_control(struct s2mp= s11_info *s2mps11, rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL); } =20 -static void s2mps14_pmic_dt_parse_ext_control_gpio(struct platform_device = *pdev, - struct of_regulator_match *rdata, struct s2mps11_info *s2mps11) -{ - struct gpio_desc **gpio =3D s2mps11->ext_control_gpiod; - unsigned int i; - unsigned int valid_regulators[3] =3D { S2MPS14_LDO10, S2MPS14_LDO11, - S2MPS14_LDO12 }; - - for (i =3D 0; i < ARRAY_SIZE(valid_regulators); i++) { - unsigned int reg =3D valid_regulators[i]; - - if (!rdata[reg].init_data || !rdata[reg].of_node) - continue; - - gpio[reg] =3D devm_fwnode_gpiod_get(&pdev->dev, - of_fwnode_handle(rdata[reg].of_node), - "samsung,ext-control", - GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, - "s2mps11-regulator"); - if (PTR_ERR(gpio[reg]) =3D=3D -ENOENT) - gpio[reg] =3D NULL; - else if (IS_ERR(gpio[reg])) { - dev_err(&pdev->dev, "Failed to get control GPIO for %d/%s\n", - reg, rdata[reg].name); - gpio[reg] =3D NULL; - continue; - } - if (gpio[reg]) - dev_dbg(&pdev->dev, "Using GPIO for ext-control over %d/%s\n", - reg, rdata[reg].name); - } -} - -static int s2mps11_pmic_dt_parse(struct platform_device *pdev, - struct of_regulator_match *rdata, struct s2mps11_info *s2mps11, - unsigned int rdev_num) -{ - struct device_node *reg_np; - - reg_np =3D of_get_child_by_name(pdev->dev.parent->of_node, "regulators"); - if (!reg_np) { - dev_err(&pdev->dev, "could not find regulators sub-node\n"); - return -EINVAL; - } - - of_regulator_match(&pdev->dev, reg_np, rdata, rdev_num); - if (s2mps11->dev_type =3D=3D S2MPS14X) - s2mps14_pmic_dt_parse_ext_control_gpio(pdev, rdata, s2mps11); - - of_node_put(reg_np); - - return 0; -} - static int s2mpu02_set_ramp_delay(struct regulator_dev *rdev, int ramp_del= ay) { unsigned int ramp_val, ramp_shift, ramp_reg; @@ -946,6 +966,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D { #define regulator_desc_s2mpu02_ldo1(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -961,6 +983,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D { #define regulator_desc_s2mpu02_ldo2(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -976,6 +1000,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D= { #define regulator_desc_s2mpu02_ldo3(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -991,6 +1017,8 @@ static const struct regulator_ops s2mpu02_buck_ops =3D= { #define regulator_desc_s2mpu02_ldo4(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1006,6 +1034,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_ldo5(num) { \ .name =3D "LDO"#num, \ .id =3D S2MPU02_LDO##num, \ + .of_match =3D of_match_ptr("LDO"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1022,6 +1052,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck1234(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1038,6 +1070,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck5(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1054,6 +1088,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck6(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1070,6 +1106,8 @@ static const struct regulator_ops s2mpu02_buck_ops = =3D { #define regulator_desc_s2mpu02_buck7(num) { \ .name =3D "BUCK"#num, \ .id =3D S2MPU02_BUCK##num, \ + .of_match =3D of_match_ptr("BUCK"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1125,6 +1163,8 @@ static const struct regulator_desc s2mpu02_regulators= [] =3D { #define regulator_desc_s2mpu05_ldo_reg(num, min, step, reg) { \ .name =3D "ldo"#num, \ .id =3D S2MPU05_LDO##num, \ + .of_match =3D of_match_ptr("ldo"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_ldo_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1156,6 +1196,8 @@ static const struct regulator_desc s2mpu02_regulators= [] =3D { #define regulator_desc_s2mpu05_buck(num, which) { \ .name =3D "buck"#num, \ .id =3D S2MPU05_BUCK##num, \ + .of_match =3D of_match_ptr("buck"#num), \ + .regulators_node =3D of_match_ptr("regulators"), \ .ops =3D &s2mpu02_buck_ops, \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ @@ -1254,22 +1296,7 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) s2mps11->dev_type); } =20 - s2mps11->ext_control_gpiod =3D devm_kcalloc(&pdev->dev, rdev_num, - sizeof(*s2mps11->ext_control_gpiod), GFP_KERNEL); - if (!s2mps11->ext_control_gpiod) - return -ENOMEM; - - struct of_regulator_match *rdata __free(kfree) =3D - kcalloc(rdev_num, sizeof(*rdata), GFP_KERNEL); - if (!rdata) - return -ENOMEM; - - for (i =3D 0; i < rdev_num; i++) - rdata[i].name =3D regulators[i].name; - - ret =3D s2mps11_pmic_dt_parse(pdev, rdata, s2mps11, rdev_num); - if (ret) - return ret; + device_set_of_node_from_dev(&pdev->dev, pdev->dev.parent); =20 platform_set_drvdata(pdev, s2mps11); =20 @@ -1279,15 +1306,6 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) for (i =3D 0; i < rdev_num; i++) { struct regulator_dev *regulator; =20 - config.init_data =3D rdata[i].init_data; - config.of_node =3D rdata[i].of_node; - config.ena_gpiod =3D s2mps11->ext_control_gpiod[i]; - /* - * Hand the GPIO descriptor management over to the regulator - * core, remove it from devres management. - */ - if (config.ena_gpiod) - devm_gpiod_unhinge(&pdev->dev, config.ena_gpiod); regulator =3D devm_regulator_register(&pdev->dev, ®ulators[i], &config); if (IS_ERR(regulator)) @@ -1296,7 +1314,7 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) regulators[i].id, regulators[i].name); =20 - if (config.ena_gpiod) { + if (regulator->ena_pin) { ret =3D s2mps14_pmic_enable_ext_control(s2mps11, regulator); if (ret < 0) --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 042F51CB518 for ; Wed, 4 Jun 2025 15:25:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050759; cv=none; b=ROXc0YQRpLAPbqp5VaJzYb88UOg5blsZNTZ7jFt+6TUfanerx5Y1IuY8tgg6zSkCOqH6fGhydydPb63LO+zyM9WUfrQK7Sux0X1SzA6+aHpuby+z7GbOmIIulKiMONTgWzIfHLfd5uvp4y/MPbRI7rfuctMTYoDfTUFL39MMpA0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050759; c=relaxed/simple; bh=gpRe8Mt5ndzq0RKdCAcP7CMV+rBpHJ84dXjPHbGOCWM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=KouNmJZ6dtbCv1xtV1WA2clWSNtgheqDI0q+g88yIfr0CKAokPR/0bRoZodUI3Mms401AgMNAXBclLJHEjCVtLwtLjn+0jzoqgbD/fffTRDW1kzxgJ/ooqFzozxsV4ttNc4I3XYOEWShKNcaWiQ7rth9l0a6+qUBPq0T5HzXdrw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=JWyNo4QV; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="JWyNo4QV" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-606bbe60c01so3622913a12.2 for ; Wed, 04 Jun 2025 08:25:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050752; x=1749655552; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pP407Ox1v91FomL1iN4XwON2iK1j8Ht0T+AJfPsmGsI=; b=JWyNo4QVZIiV/llCGZCM/mgWS16dQa+u5O0J+eiD3dCtp+m7GzBDEQvyLhqG+2YydU /QyvammoVG7aUvB4VKOSk5vEKxU6GMTYB8umvneqZvV7RdnEYNWNHWnBlO3xmIeTGZbO RQbVOnvW6MK0Vi756tSP0vBj3UsGVLmCrOn1DtIkgCH7V/Oz1aUmOCEuqZWNizxDHAYy qUYINT5xs1BEQDBLrsWe9txed0Kz6oZJNOYEU/eMOP5Rs5vLlAeaYYObfkRN5OHURJz7 jASrHNvktcVd/LSzifi/hm9jt1Dm+eVaGg1z4o4kWF/qxhUx8MCWhfm+WaYMhNTA+hbz 6L1w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050752; x=1749655552; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pP407Ox1v91FomL1iN4XwON2iK1j8Ht0T+AJfPsmGsI=; b=CYOmyznhLXUrcwbhXXyolnlbtqduFU55XetS3MQMI6rHT0baUrnJtCb/UvCMY13CGl wCS+zFxusu13MDHzU5RnRZdTvjTqLB4qFFsR9B3Pls6ytA04FC0xassBVD1d3nr6wx3V GruXDc5uHupZNplda0VpxcGtrektZplJ/BfxOm4iCMETcks9AJSA6JPAspHGuVW7ITPr YWF19NBNtIhNEwxTOhio/qV4uF5bJQpivFjoKKFejma3x+osMMc0LB6O4k3264P5/D31 EO/WUxkMFKIl/ySxDfOQMR2vv9H/wJ9P53xGlqurlUNl/fdcpTaJye4W8ItQFFfiIQQR JXRw== X-Forwarded-Encrypted: i=1; AJvYcCXPOMajALurZNFRrOwq8anUGwGPb8MlHKD0jPer/hxfhFSIMWVgjg4D6lxXMOflBFKsyYnmVLibLRm2oK4=@vger.kernel.org X-Gm-Message-State: AOJu0YyKffaTdBTnkGqZXryLQ9c2Ssrizv2GP8VpelpVbCz7sCgsOKPd Lwd4Eo2cGzF5iFOqsDjNDYC9g2r6RVPGklGnMhGY0pHnNfT/af1cWyv8/kMRXZKAee8= X-Gm-Gg: ASbGncuU3sPjkr00mtbPUMkXWAPIAyro7EzIX3tecT7KmgBIQOjHrQ+Y7esD8XRLcl6 yoOR3EKTAfF2hxBEcIt1HBqjP+ZZZFv637LtGAKQ99/7p1AForRyiok2gohvBWLn91hmzVfFCTi pSZa8iqS/6mF6t7BKaluybMgH+KtUNS44fjWkM+ocjxAlSxpa0f4KT2qXZAQ3LTlm4uTdPtGe1F QFxBlex45Wk9iwrgGYhIsASsE5nSHhl90chAg3Bp5Lj0DNHx4QtNPPM0YJqp4ADvgFOecbd1iMp DrQe7csjSF/swc31K/fgOnuijslDJYSOaT+NwAgTzrEh1fFOrJZn/1J1wQHdZMUzA1Uvu0/ml0e V9nMe7Y97pfM51EfYSA2ugmWOQIeSGY4bkA8= X-Google-Smtp-Source: AGHT+IFc62NxQDrp6Fd0aN6PA4dvCy44jt7oi4p68WSn0L0ytJoyIqbFgJ8vuOoNN2SWezfzZwIZWQ== X-Received: by 2002:a05:6402:2789:b0:602:1b8b:2902 with SMTP id 4fb4d7f45d1cf-606e941b388mr3458933a12.15.1749050752175; Wed, 04 Jun 2025 08:25:52 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:51 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:51 +0100 Subject: [PATCH 12/17] regulator: s2mps11: refactor handling of external rail control Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-12-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Refactor s2mps14_pmic_enable_ext_control() and s2mps11_of_parse_cb() slightly as a preparation for adding S2MPG10 and S2MPG11 support, as both of those PMICs also support control of rails via GPIOs. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 86 ++++++++++++++++++++++++++++++-----------= ---- 1 file changed, 57 insertions(+), 29 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index d3739526add3c966eb2979b9be2e543b5ad9d89a..ff9124c998c685d9c598570148d= ca074e671a99b 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -328,27 +328,13 @@ static int s2mps11_regulator_set_suspend_disable(stru= ct regulator_dev *rdev) rdev->desc->enable_mask, state); } =20 -static int s2mps11_of_parse_cb(struct device_node *np, - const struct regulator_desc *desc, - struct regulator_config *config) +static int s2mps11_of_parse_gpiod(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) { - const struct s2mps11_info *s2mps11 =3D config->driver_data; struct gpio_desc *ena_gpiod; int ret; =20 - if (s2mps11->dev_type =3D=3D S2MPS14X) - switch (desc->id) { - case S2MPS14_LDO10: - case S2MPS14_LDO11: - case S2MPS14_LDO12: - break; - - default: - return 0; - } - else - return 0; - ena_gpiod =3D fwnode_gpiod_get_index(of_fwnode_handle(np), "samsung,ext-control", 0, GPIOD_OUT_HIGH | @@ -380,6 +366,28 @@ static int s2mps11_of_parse_cb(struct device_node *np, return 0; } =20 +static int s2mps11_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + const struct s2mps11_info *s2mps11 =3D config->driver_data; + + if (s2mps11->dev_type =3D=3D S2MPS14X) + switch (desc->id) { + case S2MPS14_LDO10: + case S2MPS14_LDO11: + case S2MPS14_LDO12: + break; + + default: + return 0; + } + else + return 0; + + return s2mps11_of_parse_gpiod(np, desc, config); +} + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -903,10 +911,16 @@ static const struct regulator_desc s2mps15_regulators= [] =3D { }; =20 static int s2mps14_pmic_enable_ext_control(struct s2mps11_info *s2mps11, - struct regulator_dev *rdev) + struct regulator_dev *rdev) { - return regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, - rdev->desc->enable_mask, S2MPS14_ENABLE_EXT_CONTROL); + int ret =3D regmap_update_bits(rdev->regmap, rdev->desc->enable_reg, + rdev->desc->enable_mask, + S2MPS14_ENABLE_EXT_CONTROL); + if (ret < 0) + return dev_err_probe(rdev_get_dev(rdev), ret, + "failed to enable GPIO control over %d/%s\n", + rdev->desc->id, rdev->desc->name); + return 0; } =20 static int s2mpu02_set_ramp_delay(struct regulator_dev *rdev, int ramp_del= ay) @@ -1244,6 +1258,26 @@ static const struct regulator_desc s2mpu05_regulator= s[] =3D { regulator_desc_s2mpu05_buck45(5), }; =20 +static int s2mps11_handle_ext_control(struct s2mps11_info *s2mps11, + struct regulator_dev *rdev) +{ + int ret; + + switch (s2mps11->dev_type) { + case S2MPS14X: + if (!rdev->ena_pin) + return 0; + + ret =3D s2mps14_pmic_enable_ext_control(s2mps11, rdev); + break; + + default: + return 0; + } + + return ret; +} + static int s2mps11_pmic_probe(struct platform_device *pdev) { struct sec_pmic_dev *iodev =3D dev_get_drvdata(pdev->dev.parent); @@ -1314,15 +1348,9 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) regulators[i].id, regulators[i].name); =20 - if (regulator->ena_pin) { - ret =3D s2mps14_pmic_enable_ext_control(s2mps11, - regulator); - if (ret < 0) - return dev_err_probe(&pdev->dev, ret, - "failed to enable GPIO control over %d/%s\n", - regulator->desc->id, - regulator->desc->name); - } + ret =3D s2mps11_handle_ext_control(s2mps11, regulator); + if (ret < 0) + return ret; } =20 return 0; --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 24E981D5175 for ; Wed, 4 Jun 2025 15:25:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050760; cv=none; b=c8wNYxLdpaq0l93FjijIJ3ZpRB2COjl+pkVeKoSiRMQvjZW6krIT32/8oSzyXqCcx2hJGW2ZeEgD64DPlfwKQHlfqnZjwxQhovo/v0aQs6C1ZQG4KPgih/F0sf1oEHQZBfsST8auEgXj5Th4zSSvxrjRufNeCJR15jALrRlt1N4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050760; c=relaxed/simple; bh=89g6kCobF3HR6J6w5n/pC7Io3EZ/ilt2DgZlXtsx9ns=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qZGyL/pbm/bx9TYEHB16o8E0ocWOB3FnZBciXbEmWKFXoSG2msZrujN1COdFijdhJe1EuyVH003rWqiW19QoJWwiH8EhZChNKAS+LICRUV12p1MAkwAMSrsJP+H0PfvdHza75S/bPZwh2ZiTkIdurpHPo+VHPaarEcXoW3v5j7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=ezlajlm8; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="ezlajlm8" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-604f26055c6so2214510a12.1 for ; Wed, 04 Jun 2025 08:25:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050753; x=1749655553; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=IEGYDV2khNy4gA3s7OfWJd0YI0OOgwREUGVpObDem1A=; b=ezlajlm8vAdIPoYtIbuJqPue5w7aApxzV8LNf0JL4qA+sOuot5gcCDLrzcltngfT7W Oj33GBD54oVWcE+1To4vBAxma6BcMVbQFuITMbawym4Uv5LemVFWVVnYApQ0/Mk7Wbkh nFjXtwh6YKexAgEO50zJlRigv5/x+g+cnwqdSjUdFjrOIf5NgPn84bC1bAe2W0XJxakw NkkE1CfXgao3dKs85WUnFGDD9nu4K8D4WYarEkTXjAddvRq/81+lYPPh8ZbdmsSgtGU6 VZhTgw8gtqLpWmjXQO+J5dolmfPuEsvX1FcziHtVwh42JdDL1nyvlVFVuOe1uFtBTz0R 4mkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050753; x=1749655553; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=IEGYDV2khNy4gA3s7OfWJd0YI0OOgwREUGVpObDem1A=; b=IrixNyudhqE3nowEd5ENSJ4u+yHdvWE8mkiFf/8imbcKq13Vh+hUJKtGiDebl6zZ4/ Gv0TPqGIGwWOz3LohfHwyo9s4TtVoa1LkHTmU5uU4c2IuWfmVaUFPl+PotdpsCNAb8/z 0FGqm/HSpU/kxIiLxi7fLQwqhJqcatfvwyuPojxi/AzprcVLm8tFDWg6Fq/lbphlOBB3 LaRLXExnTYlxoqD2Vs0MU498BcX5Ys+K+YeapHrgH9mjAwmfpUGhFt8Snnsv2OBpYIZq xhVYTNyiDITgiJNLwhtE37wWGbxGkJfOkF54IO+xMk644kHQS4A0XWtZvjvxlVaN+lS0 mrxQ== X-Forwarded-Encrypted: i=1; AJvYcCUdK3VlcHFiw/l0xoShVHmuTNHZZ/PIqZJCAd5ee4ZYwt6Lek3bYCPR68kKfGRKlXSQknxvuzoVCQ22vrc=@vger.kernel.org X-Gm-Message-State: AOJu0YwTPbHUxMecyBGCSoGPlJSuabSrqKn+dilziN8njOVg6KdEosvj G6Ac3oKnjXtmCQMYzeZW2eMLAgmrogEGlbOFSotkDP50bFN1+jHQ/mDXc6GzdrDfi+U= X-Gm-Gg: ASbGnctdRL3HuCyDMpEq7hcAWs4sHAHJM1WtJSP9vmHlnfQI3bLuwCmOUfOmb10fPNt Q6T5e9FP+RjyJPcjfkd6QdTrLuGrxRpuTNhY1zIgJxJcRViov0Bm45hvzbVEJnDd+W5pLHHhFnH oxxfRjw8LteAzXcEURlKn6xmxCPHSfFrT6EYI8lM7IQ8bOGQkg3a+GBq/kBHjtoNgm3cs/kvdXu SI0hMhEqD/AkZNWfkaSnJZ5XTQEpjiLABunXp39Y0LNPKNU66cbWOc94lmUZCtwmCck0bCMjdJI 85p+bAWAHyAbRwS2ooRI09r+Vu64Zkb2npjbNRS4m3nAfCm4qMTEFgko2UFKLRN4ge+5FxNDxw4 G1Rk9fuIy36guKEQJXZD9e7g2n+nnTPf/ICw= X-Google-Smtp-Source: AGHT+IF4GtmRZR1zAYaVAYqk931R2ALis05PVJfS7nUbUxre+k8POSxyxX9zkmikgkd1i/jh5IT9Ng== X-Received: by 2002:a05:6402:2351:b0:607:1ebd:da75 with SMTP id 4fb4d7f45d1cf-6071ebdda91mr338186a12.15.1749050752754; Wed, 04 Jun 2025 08:25:52 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:52 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:52 +0100 Subject: [PATCH 13/17] regulator: s2mps11: add S2MPG10 regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-13-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG10 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, power meters, RTC, clock outputs, and additional GPIOs interfaces. It has 10 buck and 31 LDO rails. Several of these can either be controlled via software or via external signals, e.g. input pins connected to a main processor's GPIO pins. This commit implements support for these rails. Additional data needs to be stored for each regulator, e.g. the input pin for external control, or a rail-specific ramp-rate for when enabling a buck-rail. Therefore, probe() is updated slightly to make that possible. The rails are instantiated as separate driver instances for bucks and LDOs, because S2MPG10 is typically used with an S2MPG11 sub-PMIC where some bucks of one typically supply at least some of the LDOs of the other. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 561 ++++++++++++++++++++++++++++++++= +++- include/linux/mfd/samsung/s2mpg10.h | 3 + 2 files changed, 561 insertions(+), 3 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index ff9124c998c685d9c598570148dca074e671a99b..6fe6787044c40216f7a03551199= 81b74a8f56e58 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -3,6 +3,7 @@ // Copyright (c) 2012-2014 Samsung Electronics Co., Ltd // http://www.samsung.com =20 +#include #include #include #include @@ -16,6 +17,7 @@ #include #include #include +#include #include #include #include @@ -42,6 +44,21 @@ struct s2mps11_info { DECLARE_BITMAP(suspend_state, S2MPS_REGULATOR_MAX); }; =20 +#define to_s2mpg10_regulator_desc(x) container_of((x), struct s2mpg10_regu= lator_desc, desc) + +struct s2mpg10_regulator_desc { + struct regulator_desc desc; + + /* Ramp rate during enable, valid for bucks only. */ + unsigned int enable_ramp_rate; + + /* Registers for external control of rail. */ + unsigned int pctrlsel_reg; + unsigned int pctrlsel_mask; + /* Populated from DT. */ + unsigned int pctrlsel_val; +}; + static int get_ramp_delay(int ramp_delay) { unsigned char cnt =3D 0; @@ -388,6 +405,492 @@ static int s2mps11_of_parse_cb(struct device_node *np, return s2mps11_of_parse_gpiod(np, desc, config); } =20 +static int s2mpg10_of_parse_cb(struct device_node *np, + const struct regulator_desc *desc, + struct regulator_config *config) +{ + const struct s2mps11_info *s2mps11 =3D config->driver_data; + struct s2mpg10_regulator_desc *s2mpg10_desc =3D to_s2mpg10_regulator_desc= (desc); + u32 ext_control; + + if (s2mps11->dev_type !=3D S2MPG10) + return 0; + + if (of_property_read_u32(np, "samsung,ext-control", &ext_control)) + return 0; + + switch (s2mps11->dev_type) { + case S2MPG10: + switch (desc->id) { + case S2MPG10_BUCK1 ... S2MPG10_BUCK7: + case S2MPG10_BUCK10: + case S2MPG10_LDO3 ... S2MPG10_LDO19: + if (ext_control > S2MPG10_PCTRLSEL_TCXO_ON2) + return -EINVAL; + break; + + case S2MPG10_LDO20: + if (ext_control > S2MPG10_PCTRLSEL_LDO20M_OFF) + return -EINVAL; + break; + + default: + return -EINVAL; + } + break; + + default: + return -EINVAL; + } + + /* + * If the regulator should be configured for external control, then: + * 1) the PCTRLSELx register needs to be set accordingly + * 2) regulator_desc::enable_val needs to be: + * a) updated and + * b) written to the hardware + * 3) we switch to the ::ops that don't provide ::enable() and + * ::disable() implementations + * + * Points 1) and 2b) will be handled in _probe(), after + * devm_regulator_register() returns, so that we can properly act on + * failures, since the regulator core ignores most return values from + * this parse callback. + */ + s2mpg10_desc->pctrlsel_val =3D ext_control; + s2mpg10_desc->pctrlsel_val <<=3D (ffs(s2mpg10_desc->pctrlsel_mask) - 1); + + s2mpg10_desc->desc.enable_val =3D S2MPG10_PMIC_CTRL_ENABLE_EXT; + s2mpg10_desc->desc.enable_val <<=3D (ffs(desc->enable_mask) - 1); + + ++s2mpg10_desc->desc.ops; + + return s2mps11_of_parse_gpiod(np, desc, config); +} + +static int s2mpg10_enable_ext_control(struct s2mps11_info *s2mps11, + struct regulator_dev *rdev) +{ + const struct s2mpg10_regulator_desc *s2mpg10_desc; + int ret; + + switch (s2mps11->dev_type) { + case S2MPG10: + s2mpg10_desc =3D to_s2mpg10_regulator_desc(rdev->desc); + break; + + default: + return 0; + } + + ret =3D regmap_update_bits(rdev_get_regmap(rdev), + s2mpg10_desc->pctrlsel_reg, + s2mpg10_desc->pctrlsel_mask, + s2mpg10_desc->pctrlsel_val); + if (ret) + return dev_err_probe(rdev_get_dev(rdev), ret, + "failed to configure pctrlsel for %s\n", + rdev->desc->name); + + ret =3D regulator_enable_regmap(rdev); + if (ret) + return dev_err_probe(rdev_get_dev(rdev), ret, + "failed to enable regulator %s\n", + rdev->desc->name); + + return 0; +} + +/* ops for regulators without ramp control */ +static const struct regulator_ops s2mpg10_reg_ldo_ops[] =3D { + { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + }, { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + } +}; + +/* ops for regulators that have ramp control */ +static const struct regulator_ops s2mpg10_reg_ldo_ramp_ops[] =3D { + { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + }, { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + } +}; + +static int s2mpg10_regulator_buck_enable_time(struct regulator_dev *rdev) +{ + const struct s2mpg10_regulator_desc * const s2mpg10_desc =3D + to_s2mpg10_regulator_desc(rdev->desc); + const struct regulator_ops * const ops =3D rdev->desc->ops; + int vsel, curr_uV; + + vsel =3D ops->get_voltage_sel(rdev); + if (vsel < 0) + return vsel; + + curr_uV =3D ops->list_voltage(rdev, vsel); + if (curr_uV < 0) + return curr_uV; + + return (rdev->desc->enable_time + + DIV_ROUND_UP(curr_uV, s2mpg10_desc->enable_ramp_rate)); +} + +static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV) +{ + unsigned int ramp_reg, ramp_sel, ramp_rate; + int ret; + + if (old_uV =3D=3D new_uV) + return 0; + + ramp_reg =3D rdev->desc->ramp_reg; + if (old_uV > new_uV) + /* The downwards ramp is at a different offset. */ + ramp_reg +=3D S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1; + + ret =3D regmap_read(rdev->regmap, ramp_reg, &ramp_sel); + if (ret) + return ret; + + ramp_sel &=3D rdev->desc->ramp_mask; + ramp_sel >>=3D ffs(rdev->desc->ramp_mask) - 1; + if (ramp_sel >=3D rdev->desc->n_ramp_values || + !rdev->desc->ramp_delay_table) + return -EINVAL; + + ramp_rate =3D rdev->desc->ramp_delay_table[ramp_sel]; + + return DIV_ROUND_UP(abs(new_uV - old_uV), ramp_rate); +} + +/* + * We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), beca= use + * only if the latter is !=3D NULL, the regulator core will call neither d= uring + * DVS if the regulator is disabled. If the latter is NULL, the core always + * calls the ::set_voltage_time() callback, which would give incorrect res= ults + * if the regulator is off. + * At the same time, we do need ::set_voltage_time() due to differing upwa= rds + * and downwards ramps and we can not make that code dependent on the regu= lator + * enable state, as that would break regulator_set_voltage_time() which + * expects a correct result no matter the enable state. + */ +static const struct regulator_ops s2mpg10_reg_buck_ops[] =3D { + { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .enable_time =3D s2mpg10_regulator_buck_enable_time, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg10_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + }, { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg10_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + } +}; + +#define regulator_desc_s2mpg10_ldo_cmn(_num, _supply, _ops, _vrange, \ + _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz) { \ + .name =3D "ldo"#_num"m", \ + .supply_name =3D _supply, \ + .of_match =3D of_match_ptr("ldo"#_num"m"), \ + .regulators_node =3D of_match_ptr("regulators"), \ + .of_parse_cb =3D s2mpg10_of_parse_cb, \ + .id =3D S2MPG10_LDO##_num, \ + .ops =3D &_ops[0], \ + .type =3D REGULATOR_VOLTAGE, \ + .owner =3D THIS_MODULE, \ + .linear_ranges =3D _vrange, \ + .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ + .n_voltages =3D _vrange##_count, \ + .vsel_reg =3D S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \ + .vsel_mask =3D _vsel_mask, \ + .enable_reg =3D S2MPG10_PMIC_##_en_reg, \ + .enable_mask =3D _en_mask, \ + .ramp_delay =3D _ramp_delay, \ + .ramp_reg =3D _r_reg, \ + .ramp_mask =3D _r_mask, \ + .ramp_delay_table =3D _r_table, \ + .n_ramp_values =3D _r_table_sz, \ + .enable_time =3D 130, /* startup 20+-10 + ramp 30..100=CE=BCs */ \ +} + +#define s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _vrange, _ops, \ + _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \ + _pc_reg, _pc_mask) \ + { \ + .desc =3D regulator_desc_s2mpg10_ldo_cmn(_num, _supply, \ + _ops, \ + _vrange, _vsel_reg_sfx, _vsel_mask, \ + _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, \ + _r_table_sz), \ + .pctrlsel_reg =3D _pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +/* standard LDO via LxM_CTRL */ +#define s2mpg10_regulator_desc_ldo(_num, _supply, _vrange) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + s2mpg10_reg_ldo_ops, CTRL, GENMASK(5, 0), \ + L##_num##M_CTRL, BIT(7), \ + 0, 0, 0, NULL, 0, \ + 0, 0) \ + +/* standard LDO via LxM_CTRL but non-standard vsel mask */ +#define s2mpg10_regulator_desc_ldo_vmsk(_num, _supply, _vrange, \ + _vsel_mask) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + s2mpg10_reg_ldo_ops, CTRL, _vsel_mask, \ + L##_num##M_CTRL, BIT(7), \ + 0, 0, 0, NULL, 0, \ + 0, 0) + +/* standard LDO but possibly GPIO controlled */ +#define s2mpg10_regulator_desc_ldo_gpio(_num, _supply, _vrange, \ + _pc_reg, _pc_mask) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + s2mpg10_reg_ldo_ops, CTRL, GENMASK(5, 0), \ + L##_num##M_CTRL, GENMASK(7, 6), \ + 0, 0, 0, NULL, 0, \ + S2MPG10_PMIC_##_pc_reg, _pc_mask) + +/* LDO with ramp support and possibly GPIO controlled */ +#define s2mpg10_regulator_desc_ldo_ramp(_num, _supply, _vrange, \ + _en_mask, _r_reg_sfx, _pc_reg, _pc_mask) \ + s2mpg10_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + s2mpg10_reg_ldo_ramp_ops, CTRL1, GENMASK(6, 0), \ + LDO_CTRL2, _en_mask, \ + 6250, S2MPG10_PMIC_##_r_reg_sfx, GENMASK(1, 0), \ + s2mpg10_ldo_ramp_table, \ + ARRAY_SIZE(s2mpg10_ldo_ramp_table), \ + S2MPG10_PMIC_##_pc_reg, _pc_mask) + +#define s2mpg10_buck_to_ramp_mask(n) (GENMASK(1, 0) << (((n) % 4) * 2)) + +/* + * The ramp_delay during enable is fixed (12.5mV/=CE=BCs), while the ramp = during + * DVS can be adjusted. Linux can adjust the ramp delay via DT, in which c= ase + * the regulator core will modify the regulator's constraints and call our + * .set_ramp_delay() which updates the DVS ramp in ramp_reg. + * For enable, our .enable_time() unconditionally uses enable_ramp_rate + * (12.5mV/=CE=BCs) while our ::set_voltage_time() takes the value in ramp= _reg + * into account. + */ +#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) { \ + .name =3D "buck"#_num"m", \ + .supply_name =3D "vinb"#_num"m", \ + .of_match =3D of_match_ptr("buck"#_num"m"), \ + .of_parse_cb =3D s2mpg10_of_parse_cb, \ + .regulators_node =3D of_match_ptr("regulators"), \ + .id =3D S2MPG10_BUCK##_num, \ + .ops =3D &s2mpg10_reg_buck_ops[0], \ + .type =3D REGULATOR_VOLTAGE, \ + .owner =3D THIS_MODULE, \ + .linear_ranges =3D _vrange, \ + .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ + .n_voltages =3D _vrange##_count, \ + .vsel_reg =3D S2MPG10_PMIC_B##_num##M_OUT1, \ + .vsel_mask =3D 0xff, \ + .enable_reg =3D S2MPG10_PMIC_B##_num##M_CTRL, \ + .enable_mask =3D GENMASK(7, 6), \ + .ramp_reg =3D S2MPG10_PMIC_##_r_reg, \ + .ramp_mask =3D s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \ + - S2MPG10_BUCK1), \ + .ramp_delay_table =3D s2mpg10_buck_ramp_table, \ + .n_ramp_values =3D ARRAY_SIZE(s2mpg10_buck_ramp_table), \ + .enable_time =3D 30, /* + V/enable_ramp_rate */ \ +} + +#define s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg) \ + .desc =3D regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg), \ + .enable_ramp_rate =3D 12500 + +#define s2mpg10_regulator_desc_buck_gpio(_num, _vrange, _r_reg, \ + _pc_reg, _pc_mask) \ + { \ + s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg), \ + .pctrlsel_reg =3D S2MPG10_PMIC_##_pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +#define s2mpg10_regulator_desc_buck(_num, _vrange, _r_reg) \ + { \ + s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg), \ + } + +#define S2MPG10_VOLTAGE_RANGE(_prefix, _idx, _start_uV, _min_uV, \ + _max_uV, _step_uV) \ +static const struct linear_range _prefix##_vranges##_idx[] =3D { \ + REGULATOR_LINEAR_RANGE(_min_uV, \ + ((_min_uV) - (_start_uV)) / (_step_uV), \ + ((_max_uV) - (_start_uV)) / (_step_uV), \ + _step_uV) \ +}; \ +static const unsigned int _prefix##_vranges##_idx##_count =3D \ + ((((_max_uV) - (_start_uV)) / (_step_uV)) + 1) + +/* voltage range for s2mpg10 LDO 1, 11, 12 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 1, 300000, 700000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 2, 4, 9, 14, 18, 19, 20, 23, 25, 29, 30, = 31 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 2, 700000, 1600000, 1950000, STEP_25_MV= ); + +/* voltage range for s2mpg10 LDO 3, 5, 6, 8, 16, 17, 24, 28 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 3, 725000, 725000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 7 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 7, 300000, 450000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 13, 15 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 13, 300000, 450000, 950000, STEP_12_5_M= V); + +/* voltage range for s2mpg10 LDO 10 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 10, 1800000, 1800000, 3350000, STEP_25_= MV); + +/* voltage range for s2mpg10 LDO 21, 22, 26, 27 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_ldo, 21, 1800000, 2500000, 3300000, STEP_25_= MV); + +/* possible ramp values for s2mpg10 LDO 11, 12, 13, 15 */ +static const unsigned int s2mpg10_ldo_ramp_table[] =3D { + STEP_6_25_MV, STEP_12_5_MV +}; + +/* voltage range for s2mpg10 BUCK 1, 2, 3, 4, 5, 7, 8, 9, 10 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_buck, 1, 200000, 450000, 1300000, STEP_6_25_= MV); + +/* voltage range for s2mpg10 BUCK 6 */ +S2MPG10_VOLTAGE_RANGE(s2mpg10_buck, 6, 200000, 450000, 1350000, STEP_6_25_= MV); + +static const unsigned int s2mpg10_buck_ramp_table[] =3D { + STEP_6_25_MV, STEP_12_5_MV, STEP_25_MV +}; + +static const struct s2mpg10_regulator_desc s2mpg10_regulators_ldos[] =3D { + s2mpg10_regulator_desc_ldo_vmsk(1, "vinl3m", s2mpg10_ldo_vranges1, + GENMASK(6, 0)), + s2mpg10_regulator_desc_ldo(2, "vinl9m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo_gpio(3, "vinl4m", s2mpg10_ldo_vranges3, + PCTRLSEL5, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(4, "vinl9m", s2mpg10_ldo_vranges2, + PCTRLSEL5, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(5, "vinl3m", s2mpg10_ldo_vranges3, + PCTRLSEL6, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(6, "vinl7m", s2mpg10_ldo_vranges3, + PCTRLSEL6, GENMASK(7, 4)), + /* + * Possibly GPIO controlled, but non-standard (greater) V-range and + * enable reg & mask. + */ + s2mpg10_regulator_desc_ldo_cmn(7, "vinl3m", s2mpg10_ldo_vranges7, + s2mpg10_reg_ldo_ops, + CTRL, GENMASK(6, 0), + LDO_CTRL1, GENMASK(4, 3), + 0, 0, 0, NULL, 0, + S2MPG10_PMIC_PCTRLSEL7, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(8, "vinl4m", s2mpg10_ldo_vranges3, + PCTRLSEL7, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(9, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL8, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(10, "vinl15m", s2mpg10_ldo_vranges10, + PCTRLSEL8, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_ramp(11, "vinl7m", s2mpg10_ldo_vranges1, + GENMASK(1, 0), DVS_SYNC_CTRL3, + PCTRLSEL9, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_ramp(12, "vinl8m", s2mpg10_ldo_vranges1, + GENMASK(3, 2), DVS_SYNC_CTRL4, + PCTRLSEL9, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_ramp(13, "vinl1m", s2mpg10_ldo_vranges13, + GENMASK(5, 4), DVS_SYNC_CTRL5, + PCTRLSEL10, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(14, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL10, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_ramp(15, "vinl2m", s2mpg10_ldo_vranges13, + GENMASK(7, 6), DVS_SYNC_CTRL6, + PCTRLSEL11, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(16, "vinl5m", s2mpg10_ldo_vranges3, + PCTRLSEL11, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(17, "vinl6m", s2mpg10_ldo_vranges3, + PCTRLSEL12, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(18, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL12, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo_gpio(19, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL13, GENMASK(3, 0)), + s2mpg10_regulator_desc_ldo_gpio(20, "vinl10m", s2mpg10_ldo_vranges2, + PCTRLSEL13, GENMASK(7, 4)), + s2mpg10_regulator_desc_ldo(21, "vinl14m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(22, "vinl15m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(23, "vinl11m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(24, "vinl7m", s2mpg10_ldo_vranges3), + s2mpg10_regulator_desc_ldo(25, "vinl10m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(26, "vinl15m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(27, "vinl15m", s2mpg10_ldo_vranges21), + s2mpg10_regulator_desc_ldo(28, "vinl7m", s2mpg10_ldo_vranges3), + s2mpg10_regulator_desc_ldo(29, "vinl12m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(30, "vinl13m", s2mpg10_ldo_vranges2), + s2mpg10_regulator_desc_ldo(31, "vinl11m", s2mpg10_ldo_vranges2) +}; + +static const struct s2mpg10_regulator_desc s2mpg10_regulators_bucks[] =3D { + s2mpg10_regulator_desc_buck_gpio(1, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL1, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck_gpio(2, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL1, GENMASK(7, 4)), + s2mpg10_regulator_desc_buck_gpio(3, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL2, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck_gpio(4, s2mpg10_buck_vranges1, DVS_RAMP1, + PCTRLSEL2, GENMASK(7, 4)), + s2mpg10_regulator_desc_buck_gpio(5, s2mpg10_buck_vranges1, DVS_RAMP2, + PCTRLSEL3, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck_gpio(6, s2mpg10_buck_vranges6, DVS_RAMP2, + PCTRLSEL3, GENMASK(7, 4)), + s2mpg10_regulator_desc_buck_gpio(7, s2mpg10_buck_vranges1, DVS_RAMP2, + PCTRLSEL4, GENMASK(3, 0)), + s2mpg10_regulator_desc_buck(8, s2mpg10_buck_vranges1, DVS_RAMP2), + s2mpg10_regulator_desc_buck(9, s2mpg10_buck_vranges1, DVS_RAMP3), + s2mpg10_regulator_desc_buck_gpio(10, s2mpg10_buck_vranges1, DVS_RAMP3, + PCTRLSEL4, GENMASK(7, 4)) +}; + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -1271,6 +1774,18 @@ static int s2mps11_handle_ext_control(struct s2mps11= _info *s2mps11, ret =3D s2mps14_pmic_enable_ext_control(s2mps11, rdev); break; =20 + case S2MPG10: + /* + * If desc.enable_val is !=3D 0, then external control was + * requested. We can not test s2mpg10_desc::ext_control, + * because 0 is a valid value. + */ + if (!rdev->desc->enable_val) + return 0; + + ret =3D s2mpg10_enable_ext_control(s2mps11, rdev); + break; + default: return 0; } @@ -1286,6 +1801,7 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) unsigned int rdev_num; int i, ret; const struct regulator_desc *regulators; + const struct s2mpg10_regulator_desc *s2mpg10_regulators =3D NULL; =20 s2mps11 =3D devm_kzalloc(&pdev->dev, sizeof(struct s2mps11_info), GFP_KERNEL); @@ -1294,6 +1810,30 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) =20 s2mps11->dev_type =3D platform_get_device_id(pdev)->driver_data; switch (s2mps11->dev_type) { + case S2MPG10: + /* + * Add 1, because our core driver subtracted 1 via + * devm_mfd_add_devices(). + */ + switch (pdev->id + 1) { + case S2MPG10_REGULATOR_CELL_ID_BUCKS: + rdev_num =3D ARRAY_SIZE(s2mpg10_regulators_bucks); + s2mpg10_regulators =3D s2mpg10_regulators_bucks; + break; + case S2MPG10_REGULATOR_CELL_ID_LDOS: + rdev_num =3D ARRAY_SIZE(s2mpg10_regulators_ldos); + s2mpg10_regulators =3D s2mpg10_regulators_ldos; + break; + default: + return -EINVAL; + } + /* + * Can not use ARRAY_SIZE() here, as it doesn't reflect the + * highest regulator id. + */ + BUILD_BUG_ON((enum s2mpg10_regulators) S2MPS_REGULATOR_MAX < + S2MPG10_REGULATOR_MAX); + break; case S2MPS11X: rdev_num =3D ARRAY_SIZE(s2mps11_regulators); regulators =3D s2mps11_regulators; @@ -1339,14 +1879,28 @@ static int s2mps11_pmic_probe(struct platform_devic= e *pdev) config.driver_data =3D s2mps11; for (i =3D 0; i < rdev_num; i++) { struct regulator_dev *regulator; + const struct regulator_desc *rdesc =3D ®ulators[i]; + + if (s2mpg10_regulators) { + struct s2mpg10_regulator_desc *s2mpg10_desc; + + + s2mpg10_desc =3D devm_kmemdup(&pdev->dev, + &s2mpg10_regulators[i], + sizeof(*s2mpg10_desc), + GFP_KERNEL); + if (!s2mpg10_desc) + return -ENOMEM; + + rdesc =3D &s2mpg10_desc->desc; + } =20 regulator =3D devm_regulator_register(&pdev->dev, - ®ulators[i], &config); + rdesc, &config); if (IS_ERR(regulator)) return dev_err_probe(&pdev->dev, PTR_ERR(regulator), "regulator init failed for %d/%s\n", - regulators[i].id, - regulators[i].name); + rdesc->id, rdesc->name); =20 ret =3D s2mps11_handle_ext_control(s2mps11, regulator); if (ret < 0) @@ -1357,6 +1911,7 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) } =20 static const struct platform_device_id s2mps11_pmic_id[] =3D { + { "s2mpg10-regulator", S2MPG10}, { "s2mps11-regulator", S2MPS11X}, { "s2mps13-regulator", S2MPS13X}, { "s2mps14-regulator", S2MPS14X}, diff --git a/include/linux/mfd/samsung/s2mpg10.h b/include/linux/mfd/samsun= g/s2mpg10.h index 3e8bc65078472518c5e77f8bd199ee403eda18ea..f2e2c7923ad8116816ff5cae3b0= c0eb98af2e42b 100644 --- a/include/linux/mfd/samsung/s2mpg10.h +++ b/include/linux/mfd/samsung/s2mpg10.h @@ -295,6 +295,9 @@ enum s2mpg10_pmic_reg { S2MPG10_PMIC_LDO_SENSE4, }; =20 +/* rail controlled externally, based on PCTRLSELx */ +#define S2MPG10_PMIC_CTRL_ENABLE_EXT BIT(0) + /* Meter registers (type 0xa00) */ enum s2mpg10_meter_reg { S2MPG10_METER_CTRL1, --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f44.google.com (mail-ed1-f44.google.com [209.85.208.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 403F01DDA2D for ; Wed, 4 Jun 2025 15:25:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050759; cv=none; b=O01bBpwEfgCVIRcGVkcFxO7CYnwmjD+X69W6DNMea6ocnQ+ALVHdU6hLjb57u/PwgZEQUlUfU5cU3eFS15VxdF4TBKRxl1UiASXfd93/BYIfHNGlFFuka9Cv7bsbU0YUzJgsMKPV2Yg/YIedxhi4a991MhL+D2kseJt307x43Ls= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050759; c=relaxed/simple; bh=xiw3+9QQT1R6rACHzAcfRAzeIULsoWcavNAe3lOvbNo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=LqSUnT4ToM9KBtBvsaIP2aPCtSVcT7b4zcRY2FMt913bieFEOQHwRIWik+xUzLP8KRDuzuRp4wsB7k1dP44wokWoGIheASxQQ+AQIcbKUCk7N34mIqtX+e84y0yL3qPB9o9KSdH4Mc8NWw6e/bLmfEOWwTgGBhf8wBrWQEKgOWA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=WMK8MFW/; arc=none smtp.client-ip=209.85.208.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WMK8MFW/" Received: by mail-ed1-f44.google.com with SMTP id 4fb4d7f45d1cf-60462e180e2so3104266a12.2 for ; Wed, 04 Jun 2025 08:25:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050753; x=1749655553; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=bqcmeBNmmkfD7/7jkYs7xVbtGf9PYopW68JKLRAxWfQ=; b=WMK8MFW/jB1UTk5SjsLI8Pnx5mlvvop51NaNR4erhtjqe/Jln5vG1fHsZPybL3arIi 8nMVbNBbJobJebxhxDzshVLVxLW7FxPsP/q4Ju/JJ9LEyTOgvzeN+nRxWLpm6O5BrWiB a786fS7jh6DHr4RE38zKFzVSlcDbnIY5hsMUhNvGJ+DOuGaJmcMuFnVekAHfKjKVvgRu v++2ywKlQWUlmgRb1CAlPLQptYaO7ct+3cQGviIMcyWkAvM2UxWwZ2UxjgEV53Nr5NKT L73Am5YQ27wD7PunsyxnnZCQ1wKprAX4XOc5xykIjA52XeiTtgkDGnYs9lKikTlrIhBu MDcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050753; x=1749655553; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bqcmeBNmmkfD7/7jkYs7xVbtGf9PYopW68JKLRAxWfQ=; b=f16ESy1D/myug+X745ttoons91XT32jjp90EazyP9BRmJzAXmevKtOP74zTAr/rCEb c20odx83mi4OSt0fAysDYdJNQcRswIjOKazqUxM6dz7RSmMqpSQiO8Lnpdns02H2GFkS poC+59M2UWIK9wsYVDxFRLlerYvhO2lKiAwLG4qLlJ8q8nSSxYHtlfEIY4zj0fZj6II0 +G6vNL1tTP9lUTMlj5/wnBMN2DoIfUdFPgDTMIChuvjfmWWwKGH5oV6XKGOAbY2KtjLH 5Pn7UxuGPM0gbt0s59V7mpaX8eilpiSRmlmt3eijQAzPnBOoaz56AQ4hwGo/tGCAX7x4 EILA== X-Forwarded-Encrypted: i=1; AJvYcCWPrvgLQmy59hfdhP+K9h96+73EkxdthcfTZdZ3KYw4XGXojEqS7VkE83BNSQxNpCXTxu2xRhF6qC9WNnk=@vger.kernel.org X-Gm-Message-State: AOJu0YyeJNO39Rq0Y3XUgNLKQqOgaqSq6JbHdWh1JNtNakv/b5XdDegC JiKwTQJeVOtQmDG5vUVC2TR/wjxudZxKSjimN4vio0rQ54hIVrMcQy0XPvLenTl4TRc= X-Gm-Gg: ASbGncs6QX3KXQ15RmWWIKRTn9xRH7EwMOWKHa/jJJZm+53UPfTUgRf9htfHUi4+saE 8TPsF/DJ8UhOmi5ZhUuYdTlUMGHqizj9y88KzvHam/qpyfIsxvHOEfz1FLnct/ZS1n/9qM7X3oK EmKphHv2VmGN0ooYzvRaN7Hxhyv9sfsBuIhE5HaZsYJ1yxzT2tbEYCnRVqUKDlJT3Kgrh55h4EM Q1rLuFoS+Wn0bZPp702vY0Zo3iOR2DdMUbED6LSaoA+XE9JVWePgA6mLh2aiM1jIfmS7+f/rkQ0 qE4rJ4EBDoy5PFSezqK9C6E/WQDORErnTwOvkLmxkXg79GDuH79ueRrufJAMb15tGoz1jQBOu3V usbi6Z8dxZN5iGNfD9H3zvOG/pBKwlXPhkOs= X-Google-Smtp-Source: AGHT+IGtfaNvbOgLxL63zDuI4O0A+DETos0BCLMRQDwmpSXX87hd3C1qMtwAXr3zW2EH0X8wSGXcrg== X-Received: by 2002:a05:6402:2547:b0:604:c4fc:70c with SMTP id 4fb4d7f45d1cf-606ea5bd9c5mr3000623a12.31.1749050753425; Wed, 04 Jun 2025 08:25:53 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:52 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:53 +0100 Subject: [PATCH 14/17] regulator: s2mps11: refactor S2MPG10 ::set_voltage_time() for S2MPG11 reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-14-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The upcoming S2MPG11 support needs a similar, but different version of ::set_voltage_time(). For S2MPG10, the downwards and upwards ramps for a rail are at different offsets at the same bit positions, while for S2MPG11 the ramps are at the same offset at different bit positions. Refactor the existing version slightly to allow reuse. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 32 ++++++++++++++++++++++---------- 1 file changed, 22 insertions(+), 10 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 6fe6787044c40216f7a0355119981b74a8f56e58..f427895637a32f26e2960ce7c78= 79632f0bc2dcb 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -562,26 +562,23 @@ static int s2mpg10_regulator_buck_enable_time(struct = regulator_dev *rdev) + DIV_ROUND_UP(curr_uV, s2mpg10_desc->enable_ramp_rate)); } =20 -static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, - int old_uV, int new_uV) +static int s2mpg1x_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV, + unsigned int ramp_reg, + unsigned int ramp_mask) { - unsigned int ramp_reg, ramp_sel, ramp_rate; + unsigned int ramp_sel, ramp_rate; int ret; =20 if (old_uV =3D=3D new_uV) return 0; =20 - ramp_reg =3D rdev->desc->ramp_reg; - if (old_uV > new_uV) - /* The downwards ramp is at a different offset. */ - ramp_reg +=3D S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1; - ret =3D regmap_read(rdev->regmap, ramp_reg, &ramp_sel); if (ret) return ret; =20 - ramp_sel &=3D rdev->desc->ramp_mask; - ramp_sel >>=3D ffs(rdev->desc->ramp_mask) - 1; + ramp_sel &=3D ramp_mask; + ramp_sel >>=3D ffs(ramp_mask) - 1; if (ramp_sel >=3D rdev->desc->n_ramp_values || !rdev->desc->ramp_delay_table) return -EINVAL; @@ -591,6 +588,21 @@ static int s2mpg10_regulator_buck_set_voltage_time(str= uct regulator_dev *rdev, return DIV_ROUND_UP(abs(new_uV - old_uV), ramp_rate); } =20 +static int s2mpg10_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV) +{ + unsigned int ramp_reg; + + ramp_reg =3D rdev->desc->ramp_reg; + if (old_uV > new_uV) + /* The downwards ramp is at a different offset. */ + ramp_reg +=3D S2MPG10_PMIC_DVS_RAMP4 - S2MPG10_PMIC_DVS_RAMP1; + + return s2mpg1x_regulator_buck_set_voltage_time(rdev, old_uV, new_uV, + ramp_reg, + rdev->desc->ramp_mask); +} + /* * We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), beca= use * only if the latter is !=3D NULL, the regulator core will call neither d= uring --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f43.google.com (mail-ed1-f43.google.com [209.85.208.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6A49B1DDC04 for ; Wed, 4 Jun 2025 15:25:56 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.43 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050760; cv=none; b=eTUUxHumY/VZIjXYC/baV2Pimyy0iLr3Dc4nUKdDpEggoYPxmyH2Xi0qumgNqA/Fxm5nj+1s+RcqAF7+lgv0iR88dXKgado8J/R0GWvogBBBNccu3lWtWs1bUYyeCxkxMccouYRnf5tq9BaBFtV6I/CuYC4h2DLhaFfDLZQWNQ8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050760; c=relaxed/simple; bh=A/GHEuztfmgd1/p5cSNEjJ3+xiiEy5QUpmdgAvLhvKg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=k2oXavDcOvZQfxrUd6t9FreXdmc5KuI4rCstfoPkffMgtGj1+QQz5utiC2+BS6KkMNoaFkCz9e21pHNnzluD+Fa9gStfn35jBUp4Vxk1q23IBPP6i/vtHbPH/E3ROLS0yRMpS4TET8x3OHl7Q/I4Cw3iJk9kU1l871hs2QXE6uQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=SNm6Nlnz; arc=none smtp.client-ip=209.85.208.43 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="SNm6Nlnz" Received: by mail-ed1-f43.google.com with SMTP id 4fb4d7f45d1cf-604e745b6fbso13679546a12.2 for ; Wed, 04 Jun 2025 08:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050754; x=1749655554; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=vn2J3nnAxbZSYZ0Pl0MdJxpTvr8+PeUSA3EZa6924LA=; b=SNm6NlnzXNYUNidt32Y7GsuhNDSoLhlaTthVWBGNAAJiNY4b+ZLm45lEUGzcoYXv8z vBsQKoZ1SB6oJ8mKoYC1vBpEj4DfBcpn62ltdHBvVwk5CAVmcV5RWoA4vDCLUtRz6rtY nXT5ZemHlcSsoYl09iU92xrozxJKs2F6EZzASxOhUTOsN4nreyDekTrRTZDzN/w7/bLB 0v/RY3uzHB4Oira2qJ4AR7bkQbqjhsEjpsPaYq0gKXA/ht80YAhc8LGm1bAI4wev2RRM 7e6O5ELVT6itTJ2dPubcNb2ShC4fIXzeADTMBp4dZLz9GGmzxX7FuMVJ5DRx0J3yCWPz MFHw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050754; x=1749655554; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=vn2J3nnAxbZSYZ0Pl0MdJxpTvr8+PeUSA3EZa6924LA=; b=OQBmSXUt1s7ICi97luCAV7vpbwA2oFUJs7L+Sq94abcGfqeFruZvdfSADl2H4eV22p WUNhnqfWYZ8dq2Nbnaa2JJzfMfarO++NIB2YPsYjBUPbWnNMWIy7GKGXT6hvEMYC4IyQ ErRC+W+25mDUB8S4/QYTOaRx4vm1XSMYhU7+3j+n/OgZZKfAYjQuaMWdtt2XOnDlECAY xOKMfhftvDsWehbLexgnpQLbizdaKjOiVOBwmpMBkcJX1h1olWpIuuNJZo6+t3xCr+7n 7xyPh8FZYP/8vCa+YSPpKCnB0XEtmMayDtivBUfIQOrrs0ExevcW5aW6DYLEVJ6scBey OYDg== X-Forwarded-Encrypted: i=1; AJvYcCW8KY7Gmn/6OeobQcri/tBiiJZ9paj78YxsXl4coYNWqRj34LUUWa3A0qBUnyq958MH1kD0gCpRQ3ZBlE8=@vger.kernel.org X-Gm-Message-State: AOJu0YzFJnAZ9ildAqU33bjqF0ooyh2L+Y0+C6w7WQjkZtQ3NYuxcLzk MLZvrWhGUzEJko6eEn445dMoPY9hDAfYGiI8+zarGeD4Qas6VCo/msSFvQPqPBf/bVs= X-Gm-Gg: ASbGncuD7T1rAQOGnNalQ2JteWWkzIozCP1X+8bp+IpMv8ESSHO1YOKaQQf5BxLpDAZ ueAIXQDbDk1HyCSxLNl+6lqX6ne8TcEePtqfmakhTYc1Hvx0gFwUZL4g1De6MPCvlvyqq4jSnlW EEkLltMHfd+/mf7XqdcGKT5c1+5vMMusluYT/hT/k7ZpMw0OY5eVaEdeIyBEDL88eSCnfLAZk1n k1IRz91cX4dS7faJ3+EzycAWsB4hRoN43o3QEru9OL50tiJpJdmIEx4ui7ys3c9vrXEo2kR/HmW hHQ+k3SzRksBBV7H8a/jQZCPwq21X9bYKm/368xFGNC+YLRPQ0yRQV5btv7MxWDQTp9+CJjS5Fw esNl3TqBnBYxeVsF8NmiyD+1LCjRDf6OpfN8= X-Google-Smtp-Source: AGHT+IGETXau/Hs1twpCO4F6DmcKfpU3VQ25hwN+cddBXzSz725FYngJL1uteD+Puz581oTrnBSHGg== X-Received: by 2002:a05:6402:5c9:b0:5fc:9979:78f7 with SMTP id 4fb4d7f45d1cf-606f0b66b7bmr2628868a12.14.1749050754080; Wed, 04 Jun 2025 08:25:54 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:53 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:54 +0100 Subject: [PATCH 15/17] regulator: s2mps11: refactor S2MPG10 regulator macros for S2MPG11 reuse Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-15-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Rails in the S2MPG11 share a very similar set of properties with S2MP10 with slight differences. Update the existing macros to allow reuse by the upcoming S2MPG11 driver. Signed-off-by: Andr=C3=A9 Draszik --- Note: checkpatch complains about unused macro arguments _r_mask, _r_table, and _r_table_sz, but these are false-positives due to patch context. --- drivers/regulator/s2mps11.c | 70 ++++++++++++++++++++++++++++-------------= ---- 1 file changed, 43 insertions(+), 27 deletions(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index f427895637a32f26e2960ce7c7879632f0bc2dcb..74f09b949ca7d6f1d61decd0864= 80996fd444dbd 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -638,24 +638,24 @@ static const struct regulator_ops s2mpg10_reg_buck_op= s[] =3D { } }; =20 -#define regulator_desc_s2mpg10_ldo_cmn(_num, _supply, _ops, _vrange, \ - _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ +#define regulator_desc_s2mpg1x_ldo_cmn(_name, _id, _supply, _ops, \ + _vrange, _vsel_reg, _vsel_mask, _en_reg, _en_mask, \ _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz) { \ - .name =3D "ldo"#_num"m", \ + .name =3D "ldo"_name, \ .supply_name =3D _supply, \ - .of_match =3D of_match_ptr("ldo"#_num"m"), \ + .of_match =3D of_match_ptr("ldo"_name), \ .regulators_node =3D of_match_ptr("regulators"), \ .of_parse_cb =3D s2mpg10_of_parse_cb, \ - .id =3D S2MPG10_LDO##_num, \ + .id =3D _id, \ .ops =3D &_ops[0], \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ .linear_ranges =3D _vrange, \ .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ .n_voltages =3D _vrange##_count, \ - .vsel_reg =3D S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \ + .vsel_reg =3D _vsel_reg, \ .vsel_mask =3D _vsel_mask, \ - .enable_reg =3D S2MPG10_PMIC_##_en_reg, \ + .enable_reg =3D _en_reg, \ .enable_mask =3D _en_mask, \ .ramp_delay =3D _ramp_delay, \ .ramp_reg =3D _r_reg, \ @@ -670,10 +670,12 @@ static const struct regulator_ops s2mpg10_reg_buck_op= s[] =3D { _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \ _pc_reg, _pc_mask) \ { \ - .desc =3D regulator_desc_s2mpg10_ldo_cmn(_num, _supply, \ - _ops, \ - _vrange, _vsel_reg_sfx, _vsel_mask, \ - _en_reg, _en_mask, \ + .desc =3D regulator_desc_s2mpg1x_ldo_cmn(#_num"m", \ + S2MPG10_LDO##_num, _supply, _ops, \ + _vrange, \ + S2MPG10_PMIC_L##_num##M_##_vsel_reg_sfx, \ + _vsel_mask, \ + S2MPG10_PMIC_##_en_reg, _en_mask, \ _ramp_delay, _r_reg, _r_mask, _r_table, \ _r_table_sz), \ .pctrlsel_reg =3D _pc_reg, \ @@ -728,31 +730,45 @@ static const struct regulator_ops s2mpg10_reg_buck_op= s[] =3D { * (12.5mV/=CE=BCs) while our ::set_voltage_time() takes the value in ramp= _reg * into account. */ -#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) { \ - .name =3D "buck"#_num"m", \ - .supply_name =3D "vinb"#_num"m", \ - .of_match =3D of_match_ptr("buck"#_num"m"), \ +#define regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, _ops, \ + _vrange, _vsel_reg, _vsel_mask, _en_reg, _en_mask, \ + _r_reg, _r_mask, _r_table, _r_table_sz, \ + _en_time) { \ + .name =3D "buck"_name, \ + .supply_name =3D _supply, \ + .of_match =3D of_match_ptr("buck"_name), \ .of_parse_cb =3D s2mpg10_of_parse_cb, \ .regulators_node =3D of_match_ptr("regulators"), \ - .id =3D S2MPG10_BUCK##_num, \ - .ops =3D &s2mpg10_reg_buck_ops[0], \ + .of_parse_cb =3D s2mpg10_of_parse_cb, \ + .id =3D _id, \ + .ops =3D &_ops[0], \ .type =3D REGULATOR_VOLTAGE, \ .owner =3D THIS_MODULE, \ .linear_ranges =3D _vrange, \ .n_linear_ranges =3D ARRAY_SIZE(_vrange), \ .n_voltages =3D _vrange##_count, \ - .vsel_reg =3D S2MPG10_PMIC_B##_num##M_OUT1, \ - .vsel_mask =3D 0xff, \ - .enable_reg =3D S2MPG10_PMIC_B##_num##M_CTRL, \ - .enable_mask =3D GENMASK(7, 6), \ - .ramp_reg =3D S2MPG10_PMIC_##_r_reg, \ - .ramp_mask =3D s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \ - - S2MPG10_BUCK1), \ - .ramp_delay_table =3D s2mpg10_buck_ramp_table, \ - .n_ramp_values =3D ARRAY_SIZE(s2mpg10_buck_ramp_table), \ - .enable_time =3D 30, /* + V/enable_ramp_rate */ \ + .vsel_reg =3D _vsel_reg, \ + .vsel_mask =3D _vsel_mask, \ + .enable_reg =3D _en_reg, \ + .enable_mask =3D _en_mask, \ + .ramp_reg =3D _r_reg, \ + .ramp_mask =3D _r_mask, \ + .ramp_delay_table =3D _r_table, \ + .n_ramp_values =3D _r_table_sz, \ + .enable_time =3D _en_time, /* + V/enable_ramp_rate */ \ } =20 +#define regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg) \ + regulator_desc_s2mpg1x_buck_cmn(#_num"m", S2MPG10_BUCK##_num, \ + "vinb"#_num"m", s2mpg10_reg_buck_ops, _vrange, \ + S2MPG10_PMIC_B##_num##M_OUT1, GENMASK(7, 0), \ + S2MPG10_PMIC_B##_num##M_CTRL, GENMASK(7, 6), \ + S2MPG10_PMIC_##_r_reg, \ + s2mpg10_buck_to_ramp_mask(S2MPG10_BUCK##_num \ + - S2MPG10_BUCK1), \ + s2mpg10_buck_ramp_table, \ + ARRAY_SIZE(s2mpg10_buck_ramp_table), 30) + #define s2mpg10_regulator_desc_buck_cm(_num, _vrange, _r_reg) \ .desc =3D regulator_desc_s2mpg10_buck(_num, _vrange, _r_reg), \ .enable_ramp_rate =3D 12500 --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f54.google.com (mail-ed1-f54.google.com [209.85.208.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5BD081DE3B5 for ; Wed, 4 Jun 2025 15:25:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050761; cv=none; b=CUU2VzDyn5aNVF409ZOLB9WeR5rUwhqNqRHcCeSBjTgPHBQBJzSqmyK5OVs4m93rynGGPhJ7KN0YPdgqD81Im0ujWGx53YjXJYbE2ZdEpseOuePtCJusQjzHUK931hxG03Z7qWyRjgfHSs/7nngEyH0QYC+Hc6vYCTiCWYvAGzo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050761; c=relaxed/simple; bh=S58osScf9m+EZHP6ZPFv6S9jPWquICjN+2mKXJ7uBec=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GOU25A/75XArSGLBkKJ7/jSEibXD6OkRnu3s9HqdZOfjc2OoeQW3LzyrrEt57dFaFHlA5Cy6erU6igpZBOAJKA8HCIgr2SQnLlrWEXCX0ufq0C5+3t+DxqIAXTnCUHGyvctxDhBnA6X+7x52jrPdMI+TqjB+cmkpduwkyNcb0NY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=QYXbmF/V; arc=none smtp.client-ip=209.85.208.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="QYXbmF/V" Received: by mail-ed1-f54.google.com with SMTP id 4fb4d7f45d1cf-605b9488c28so8177576a12.2 for ; Wed, 04 Jun 2025 08:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050755; x=1749655555; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=7B0+Nwu/HOkqYpijxQs4Jzs+csQzmp8Gn5FLuXG11/I=; b=QYXbmF/VacG/6FgIsHsRfmjYL1ZGXi+lZU1KrZLBK4FC1kjZkRhG22WV+qeoytDOo7 rIgy1QMdypbG5+pj2dj0wODYQPuQXkS/d8phJzzMTjV9cDIpn62JcU8qChRhyeKWm2xy e8zx0GXcRWi96FtrOiipwru07Iu7WrnpHUuAy/HaLRGHlnbzVzFFChyqvP5Irx+7kFGM nJBkTXupD973Oo30U+7JgnuupVZveSirabPK+3bjBuQPoCH+fZPnZahqVBZ59aR6phbA dW4C0TgwvaZ7Lq1gsHlWfAfYw1FeGVJnmIwWFIS8JYOGaSAQaHyFtkl0k4YGRZLltifW Dv3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050755; x=1749655555; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=7B0+Nwu/HOkqYpijxQs4Jzs+csQzmp8Gn5FLuXG11/I=; b=TQjTKWf4swigqaSElcw3Q63XDQ0YI/as6xJ26O+cpMdecNh8gngiOwFVOkc5B6EYqf u2hgnxTLjQQGbDDPdB83hVFU+skesi4yw5LLxt8Loe8oAX+DCJ4WxsbyOreFRgA0HZn4 yt6wyhdDjMSamtVpFYNXm8XE1PId5fxcWMMAK251BA+nn/ldu9L3bVzyUff5h9B9ZlRN tBvXsmS2xv1rVyLFb9gLqR2eIPfEG+d0bD3KVW5UVBGL6smqZTLPCW82jzoqt6Lb1zzf yusenHPJPaW2cJQbPE5P9tZ2ueAhSuxP9xAhQPPck+ELsQ+0gQiPf3qAR/3ol7cw7V9V XteQ== X-Forwarded-Encrypted: i=1; AJvYcCVwJtL7YSZ8Xl+G1j03kQnM59AYYq3AkyCMC4cg1fbKEJj/r3vV8Xuc7crEjOMNzA37Kcs2b6Fncmvb3XY=@vger.kernel.org X-Gm-Message-State: AOJu0Yyyr0CH5Djb8j6cTNMe73X2TIYfg4ltuOBrP5ODPT3ztap9PEpF GxRvRuX+TXBs7hqsB2MztJDBfQ7yEsqYePmeRqu8YPZ/eggnzRN2G8JB5BCX5q3Rc/s= X-Gm-Gg: ASbGncu0JyqZ1aYgpRni0rC2Yv+EqzdG/xbS3EtyUkzLNZ6pe4DzCqnAuIWz0mNxq7y 1IvT3x4tnAME8EF/V1CzxIJG9GGgBpWNl61bDozPldBfvTezCHhP4UNe1I/W2XZVjj0Ym/dxY8F Y1t2b8ydHdliVxooXg12TQD1QfjbBEFvHkj3AUv7wsuOvIP2V+s3u0Z9jesQxeY4NQilJ/qLClt e/swaS/ojSDGZY3DMSanQwO78COGz70vaRFeRo1TO+Dam0WDSF1nmXkuH4/mw0ynxOPJUZuFv/y ppUikVCpXKU8Gg99HBMAqyz0gkJ6GK0h8h+qqxKJqHgg9KllN6X7ywPixeEOdZ38Q4ub/XlShQW JGAwQ7E0PrjxKr6iTIqAvkI9aTww+1iSLETiMiKn9U5ejgTmZDt11HoT5 X-Google-Smtp-Source: AGHT+IFnvxqBiHW9G1Ii6JI98RPKz5RCaegMjvcGQbieSyHuvx0T2tzr+X2hIiYnkirxUQ7UEIZKZA== X-Received: by 2002:a05:6402:280d:b0:607:116e:108d with SMTP id 4fb4d7f45d1cf-607116e12b9mr912806a12.21.1749050754729; Wed, 04 Jun 2025 08:25:54 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:54 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:55 +0100 Subject: [PATCH 16/17] regulator: s2mps11: add S2MPG11 regulator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-16-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 The S2MPG10 PMIC is a Power Management IC for mobile applications with buck converters, various LDOs, and power meters. It typically complements an S2MPG10 PMIC in a main/sub configuration as the sub-PMIC. It has 12 buck, 1 buck-boost, and 15 LDO rails. Several of these can either be controlled via software or via external signals, e.g. input pins connected to a main processor's GPIO pins. This commit implements support for these rails. The rails are instantiated as separate driver instances for bucks and LDOs, because S2MPG11 is typically used with an S2MPG10 main-PMIC where some bucks of one typically supply at least some of the LDOs of the other. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 301 ++++++++++++++++++++++++++++++++++++++++= +++- 1 file changed, 300 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 74f09b949ca7d6f1d61decd086480996fd444dbd..3b5f6f2f2b11be81f27bc39d5d4= 8005da4afeace 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -18,6 +18,7 @@ #include #include #include +#include #include #include #include @@ -413,7 +414,7 @@ static int s2mpg10_of_parse_cb(struct device_node *np, struct s2mpg10_regulator_desc *s2mpg10_desc =3D to_s2mpg10_regulator_desc= (desc); u32 ext_control; =20 - if (s2mps11->dev_type !=3D S2MPG10) + if (s2mps11->dev_type !=3D S2MPG10 && s2mps11->dev_type !=3D S2MPG11) return 0; =20 if (of_property_read_u32(np, "samsung,ext-control", &ext_control)) @@ -439,6 +440,27 @@ static int s2mpg10_of_parse_cb(struct device_node *np, } break; =20 + case S2MPG11: + switch (desc->id) { + case S2MPG11_BUCK1 ... S2MPG11_BUCK3: + case S2MPG11_BUCK5: + case S2MPG11_BUCK8: + case S2MPG11_BUCK9: + case S2MPG11_BUCKD: + case S2MPG11_BUCKA: + case S2MPG10_LDO1: + case S2MPG10_LDO2: + case S2MPG10_LDO8: + case S2MPG10_LDO13: + if (ext_control > S2MPG11_PCTRLSEL_LDO13S_EN) + return -EINVAL; + break; + + default: + return -EINVAL; + } + break; + default: return -EINVAL; } @@ -476,6 +498,7 @@ static int s2mpg10_enable_ext_control(struct s2mps11_in= fo *s2mps11, =20 switch (s2mps11->dev_type) { case S2MPG10: + case S2MPG11: s2mpg10_desc =3D to_s2mpg10_regulator_desc(rdev->desc); break; =20 @@ -603,6 +626,21 @@ static int s2mpg10_regulator_buck_set_voltage_time(str= uct regulator_dev *rdev, rdev->desc->ramp_mask); } =20 +static int s2mpg11_regulator_buck_set_voltage_time(struct regulator_dev *r= dev, + int old_uV, int new_uV) +{ + unsigned int ramp_mask; + + ramp_mask =3D rdev->desc->ramp_mask; + if (old_uV > new_uV) + /* The downwards mask is at a different position. */ + ramp_mask >>=3D 2; + + return s2mpg1x_regulator_buck_set_voltage_time(rdev, old_uV, new_uV, + rdev->desc->ramp_reg, + ramp_mask); +} + /* * We assign both, ::set_voltage_time() and ::set_voltage_time_sel(), beca= use * only if the latter is !=3D NULL, the regulator core will call neither d= uring @@ -919,6 +957,249 @@ static const struct s2mpg10_regulator_desc s2mpg10_re= gulators_bucks[] =3D { PCTRLSEL4, GENMASK(7, 4)) }; =20 +static const struct regulator_ops s2mpg11_reg_buck_ops[] =3D { + { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .is_enabled =3D regulator_is_enabled_regmap, + .enable =3D regulator_enable_regmap, + .disable =3D regulator_disable_regmap, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg11_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable_time =3D s2mpg10_regulator_buck_enable_time, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + }, { + .list_voltage =3D regulator_list_voltage_linear_range, + .map_voltage =3D regulator_map_voltage_linear_range, + .get_voltage_sel =3D regulator_get_voltage_sel_regmap, + .set_voltage_sel =3D regulator_set_voltage_sel_regmap, + .set_voltage_time =3D s2mpg11_regulator_buck_set_voltage_time, + .set_voltage_time_sel =3D regulator_set_voltage_time_sel, + .enable_time =3D s2mpg10_regulator_buck_enable_time, + .set_ramp_delay =3D regulator_set_ramp_delay_regmap, + } +}; + +#define s2mpg11_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + _vsel_reg_sfx, _vsel_mask, _en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, _r_table_sz, \ + _pc_reg, _pc_mask) \ + { \ + .desc =3D regulator_desc_s2mpg1x_ldo_cmn(#_num"s", \ + S2MPG11_LDO##_num, _supply, \ + s2mpg10_reg_ldo_ops, \ + _vrange, \ + S2MPG11_PMIC_L##_num##S_##_vsel_reg_sfx, \ + _vsel_mask, \ + S2MPG11_PMIC_##_en_reg, _en_mask, \ + _ramp_delay, _r_reg, _r_mask, _r_table, \ + _r_table_sz), \ + .pctrlsel_reg =3D _pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + + +/* standard LDO via LxM_CTRL */ +#define s2mpg11_regulator_desc_ldo(_num, _supply, _vrange) \ + s2mpg11_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + CTRL, GENMASK(5, 0), \ + L##_num##S_CTRL, BIT(7), \ + 0, 0, 0, NULL, 0, \ + 0, 0) + +/* standard LDO but possibly GPIO controlled */ +#define s2mpg11_regulator_desc_ldo_gpio(_num, _supply, _vrange, \ + _pc_reg, _pc_mask) \ + s2mpg11_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + CTRL, GENMASK(5, 0), \ + L##_num##S_CTRL, GENMASK(7, 6), \ + 0, 0, 0, NULL, 0, \ + S2MPG11_PMIC_##_pc_reg, _pc_mask) + +/* LDO with ramp support and possibly GPIO controlled */ +#define s2mpg11_regulator_desc_ldo_ramp(_num, _supply, _vrange, \ + _en_mask, _r_reg_sfx, _pc_reg, _pc_mask) \ + s2mpg11_regulator_desc_ldo_cmn(_num, _supply, _vrange, \ + CTRL1, GENMASK(6, 0), \ + LDO_CTRL1, _en_mask, \ + 6250, S2MPG11_PMIC_##_r_reg_sfx, GENMASK(1, 0), \ + s2mpg10_ldo_ramp_table, \ + ARRAY_SIZE(s2mpg10_ldo_ramp_table), \ + S2MPG11_PMIC_##_pc_reg, _pc_mask) + +#define s2mpg11_buck_to_ramp_mask(n) (GENMASK(3, 2) << (((n) % 2) * 4)) + +#define regulator_desc_s2mpg11_buckx(_name, _id, _supply, _vrange, \ + _vsel_reg, _en_reg, _en_mask, _r_reg) \ + regulator_desc_s2mpg1x_buck_cmn(_name, _id, _supply, \ + s2mpg11_reg_buck_ops, _vrange, \ + S2MPG11_PMIC_##_vsel_reg, GENMASK(7, 0), \ + S2MPG11_PMIC_##_en_reg, _en_mask, \ + S2MPG11_PMIC_##_r_reg, \ + s2mpg11_buck_to_ramp_mask(_id - S2MPG11_BUCK1), \ + s2mpg10_buck_ramp_table, \ + ARRAY_SIZE(s2mpg10_buck_ramp_table), 30) + +#define s2mpg11_regulator_desc_buck_xm(_num, _vrange, _vsel_reg_sfx, \ + _en_mask, _r_reg, _en_rrate) \ + .desc =3D regulator_desc_s2mpg11_buckx(#_num"s", \ + S2MPG11_BUCK##_num, "vinb"#_num"s", \ + _vrange, \ + B##_num##S_##_vsel_reg_sfx, \ + B##_num##S_CTRL, _en_mask, \ + _r_reg), \ + .enable_ramp_rate =3D _en_rrate + +#define s2mpg11_regulator_desc_buck_cm(_num, _vrange, _vsel_reg_sfx, \ + _en_mask, _r_reg) \ + { \ + s2mpg11_regulator_desc_buck_xm(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, 12500), \ + } + +#define s2mpg11_regulator_desc_buckn_cm_gpio(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, _pc_reg, _pc_mask) \ + { \ + s2mpg11_regulator_desc_buck_xm(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, 12500), \ + .pctrlsel_reg =3D S2MPG11_PMIC_##_pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +#define s2mpg11_regulator_desc_buck_vm(_num, _vrange, _vsel_reg_sfx, \ + _en_mask, _r_reg) \ + { \ + s2mpg11_regulator_desc_buck_xm(_num, _vrange, \ + _vsel_reg_sfx, _en_mask, _r_reg, 25000), \ + } + +#define s2mpg11_regulator_desc_bucka(_num, _num_lower, _r_reg, \ + _pc_reg, _pc_mask) \ + { \ + .desc =3D regulator_desc_s2mpg11_buckx(#_num_lower, \ + S2MPG11_BUCK##_num, "vinb"#_num_lower, \ + s2mpg11_buck_vranges##_num_lower, \ + BUCK##_num##_OUT, \ + BUCK##_num##_CTRL, GENMASK(7, 6), \ + _r_reg), \ + .enable_ramp_rate =3D 25000, \ + .pctrlsel_reg =3D S2MPG11_PMIC_##_pc_reg, \ + .pctrlsel_mask =3D _pc_mask, \ + } + +#define s2mpg11_regulator_desc_buckboost() \ + { \ + .desc =3D regulator_desc_s2mpg1x_buck_cmn("boost", \ + S2MPG11_BUCKBOOST, "vinbb", \ + s2mpg10_reg_ldo_ops, \ + s2mpg11_buck_vrangesboost, \ + S2MPG11_PMIC_BB_OUT1, GENMASK(6, 0), \ + S2MPG11_PMIC_BB_CTRL, BIT(7), \ + 0, 0, NULL, 0, 35), \ + .enable_ramp_rate =3D 17500, \ + } + +/* voltage range for s2mpg11 LDO 1, 2 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 1, 300000, 450000, 950000, STEP_12_5_MV= ); + +/* voltage range for s2mpg11 LDO 3, 7, 10, 11, 12, 14, 15 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 3, 700000, 1600000, 1950000, STEP_25_MV= ); + +/* voltage range for s2mpg11 LDO 4, 6 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 4, 1800000, 2500000, 3300000, STEP_25_M= V); + +/* voltage range for s2mpg11 LDO 5 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 5, 1600000, 1600000, 1950000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 LDO 8 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 8, 979600, 1130400, 1281200, 5800); + +/* voltage range for s2mpg11 LDO 9 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 9, 725000, 725000, 1300000, STEP_12_5_M= V); + +/* voltage range for s2mpg11 LDO 13 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_ldo, 13, 1800000, 1800000, 3350000, STEP_25_= MV); + +/* voltage range for s2mpg11 BUCK 1, 2, 3, 4, 8, 9, 10 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 1, 200000, 450000, 1300000, STEP_6_25_= MV); + +/* voltage range for s2mpg11 BUCK 5 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 5, 200000, 400000, 1300000, STEP_6_25_= MV); + +/* voltage range for s2mpg11 BUCK 6 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 6, 200000, 1000000, 1500000, STEP_6_25= _MV); + +/* voltage range for s2mpg11 BUCK 7 */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, 7, 600000, 1500000, 2200000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 BUCK D */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, d, 600000, 2400000, 3300000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 BUCK A */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, a, 600000, 1700000, 2100000, STEP_12_5= _MV); + +/* voltage range for s2mpg11 BUCK BOOST */ +S2MPG10_VOLTAGE_RANGE(s2mpg11_buck, boost, + 2600000, 3000000, 3600000, STEP_12_5_MV); + +static const struct s2mpg10_regulator_desc s2mpg11_regulators_ldos[] =3D { + s2mpg11_regulator_desc_ldo_ramp(1, "vinl1s", s2mpg11_ldo_vranges1, + GENMASK(5, 4), DVS_SYNC_CTRL1, + PCTRLSEL5, GENMASK(3, 0)), + s2mpg11_regulator_desc_ldo_ramp(2, "vinl1s", s2mpg11_ldo_vranges1, + GENMASK(7, 6), DVS_SYNC_CTRL2, + PCTRLSEL5, GENMASK(7, 4)), + s2mpg11_regulator_desc_ldo(3, "vinl3s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(4, "vinl5s", s2mpg11_ldo_vranges4), + s2mpg11_regulator_desc_ldo(5, "vinl3s", s2mpg11_ldo_vranges5), + s2mpg11_regulator_desc_ldo(6, "vinl5s", s2mpg11_ldo_vranges4), + s2mpg11_regulator_desc_ldo(7, "vinl3s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo_gpio(8, "vinl2s", s2mpg11_ldo_vranges8, + PCTRLSEL6, GENMASK(3, 0)), + s2mpg11_regulator_desc_ldo(9, "vinl2s", s2mpg11_ldo_vranges9), + s2mpg11_regulator_desc_ldo(10, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(11, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(12, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo_gpio(13, "vinl6s", s2mpg11_ldo_vranges13, + PCTRLSEL6, GENMASK(7, 4)), + s2mpg11_regulator_desc_ldo(14, "vinl4s", s2mpg11_ldo_vranges3), + s2mpg11_regulator_desc_ldo(15, "vinl3s", s2mpg11_ldo_vranges3), +}; + +static const struct s2mpg10_regulator_desc s2mpg11_regulators_bucks[] =3D { + s2mpg11_regulator_desc_buckboost(), + s2mpg11_regulator_desc_buckn_cm_gpio(1, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP1, + PCTRLSEL1, GENMASK(3, 0)), + s2mpg11_regulator_desc_buckn_cm_gpio(2, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP1, + PCTRLSEL1, GENMASK(7, 4)), + s2mpg11_regulator_desc_buckn_cm_gpio(3, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP2, + PCTRLSEL2, GENMASK(3, 0)), + s2mpg11_regulator_desc_buck_cm(4, s2mpg11_buck_vranges1, + OUT, BIT(7), DVS_RAMP2), + s2mpg11_regulator_desc_buckn_cm_gpio(5, s2mpg11_buck_vranges5, + OUT, GENMASK(7, 6), DVS_RAMP3, + PCTRLSEL2, GENMASK(7, 4)), + s2mpg11_regulator_desc_buck_cm(6, s2mpg11_buck_vranges6, + OUT1, BIT(7), DVS_RAMP3), + s2mpg11_regulator_desc_buck_vm(7, s2mpg11_buck_vranges7, + OUT1, BIT(7), DVS_RAMP4), + s2mpg11_regulator_desc_buckn_cm_gpio(8, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP4, + PCTRLSEL3, GENMASK(3, 0)), + s2mpg11_regulator_desc_buckn_cm_gpio(9, s2mpg11_buck_vranges1, + OUT1, GENMASK(7, 6), DVS_RAMP5, + PCTRLSEL3, GENMASK(7, 4)), + s2mpg11_regulator_desc_buck_cm(10, s2mpg11_buck_vranges1, + OUT, BIT(7), DVS_RAMP5), + s2mpg11_regulator_desc_bucka(D, d, DVS_RAMP6, PCTRLSEL4, GENMASK(3, 0)), + s2mpg11_regulator_desc_bucka(A, a, DVS_RAMP6, PCTRLSEL4, GENMASK(7, 4)), +}; + static const struct regulator_ops s2mps11_ldo_ops =3D { .list_voltage =3D regulator_list_voltage_linear, .map_voltage =3D regulator_map_voltage_linear, @@ -1803,6 +2084,7 @@ static int s2mps11_handle_ext_control(struct s2mps11_= info *s2mps11, break; =20 case S2MPG10: + case S2MPG11: /* * If desc.enable_val is !=3D 0, then external control was * requested. We can not test s2mpg10_desc::ext_control, @@ -1862,6 +2144,22 @@ static int s2mps11_pmic_probe(struct platform_device= *pdev) BUILD_BUG_ON((enum s2mpg10_regulators) S2MPS_REGULATOR_MAX < S2MPG10_REGULATOR_MAX); break; + case S2MPG11: + switch (pdev->id + 1) { + case S2MPG10_REGULATOR_CELL_ID_BUCKS: + rdev_num =3D ARRAY_SIZE(s2mpg11_regulators_bucks); + s2mpg10_regulators =3D s2mpg11_regulators_bucks; + break; + case S2MPG10_REGULATOR_CELL_ID_LDOS: + rdev_num =3D ARRAY_SIZE(s2mpg11_regulators_ldos); + s2mpg10_regulators =3D s2mpg11_regulators_ldos; + break; + default: + return -EINVAL; + } + BUILD_BUG_ON((enum s2mpg11_regulators) S2MPS_REGULATOR_MAX < + S2MPG11_REGULATOR_MAX); + break; case S2MPS11X: rdev_num =3D ARRAY_SIZE(s2mps11_regulators); regulators =3D s2mps11_regulators; @@ -1940,6 +2238,7 @@ static int s2mps11_pmic_probe(struct platform_device = *pdev) =20 static const struct platform_device_id s2mps11_pmic_id[] =3D { { "s2mpg10-regulator", S2MPG10}, + { "s2mpg11-regulator", S2MPG11}, { "s2mps11-regulator", S2MPS11X}, { "s2mps13-regulator", S2MPS13X}, { "s2mps14-regulator", S2MPS14X}, --=20 2.49.0.1204.g71687c7c1d-goog From nobody Fri Dec 19 19:15:52 2025 Received: from mail-ed1-f48.google.com (mail-ed1-f48.google.com [209.85.208.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 95E011DE4E6 for ; Wed, 4 Jun 2025 15:25:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050762; cv=none; b=L1TGbLSmrCGAtAvoGwFO/eIyPMGfsf1DCDsNjbiv8iheeawSCs0TsSoAlkuXqdlKpKmCqymNNTWiJWyXsBd5tbHh6hYrCje6GJbrKwRgrHUA2JiT/riWzvnXo+UuFcdnlXuj8XgyP5+BA6FuANn3O6JlRAFg4lfVtp5rDdwOv3A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1749050762; c=relaxed/simple; bh=38iyypFvEIDDo+XViI83hfrn7fp3ROVaa2JyQWVHtXI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=vBqc0x/OGLwVKmntNeLSzQKQJVYfBLIW4gEfsEVK5G/55GJy8L2Wzx9IGRJDY+0uSFxs55hhKlqR/qa2BfzGV1naH3eGvMvhZKUtc6OdMhHUfYSDV1JHMmujjXfckcw7HJKbwpJhrv0Z6pRbIUEKJYInw6ODDKRLeYBWMbBbSJY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=u/3wSDI2; arc=none smtp.client-ip=209.85.208.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="u/3wSDI2" Received: by mail-ed1-f48.google.com with SMTP id 4fb4d7f45d1cf-606b6dbe316so3193872a12.3 for ; Wed, 04 Jun 2025 08:25:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1749050755; x=1749655555; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=QHL3sUIzhoW/yqDxEI2huZEz7k/6gYpbh53sq2QOYGk=; b=u/3wSDI20VetYzJBc0CaJdFq5W42zu+a5LNRj4z0kHkGckg00rVca3cQOl5nPmSfSr bW+S+zUmlhp+0T24YBXIfkzPdEjM2d5J0qdOdaJHwcbFUPC3I2jOZ8TSR0nWrMXs05Pl ZcynzZnVRH6btyyKRlDBgS6G+dptTK39xt8lq3EU0LOH+le1PWzI9z8WR8Rtrjly01Dr yEsJGISZs13eStjyQwFtTMgR7Zwb1ekeQo4UZ+ViijMuDoE1MA6G27uNtolX7LPttC75 BkMQwq2LydaxTiBppH/0AB5s+sGko1FwGuBR5Dpm1YexdMDud76f/pP0t4nYFGqf8I47 RAqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1749050755; x=1749655555; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=QHL3sUIzhoW/yqDxEI2huZEz7k/6gYpbh53sq2QOYGk=; b=MyA+dgPXVidyZIxWwgkHmX7ZBxLRoaZO89rFHBcgxS6JI3KJNqjN8njF1UFJTunWbM u/LbPV0PDgu+2FvwG62CKuikqRF72BgeVKzfuIpO9ved/dR9BGxCseWjaHn0050oFGVV 7qZGKddQbPpP9k0O8uUIkg1a2FviqVkuWRF6o16brYFTgAsDxwtRWYYQ1bebw3+5uxre z6hbZkBtDC2LpWyqz8IRXaFPTW/yeNJUMlcZmZIzkvefFQNXW+xnyMz3PjdaOPxSgSpM Q5lTrp0/KF5ZhuyLQjo940Tp7WxIVij4Pyc3TAAQDVp9k/FeCqS6U7OQCL3mhAs30Y0b iBLg== X-Forwarded-Encrypted: i=1; AJvYcCX279+P8bcfgZ+cCFst40clRtmmSH+Al8s2VnuE3HwGNRiaLsh8gFkIECcvuh3ZkYw7PFtkEaJMppEq7N0=@vger.kernel.org X-Gm-Message-State: AOJu0YwkRhVcCGGWVvbTXKFXUcAxe5ng8+Er2cEPdFJzE8F+0PmAhIan 95DbJo25XPhuGt1Sor8+16iRlj3owtn/x9SSR6KEYjqXvKcaubJuUoXwSfseMRJYrks= X-Gm-Gg: ASbGncuLZbJlJHzfs8dan+4ksFsKrkEPmC204HA7TKUh8CCWDaJ1dbTrR0fqMbrwA5m dOASm+RQpaTozD5IP2aEY8j9aSmbgHhoA2ODqRTXId6jkn4ltoyR/XJiXaKjKQ4PdU0HbpOzrgb ogQ3zycUZbeSkVfyuqqzHvU1OykQ4DPa12qaulAu/31XclrhYFdtSBZSmdaPDCqQsozTndSalr/ IZQncx8n/9aJnJN02EEj+gc/BOmR8EnG3xsHXxWi9pQIPuaIdB6EM2GiQI3LVXCFaCTTfABXIpy iFJNTf8tfha/JV7ymuWqEcK2s3GA/lAQjdeq4YZg23nptF6c8uZVa4vAdX9I0bV/BDeOicLpLDB BsgUQYpSGtxe/TnI4olGKwLkp8O4HBjoW710= X-Google-Smtp-Source: AGHT+IE5xsg7Femx+fxJUmqis3En5XL3tdeKdVoLZHO6BHxnqgQt3JKQXfamnwt6W3l2CrMDnwEtNA== X-Received: by 2002:a05:6402:348d:b0:5fb:c126:12c9 with SMTP id 4fb4d7f45d1cf-606ea17d2c0mr3262215a12.25.1749050755202; Wed, 04 Jun 2025 08:25:55 -0700 (PDT) Received: from puffmais.c.googlers.com (140.20.91.34.bc.googleusercontent.com. [34.91.20.140]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-606ed984f63sm1051640a12.58.2025.06.04.08.25.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 04 Jun 2025 08:25:54 -0700 (PDT) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Wed, 04 Jun 2025 16:25:56 +0100 Subject: [PATCH 17/17] regulator: s2mps11: more descriptive gpio consumer name Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250604-s2mpg1x-regulators-v1-17-6038740f49ae@linaro.org> References: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> In-Reply-To: <20250604-s2mpg1x-regulators-v1-0-6038740f49ae@linaro.org> To: Tudor Ambarus , Rob Herring , Conor Dooley , Krzysztof Kozlowski , Liam Girdwood , Mark Brown , Lee Jones , Linus Walleij , Bartosz Golaszewski Cc: Peter Griffin , Will McVicker , kernel-team@android.com, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-gpio@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Currently, gpios claimed by this driver for external rail control all show up with "s2mps11-regulator" as consumer, which is not very informative. Switch to using the regulator name via desc->name instead, using the device name as fallback. Signed-off-by: Andr=C3=A9 Draszik --- drivers/regulator/s2mps11.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/regulator/s2mps11.c b/drivers/regulator/s2mps11.c index 3b5f6f2f2b11be81f27bc39d5d48005da4afeace..a1bb4e420acf23ed048c3560049= 30c586d21b39f 100644 --- a/drivers/regulator/s2mps11.c +++ b/drivers/regulator/s2mps11.c @@ -357,7 +357,8 @@ static int s2mps11_of_parse_gpiod(struct device_node *n= p, "samsung,ext-control", 0, GPIOD_OUT_HIGH | GPIOD_FLAGS_BIT_NONEXCLUSIVE, - "s2mps11-regulator"); + desc->name + ? : dev_name(config->dev)); if (IS_ERR(ena_gpiod)) { ret =3D PTR_ERR(ena_gpiod); =20 --=20 2.49.0.1204.g71687c7c1d-goog