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client-ip=165.204.84.17; helo=SATLEXMB04.amd.com; pr=C Received: from SATLEXMB04.amd.com (165.204.84.17) by BL6PEPF00020E5F.mail.protection.outlook.com (10.167.249.20) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.8792.29 via Frontend Transport; Tue, 3 Jun 2025 17:25:36 +0000 Received: from ethanolx7ea3host.amd.com (10.180.168.240) by SATLEXMB04.amd.com (10.181.40.145) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 3 Jun 2025 12:25:34 -0500 From: Terry Bowman To: , , , , , , , , , , , , , , , , , , , , , , , , , , Subject: [PATCH v9 15/16] CXL/PCI: Enable CXL protocol errors during CXL Port probe Date: Tue, 3 Jun 2025 12:22:38 -0500 Message-ID: <20250603172239.159260-16-terry.bowman@amd.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250603172239.159260-1-terry.bowman@amd.com> References: <20250603172239.159260-1-terry.bowman@amd.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: SATLEXMB03.amd.com (10.181.40.144) To SATLEXMB04.amd.com (10.181.40.145) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00020E5F:EE_|DM4PR12MB6040:EE_ X-MS-Office365-Filtering-Correlation-Id: 28e3248e-3ba9-443f-fea0-08dda2c3a71e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700013|1800799024|82310400026|376014|7416014|921020; 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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jun 2025 17:25:36.2174 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 28e3248e-3ba9-443f-fea0-08dda2c3a71e X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00020E5F.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6040 Content-Type: text/plain; charset="utf-8" CXL protocol errors are not enabled for all CXL devices after boot. These must be enabled inorder to process CXL protocol errors. Export the AER service driver's pci_aer_unmask_internal_errors(). Introduce cxl_unmask_prot_interrupts() to call pci_aer_unmask_internal_erro= rs(). pci_aer_unmask_internal_errors() expects the pdev->aer_cap is initialized. But, dev->aer_cap is not initialized for CXL Upstream Switch Ports and CXL Downstream Switch Ports. Initialize the dev->aer_cap if necessary. Enable A= ER correctable internal errors and uncorrectable internal errors for all CXL devices. Signed-off-by: Terry Bowman Reviewed-by: Jonathan Cameron Reviewed-by: Kuppuswamy Sathyanarayanan --- drivers/cxl/port.c | 29 +++++++++++++++++++++++++++-- drivers/pci/pcie/aer.c | 3 ++- include/linux/aer.h | 1 + 3 files changed, 30 insertions(+), 3 deletions(-) diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c index 0f7c4010ba58..3687848ae772 100644 --- a/drivers/cxl/port.c +++ b/drivers/cxl/port.c @@ -3,6 +3,7 @@ #include #include #include +#include =20 #include "cxlmem.h" #include "cxlpci.h" @@ -60,6 +61,21 @@ static int discover_region(struct device *dev, void *unu= sed) =20 #ifdef CONFIG_PCIEAER_CXL =20 +static void cxl_unmask_prot_interrupts(struct device *dev) +{ + struct pci_dev *pdev __free(pci_dev_put) =3D + pci_dev_get(to_pci_dev(dev)); + + if (!pdev->aer_cap) { + pdev->aer_cap =3D pci_find_ext_capability(pdev, + PCI_EXT_CAP_ID_ERR); + if (!pdev->aer_cap) + return; + } + + pci_aer_unmask_internal_errors(pdev); +} + static void cxl_dport_map_rch_aer(struct cxl_dport *dport) { resource_size_t aer_phys; @@ -118,8 +134,12 @@ static void cxl_uport_init_ras_reporting(struct cxl_po= rt *port, =20 map->host =3D host; if (cxl_map_component_regs(map, &port->uport_regs, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(&port->dev, "Failed to map RAS capability\n"); + return; + } + + cxl_unmask_prot_interrupts(port->uport_dev); } =20 /** @@ -144,9 +164,12 @@ void cxl_dport_init_ras_reporting(struct cxl_dport *dp= ort, struct device *host) } =20 if (cxl_map_component_regs(&dport->reg_map, &dport->regs.component, - BIT(CXL_CM_CAP_CAP_ID_RAS))) + BIT(CXL_CM_CAP_CAP_ID_RAS))) { dev_dbg(dport->dport_dev, "Failed to map RAS capability\n"); + return; + } =20 + cxl_unmask_prot_interrupts(dport->dport_dev); } EXPORT_SYMBOL_NS_GPL(cxl_dport_init_ras_reporting, "CXL"); =20 @@ -177,6 +200,8 @@ static void cxl_endpoint_port_init_ras(struct cxl_port = *port) } =20 cxl_dport_init_ras_reporting(dport, &cxlmd->dev); + + cxl_unmask_prot_interrupts(cxlmd->cxlds->dev); } =20 #else diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c index 5efe5a718960..2d202ad1453a 100644 --- a/drivers/pci/pcie/aer.c +++ b/drivers/pci/pcie/aer.c @@ -964,7 +964,7 @@ static bool find_source_device(struct pci_dev *parent, * Note: AER must be enabled and supported by the device which must be * checked in advance, e.g. with pcie_aer_is_native(). */ -static void pci_aer_unmask_internal_errors(struct pci_dev *dev) +void pci_aer_unmask_internal_errors(struct pci_dev *dev) { int aer =3D dev->aer_cap; u32 mask; @@ -977,6 +977,7 @@ static void pci_aer_unmask_internal_errors(struct pci_d= ev *dev) mask &=3D ~PCI_ERR_COR_INTERNAL; pci_write_config_dword(dev, aer + PCI_ERR_COR_MASK, mask); } +EXPORT_SYMBOL_NS_GPL(pci_aer_unmask_internal_errors, "CXL"); =20 static bool is_cxl_mem_dev(struct pci_dev *dev) { diff --git a/include/linux/aer.h b/include/linux/aer.h index c9a18eca16f8..74600e75705f 100644 --- a/include/linux/aer.h +++ b/include/linux/aer.h @@ -107,5 +107,6 @@ void pci_print_aer(struct pci_dev *dev, int aer_severit= y, int cper_severity_to_aer(int cper_severity); void aer_recover_queue(int domain, unsigned int bus, unsigned int devfn, int severity, struct aer_capability_regs *aer_regs); +void pci_aer_unmask_internal_errors(struct pci_dev *dev); #endif //_AER_H_ =20 --=20 2.34.1