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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d7f1afebsm164430945e9.0.2025.06.03.07.37.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 07:37:53 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 03 Jun 2025 16:36:23 +0200 Subject: [PATCH v8 1/6] Documentation: ABI: IIO: add new convdelay documentation Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-wip-bl-ad7606-calibration-v8-1-2371e7108f32@baylibre.com> References: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> In-Reply-To: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1850; i=adureghello@baylibre.com; h=from:subject:message-id; bh=m1V9a4luyCqmxst4hAeMv2hk5LxVMC81ZTSMIekPDQ4=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiw56h49tXVZsOVs7u3tdiwdDf/nZHMUv2H/8LtpwfEv /EGfIxX7ChlYRDjYpAVU2SpS4wwCb0dKqW8gHE2zBxWJpAhDFycAjCRg1UM/z3k71Qw8J28dkH3 eMmC78z5T+fOubQioWfO24vVc/LXbL3F8M9U6MrctPkCW7pqfZ/Zn1ob27zxJeesj0UPdIzabVl /JHIAAA== X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add new IIO "convdelay" documentation. The ad7606 implements a phase calibation feature, in nanoseconds. Being this a time delay, using the convdelay suffix. Signed-off-by: Angelo Dureghello --- Documentation/ABI/testing/sysfs-bus-iio | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/ABI/testing/sysfs-bus-iio b/Documentation/ABI/te= sting/sysfs-bus-iio index ef52c427a015cf47bb9847782e13afbee01e9f31..7e59cbd5acb85fd0909c1d56f9d= 76a84933d418a 100644 --- a/Documentation/ABI/testing/sysfs-bus-iio +++ b/Documentation/ABI/testing/sysfs-bus-iio @@ -559,6 +559,30 @@ Description: - a small discrete set of values like "0 2 4 6 8" - a range specified as "[min step max]" =20 +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Delay of start of conversion from common reference point shared + by all channels. Can be writable when used to compensate for + delay variation introduced by external filters feeding a + simultaneous sampling ADC. + + E.g., for the ad7606 ADC series, this value is intended as a + configurable time delay in seconds, to correct delay introduced + by an optional external filtering circuit. + +What: /sys/bus/iio/devices/iio:deviceX/in_voltageY_convdelay_available +KernelVersion: 6.16 +Contact: linux-iio@vger.kernel.org +Description: + Available values of convdelay. Maybe expressed as: + + - a range specified as "[min step max]" + + If shared across all channels, _convdelay_available + is used. + What: /sys/bus/iio/devices/iio:deviceX/in_accel_x_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_y_calibscale What: /sys/bus/iio/devices/iio:deviceX/in_accel_z_calibscale --=20 2.49.0 From nobody Mon Feb 9 09:23:04 2026 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8BB0D23A563 for ; Tue, 3 Jun 2025 14:37:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748961479; cv=none; b=YVvLA00iadWhpw+Ya5beD7eZP2tc/wWHXvXDReNeQT2ix2JQ1UYTbNQevEVBVJc0NxzcTDHKduKGDo0tT0h3i0vC9R4l6Y8NUQnrg+XhW6hRIsPnAercUno3h40UG6LH1BBlxV2sHEUAtyBTNw5ONziAzhw6YeolIL9/X1Xfopg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748961479; c=relaxed/simple; bh=cBfFaDkjp8cn9ZsqfhZtThmlU0g1ewE4x6fWUwfuIqQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=PL3WhuX4pMvhgitaUun07oSsUAdIMC0B/PFXPrO/iEAO4q/gZ/TJbSC/aeizbCPZ+W2LDJ3A/Z0R+KEQLReyPkKBhoB5LpAwLoC2cqmvQFUtxGt7ysWJ0jld6PQSHFqx/8L3zbWJkGf9CpIVNZivhgnjiRf7Pjwaf+CbL2yARWw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com; spf=pass smtp.mailfrom=baylibre.com; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b=ysbRskEN; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=baylibre.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=baylibre.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=baylibre-com.20230601.gappssmtp.com header.i=@baylibre-com.20230601.gappssmtp.com header.b="ysbRskEN" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-451d54214adso23585335e9.3 for ; Tue, 03 Jun 2025 07:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20230601.gappssmtp.com; s=20230601; t=1748961476; x=1749566276; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=Wv6YLDN8CkaWn53LtM3+C3UNFVc2t/n3NaXm0d2EaQs=; b=ysbRskEN0A3PLHKDFHGbg9/fMXzvuRjhl9QCN3EUImjtEfAFJr1sRFGQ/20u+lueKl JN9ngEOn3QEB+n99c53jVRw+4YX4KJcVs6Ugh3btewQEeRROxcGovVPgGFS5c/6tQ+Ir uQqhJYl7pZyoH6/Vureu/DssC+j9KIDKUHXwJqlzwwxTN7Ezqo+AMl4BgDKvKRzijbyV iCGgVwBMvK45zV3oVD7vLjXG69v0E/5Qa4bBjpY1I+NT2/apjdhgBQLuUyxnwx0uztkL wu+JKREiEPZwKFU3lzli1jMCbSVy0MwaYWlqTfqOXymJn3J5cQU2hDGWYR8W8lZ8PTUU 9cug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748961476; x=1749566276; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Wv6YLDN8CkaWn53LtM3+C3UNFVc2t/n3NaXm0d2EaQs=; b=oj7fufiTk9sVfIXPqeag6H+rQuoddQkLUGr+Rk1EkKMC73QyjVnTm8nLMEelj7P/8n Lm3QqOKv55CCw1fLxwqfLDI/lErQ7XMgpj+HjgkXOXyCuYhgcg6gntY2GGpL30W1TpVf +DnVURcDwtCI+EfSu4hDcSux7NheCPlaIzpCva7Ccu2DG9eXsRN6agoSAFhcE1Rk4O6b Ubc/b9zvxmfYuooeid6fI3Sh1PYNeK+THG84LSTiIzhFtsl8Karr79LtaEojoBt03YtT Pw9yDTbW3PN86W/1nElsEmOXxbBVkZccGewwfOLtIUa561YLUpf6rXLK404m32DdXR3d oW8A== X-Forwarded-Encrypted: i=1; AJvYcCWjdYn3YwPaJ1IQ9uXNUlr9GF8rfY1ncIObvKSB/adTpAC34xCmunLdLZTp0KO9PB5aXwU6QOsG61bQ0n0=@vger.kernel.org X-Gm-Message-State: AOJu0YyTjLgy1k03jTqML3PfL3R9DOcLSaLz/KgxzMlfOAZyiC9qnmVv XQMprQu1XxsRFQZOZnbvMaaiGnMVZSMi4+tfQVlz9VgzSYtOP8xsRfVZHRVCjZ0HXUo= X-Gm-Gg: ASbGncvWQsvRhtqldaIBgmR7R5JAqWIo4Ww5LDObi461wpRPHpncOarFgV3n+OmhF40 vFYj3ygTmZL7kKjqaDwX9YaXg1ChYaTuVM1+LlTj0fFO+cMwi8dgyj5bVQAaIR0w0+6zg4BM8+Q UTvSEWU+g80sX/Dn9Spj2zJqGb9GorcJ+KI4d+U4UY4XTYMbGSg6wB7ve096Btt5iQCkMBlMNKj JVWecidZUHrD/rzopwpxmNUud4k6etETc3BMfhPfi86q24qQo+tG4JyHRr2Gkd1o+qYThnRx3Xl epFeDVTHyzEjURvSRCgMP7lGiyubqhOwGwThkScSLm8jIe3O4GhFifk76ndF3u/KsSzUq9RLBFK kM+2P/XPgkKBaG/NB7PZOuvQ3c9umUb2lCIA= X-Google-Smtp-Source: AGHT+IGi92HX1UJvJNv4jB4VsIqlJhcaBZEOiBDzHJTO+g5R+fS7gSPid4Q+SBUhQBpnpASye2ehmw== X-Received: by 2002:a05:600c:4f53:b0:451:edc8:7806 with SMTP id 5b1f17b1804b1-451edc879e2mr2630175e9.32.1748961475600; Tue, 03 Jun 2025 07:37:55 -0700 (PDT) Received: from [192.168.0.2] (host-80-116-51-117.pool80116.interbusiness.it. [80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d7f1afebsm164430945e9.0.2025.06.03.07.37.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 07:37:55 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 03 Jun 2025 16:36:24 +0200 Subject: [PATCH v8 2/6] iio: core: add ADC delay calibration definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-wip-bl-ad7606-calibration-v8-2-2371e7108f32@baylibre.com> References: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> In-Reply-To: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1303; i=adureghello@baylibre.com; h=from:subject:message-id; bh=1bBjL7VlkgNBkqwPeVPqoUWRyRoNRlMdTRY5+MPjmRY=; b=kA0DAAoWD8251fe2tzsByyZiAGg/CHijdsTzMjwT3UGd2xYkTjaRg19yhgnb2aeqUjuFnGlAz Yh1BAAWCgAdFiEEfmFYNFXbVRojoAGbD8251fe2tzsFAmg/CHgACgkQD8251fe2tzsLDQEAwcDp dw/ODgoZISYIDlUeA3UR3m5FJKXZBPXv3T2cjTgA/0Aah4WIIse+TYCpnRXKtC3T4k5/MjryXo5 zSSfPaDMN X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello ADCs as ad7606 implement a phase calibration as a delay. Add such definition, needed for ad7606. Signed-off-by: Angelo Dureghello --- drivers/iio/industrialio-core.c | 1 + include/linux/iio/types.h | 1 + 2 files changed, 2 insertions(+) diff --git a/drivers/iio/industrialio-core.c b/drivers/iio/industrialio-cor= e.c index 178e99b111debc59a247fcc3a6037e429db3bebf..f13c3aa470d774bfe655d6a9fb0= 0c263789db637 100644 --- a/drivers/iio/industrialio-core.c +++ b/drivers/iio/industrialio-core.c @@ -188,6 +188,7 @@ static const char * const iio_chan_info_postfix[] =3D { [IIO_CHAN_INFO_CALIBAMBIENT] =3D "calibambient", [IIO_CHAN_INFO_ZEROPOINT] =3D "zeropoint", [IIO_CHAN_INFO_TROUGH] =3D "trough_raw", + [IIO_CHAN_INFO_CONVDELAY] =3D "convdelay", }; /** * iio_device_id() - query the unique ID for the device diff --git a/include/linux/iio/types.h b/include/linux/iio/types.h index d89982c98368cf72c0fc30fa66ab001e48af4e8b..ad2761efcc8315e1f9907d2a715= 9447fb463333e 100644 --- a/include/linux/iio/types.h +++ b/include/linux/iio/types.h @@ -69,6 +69,7 @@ enum iio_chan_info_enum { IIO_CHAN_INFO_CALIBAMBIENT, IIO_CHAN_INFO_ZEROPOINT, IIO_CHAN_INFO_TROUGH, + IIO_CHAN_INFO_CONVDELAY, }; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d7f1afebsm164430945e9.0.2025.06.03.07.37.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 07:37:56 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 03 Jun 2025 16:36:25 +0200 Subject: [PATCH v8 3/6] iio: adc: ad7606: add offset and phase calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-wip-bl-ad7606-calibration-v8-3-2371e7108f32@baylibre.com> References: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> In-Reply-To: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=9455; i=adureghello@baylibre.com; h=from:subject:message-id; bh=m8KvlzK04oJDHf4rtyOO7VisfkGK5WgMZB7GZsUOf6s=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiw56iIuJJWyTf3dUVMQOqfxV9PHfBdvcewRm3housGw mU25XeSO0pZGMS4GGTFFFnqEiNMQm+HSikvYJwNM4eVCWQIAxenAEzkei0jw8Ebx6O3mD9r+Pb3 yjG7m/G7rc3Wp59NC11yYV2ccKoX12yGfzpVTvzJCfMY1mjtuP9qgoZ56qelxosaG80OdW5u+zn 1MR8A X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add support for offset and phase calibration, only for devices that support software mode, that are: ad7606b ad7606c-16 ad7606c-18 Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 160 +++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 9 +++ 2 files changed, 169 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 185243dee86ed2e9ebc43b578003d0c010e97a9f..9a9bef0cfbb37138f71ba5b1bab= eaa423eaf4d5a 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -95,6 +95,22 @@ static const unsigned int ad7616_oversampling_avail[8] = =3D { 1, 2, 4, 8, 16, 32, 64, 128, }; =20 +static const int ad7606_calib_offset_avail[3] =3D { + -128, 1, 127, +}; + +static const int ad7606c_18bit_calib_offset_avail[3] =3D { + -512, 4, 508, +}; + +static const int ad7606b_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1250 }, { 0, 318750 }, +}; + +static const int ad7606c_calib_phase_avail[][2] =3D { + { 0, 0 }, { 0, 1000 }, { 0, 255000 }, +}; + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan); static int ad7606c_16bit_chan_scale_setup(struct iio_dev *indio_dev, @@ -164,6 +180,8 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606b_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606b_info, "IIO_AD7606"); =20 @@ -177,6 +195,8 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_16_info, "IIO_AD7606"); =20 @@ -226,6 +246,8 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, + .calib_phase_avail =3D ad7606c_calib_phase_avail, }; EXPORT_SYMBOL_NS_GPL(ad7606c_18_info, "IIO_AD7606"); =20 @@ -681,6 +703,40 @@ static int ad7606_scan_direct(struct iio_dev *indio_de= v, unsigned int ch, return ret; } =20 +static int ad7606_get_calib_offset(struct ad7606_state *st, int ch, int *v= al) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_OFFSET(ch)); + if (ret < 0) + return ret; + + *val =3D st->chip_info->calib_offset_avail[0] + + ret * st->chip_info->calib_offset_avail[1]; + + return 0; +} + +static int ad7606_get_calib_phase(struct ad7606_state *st, int ch, int *va= l, + int *val2) +{ + int ret; + + ret =3D st->bops->reg_read(st, AD7606_CALIB_PHASE(ch)); + if (ret < 0) + return ret; + + *val =3D 0; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + *val2 =3D ret * st->chip_info->calib_phase_avail[1][1]; + + return 0; +} + static int ad7606_read_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int *val, @@ -715,6 +771,22 @@ static int ad7606_read_raw(struct iio_dev *indio_dev, pwm_get_state(st->cnvst_pwm, &cnvst_pwm_state); *val =3D DIV_ROUND_CLOSEST_ULL(NSEC_PER_SEC, cnvst_pwm_state.period); return IIO_VAL_INT; + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_get_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + if (ret) + return ret; + return IIO_VAL_INT_PLUS_NANO; } return -EINVAL; } @@ -765,6 +837,64 @@ static int ad7606_write_os_hw(struct iio_dev *indio_de= v, int val) return 0; } =20 +static int ad7606_set_calib_offset(struct ad7606_state *st, int ch, int va= l) +{ + int start_val, step_val, stop_val; + int offset; + + start_val =3D st->chip_info->calib_offset_avail[0]; + step_val =3D st->chip_info->calib_offset_avail[1]; + stop_val =3D st->chip_info->calib_offset_avail[2]; + + if (val < start_val || val > stop_val) + return -EINVAL; + + offset =3D (val - start_val) / step_val; + + return st->bops->reg_write(st, AD7606_CALIB_OFFSET(ch), offset); +} + +static int ad7606_set_calib_phase(struct ad7606_state *st, int ch, int val, + int val2) +{ + int wreg, start_ns, step_ns, stop_ns; + + if (val !=3D 0) + return -EINVAL; + + start_ns =3D st->chip_info->calib_phase_avail[0][1]; + step_ns =3D st->chip_info->calib_phase_avail[1][1]; + stop_ns =3D st->chip_info->calib_phase_avail[2][1]; + + /* + * ad7606b: phase delay from 0 to 318.75 =CE=BCs in steps of 1.25 =CE=BCs. + * ad7606c-16/18: phase delay from 0 =C2=B5s to 255 =C2=B5s in steps of 1= =C2=B5s. + */ + if (val2 < start_ns || val2 > stop_ns) + return -EINVAL; + + wreg =3D val2 / step_ns; + + return st->bops->reg_write(st, AD7606_CALIB_PHASE(ch), wreg); +} + +static int ad7606_write_raw_get_fmt(struct iio_dev *indio_dev, + struct iio_chan_spec const *chan, long info) +{ + switch (info) { + case IIO_CHAN_INFO_SCALE: + return IIO_VAL_INT_PLUS_MICRO; + case IIO_CHAN_INFO_SAMP_FREQ: + case IIO_CHAN_INFO_OVERSAMPLING_RATIO: + case IIO_CHAN_INFO_CALIBBIAS: + return IIO_VAL_INT; + case IIO_CHAN_INFO_CONVDELAY: + return IIO_VAL_INT_PLUS_NANO; + default: + return -EINVAL; + } +} + static int ad7606_write_raw(struct iio_dev *indio_dev, struct iio_chan_spec const *chan, int val, @@ -818,6 +948,18 @@ static int ad7606_write_raw(struct iio_dev *indio_dev, if (val < 0 && val2 !=3D 0) return -EINVAL; return ad7606_set_sampling_freq(st, val); + case IIO_CHAN_INFO_CALIBBIAS: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_offset(st, chan->scan_index, val); + iio_device_release_direct(indio_dev); + return ret; + case IIO_CHAN_INFO_CONVDELAY: + if (!iio_device_claim_direct(indio_dev)) + return -EBUSY; + ret =3D ad7606_set_calib_phase(st, chan->scan_index, val, val2); + iio_device_release_direct(indio_dev); + return ret; default: return -EINVAL; } @@ -996,6 +1138,14 @@ static int ad7606_read_avail(struct iio_dev *indio_de= v, *type =3D IIO_VAL_INT_PLUS_MICRO; =20 return IIO_AVAIL_LIST; + case IIO_CHAN_INFO_CALIBBIAS: + *vals =3D st->chip_info->calib_offset_avail; + *type =3D IIO_VAL_INT; + return IIO_AVAIL_RANGE; + case IIO_CHAN_INFO_CONVDELAY: + *vals =3D (const int *)st->chip_info->calib_phase_avail; + *type =3D IIO_VAL_INT_PLUS_NANO; + return IIO_AVAIL_RANGE; } return -EINVAL; } @@ -1058,6 +1208,7 @@ static const struct iio_info ad7606_info_sw_mode =3D { .read_raw =3D &ad7606_read_raw, .write_raw =3D &ad7606_write_raw, .read_avail =3D &ad7606_read_avail, + .write_raw_get_fmt =3D ad7606_write_raw_get_fmt, .debugfs_reg_access =3D &ad7606_reg_access, .validate_trigger =3D &ad7606_validate_trigger, .update_scan_mode =3D &ad7606_update_scan_mode, @@ -1250,6 +1401,15 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) chan->info_mask_separate_available |=3D BIT(IIO_CHAN_INFO_SCALE); =20 + if (st->chip_info->calib_offset_avail) { + chan->info_mask_separate |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + chan->info_mask_separate_available |=3D + BIT(IIO_CHAN_INFO_CALIBBIAS) | + BIT(IIO_CHAN_INFO_CONVDELAY); + } + /* * All chips with software mode support oversampling, * so we skip the oversampling_available check. And the diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index 441e62c521bcbea69b4f70bb2d55f65334d22276..f613583a7fa4095115b0b28e3f8= e51cd32b93524 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -40,6 +40,11 @@ #define AD7606_RANGE_CH_ADDR(ch) (0x03 + ((ch) >> 1)) #define AD7606_OS_MODE 0x08 =20 +#define AD7606_CALIB_GAIN(ch) (0x09 + (ch)) +#define AD7606_CALIB_GAIN_MASK GENMASK(5, 0) +#define AD7606_CALIB_OFFSET(ch) (0x11 + (ch)) +#define AD7606_CALIB_PHASE(ch) (0x19 + (ch)) + struct ad7606_state; =20 typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, @@ -61,6 +66,8 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_offset_avail: pointer to offset calibration range/limits array + * @calib_phase_avail: pointer to phase calibration range/limits array */ struct ad7606_chip_info { unsigned int max_samplerate; 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Acked-by: Conor Dooley Signed-off-by: Angelo Dureghello --- .../devicetree/bindings/iio/adc/adi,ad7606.yaml | 29 ++++++++++++++++++= ++++ 1 file changed, 29 insertions(+) diff --git a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml b/Do= cumentation/devicetree/bindings/iio/adc/adi,ad7606.yaml index 29f12d650442b8ff2eb455306ce59a0e87867ddd..6926f5f090ad6bbbe7bfd9327dc= 5ae17dafcd1fd 100644 --- a/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml +++ b/Documentation/devicetree/bindings/iio/adc/adi,ad7606.yaml @@ -204,6 +204,15 @@ patternProperties: considered a bipolar differential channel. Otherwise it is bipol= ar single-ended. =20 + adi,rfilter-ohms: + description: + For ADCs that supports gain calibration, this property must be s= et to + the value of the external RFilter resistor. Proper gain error + correction is applied based on this value. + default: 0 + minimum: 0 + maximum: 64512 + required: - reg - bipolar @@ -256,6 +265,25 @@ allOf: properties: adi,oversampling-ratio-gpios: false =20 + - if: + properties: + compatible: + contains: + enum: + - adi,ad7605-4 + - adi,ad7606-4 + - adi,ad7606-6 + - adi,ad7606-8 + - adi,ad7607 + - adi,ad7608 + - adi,ad7609 + - adi,ad7616 + then: + patternProperties: + "^channel@[0-9a-f]+$": + properties: + adi,rfilter-ohms: false + - if: properties: compatible: @@ -398,6 +426,7 @@ examples: reg =3D <8>; diff-channels =3D <8 8>; bipolar; + adi,rfilter-ohms =3D <2048>; }; =20 }; --=20 2.49.0 From nobody Mon Feb 9 09:23:04 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9609923C512 for ; Tue, 3 Jun 2025 14:38:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d7f1afebsm164430945e9.0.2025.06.03.07.37.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 07:37:59 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 03 Jun 2025 16:36:27 +0200 Subject: [PATCH v8 5/6] iio: adc: ad7606: exit for invalid fdt dt_schema properties Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-wip-bl-ad7606-calibration-v8-5-2371e7108f32@baylibre.com> References: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> In-Reply-To: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1153; i=adureghello@baylibre.com; h=from:subject:message-id; bh=rfCHNvDJGZ9CfpNWbsvNZme06fPzQKFo7DAhEkye3IU=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiw56gofpjWOk/92/TCQO2mBqUzHm9/yq3j6er66+rW+ 4ktv5e7o5SFQYyLQVZMkaUuMcIk9HaolPICxtkwc1iZQIYwcHEKwETOqTD8M/X8uefDpwPN9jU7 8zZvSHkZWG4Yx6dyT7t2M+cBY72fExh+MauesFcWCU6y/29m9/Vq//VX+X9kdondPsv3fZ4/k5Y 1NwA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Fix ad7606_get_chan_config() fdt parsing function to exit for error in case of invalid dt_schema values. Idea is to not proceed when there are values that are not allowed under the dt_schema. Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 10 ++++------ 1 file changed, 4 insertions(+), 6 deletions(-) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index 9a9bef0cfbb37138f71ba5b1babeaa423eaf4d5a..e0a666cc0e14255754e74daa9e1= e88bc4ad1665c 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -319,15 +319,13 @@ static int ad7606_get_chan_config(struct iio_dev *ind= io_dev, int ch, =20 ret =3D fwnode_property_read_u32(child, "reg", ®); if (ret) - continue; + return ret; =20 /* channel number (here) is from 1 to num_channels */ - if (reg < 1 || reg > num_channels) { - dev_warn(dev, - "Invalid channel number (ignoring): %d\n", reg); - continue; - } + if (reg < 1 || reg > num_channels) + return -EINVAL; =20 + /* Loop until we are in the right channel. */ if (reg !=3D (ch + 1)) continue; =20 --=20 2.49.0 From nobody Mon Feb 9 09:23:04 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 329E423D283 for ; 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[80.116.51.117]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d7f1afebsm164430945e9.0.2025.06.03.07.38.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 07:38:00 -0700 (PDT) From: Angelo Dureghello X-Google-Original-From: Angelo Dureghello Date: Tue, 03 Jun 2025 16:36:28 +0200 Subject: [PATCH v8 6/6] iio: adc: ad7606: add gain calibration support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-wip-bl-ad7606-calibration-v8-6-2371e7108f32@baylibre.com> References: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> In-Reply-To: <20250603-wip-bl-ad7606-calibration-v8-0-2371e7108f32@baylibre.com> To: Jonathan Cameron , David Lechner , =?utf-8?q?Nuno_S=C3=A1?= , Andy Shevchenko , Lars-Peter Clausen , Michael Hennerich , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-iio@vger.kernel.org, linux-kernel@vger.kernel.org, Michael Hennerich , devicetree@vger.kernel.org, Angelo Dureghello X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=6897; i=adureghello@baylibre.com; h=from:subject:message-id; bh=bvs8fIeq1nHwOu3c93up6s7Yw04NDFLuL8OghW12l8w=; b=owGbwMvMwCXGf3bn1e/btlsznlZLYsiw56i4/1h3Qrmg663V6t9KHtYLzn4Quv7X5r0xVWGHy nNdmb/kd5SyMIhxMciKKbLUJUaYhN4OlVJewDgbZg4rE8gQBi5OAZiIuzIjw9NLgfkZkt/5Hnl2 h4pGnoth5y5YManN8H+Mzd30ZUXBJxkZDt/4UTBP11ikzHY5s6WuZWdGb6tDwZ/PJ3Ys/bwyeDI TKwA= X-Developer-Key: i=adureghello@baylibre.com; a=openpgp; fpr=703CDFAD8B573EB00850E38366D1CB9419AF3953 From: Angelo Dureghello Add gain calibration support, using resistor values set on devicetree, values to be set accordingly with ADC external RFilter, as explained in the ad7606c-16 datasheet, rev0, page 37. Usage example in the fdt yaml documentation. Tested-by: David Lechner Reviewed-by: Nuno S=C3=A1 Signed-off-by: Angelo Dureghello --- drivers/iio/adc/ad7606.c | 66 ++++++++++++++++++++++++++++++++++++++++++++= ++++ drivers/iio/adc/ad7606.h | 6 +++++ 2 files changed, 72 insertions(+) diff --git a/drivers/iio/adc/ad7606.c b/drivers/iio/adc/ad7606.c index e0a666cc0e14255754e74daa9e1e88bc4ad1665c..22dcb52ced57d4305db6401605c= 064fc438d5be4 100644 --- a/drivers/iio/adc/ad7606.c +++ b/drivers/iio/adc/ad7606.c @@ -33,6 +33,10 @@ =20 #include "ad7606.h" =20 +#define AD7606_CALIB_GAIN_MIN 0 +#define AD7606_CALIB_GAIN_STEP 1024 +#define AD7606_CALIB_GAIN_MAX (63 * AD7606_CALIB_GAIN_STEP) + /* * Scales are computed as 5000/32768 and 10000/32768 respectively, * so that when applied to the raw values they provide mV values. @@ -125,6 +129,7 @@ static int ad7609_chan_scale_setup(struct iio_dev *indi= o_dev, struct iio_chan_spec *chan); static int ad7616_sw_mode_setup(struct iio_dev *indio_dev); static int ad7606b_sw_mode_setup(struct iio_dev *indio_dev); +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev); =20 const struct ad7606_chip_info ad7605_4_info =3D { .max_samplerate =3D 300 * KILO, @@ -180,6 +185,7 @@ const struct ad7606_chip_info ad7606b_info =3D { .scale_setup_cb =3D ad7606_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606b_calib_phase_avail, }; @@ -195,6 +201,7 @@ const struct ad7606_chip_info ad7606c_16_info =3D { .scale_setup_cb =3D ad7606c_16bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -246,6 +253,7 @@ const struct ad7606_chip_info ad7606c_18_info =3D { .scale_setup_cb =3D ad7606c_18bit_chan_scale_setup, .sw_setup_cb =3D ad7606b_sw_mode_setup, .offload_storagebits =3D 32, + .calib_gain_setup_cb =3D ad7606_chan_calib_gain_setup, .calib_offset_avail =3D ad7606c_18bit_calib_offset_avail, .calib_phase_avail =3D ad7606c_calib_phase_avail, }; @@ -355,6 +363,36 @@ static int ad7606_get_chan_config(struct iio_dev *indi= o_dev, int ch, return 0; } =20 +static int ad7606_chan_calib_gain_setup(struct iio_dev *indio_dev) +{ + struct ad7606_state *st =3D iio_priv(indio_dev); + unsigned int num_channels =3D st->chip_info->num_adc_channels; + struct device *dev =3D st->dev; + int ret; + + device_for_each_child_node_scoped(dev, child) { + u32 reg, r_gain; + + ret =3D fwnode_property_read_u32(child, "reg", ®); + if (ret) + return ret; + + /* Chan reg is a 1-based index. */ + if (reg < 1 || reg > num_channels) + return -EINVAL; + + r_gain =3D 0; + ret =3D fwnode_property_read_u32(child, "adi,rfilter-ohms", + &r_gain); + if (r_gain > AD7606_CALIB_GAIN_MAX) + return -EINVAL; + + st->r_gain[reg - 1] =3D r_gain; + } + + return 0; +} + static int ad7606c_18bit_chan_scale_setup(struct iio_dev *indio_dev, struct iio_chan_spec *chan) { @@ -1352,6 +1390,21 @@ static int ad7606b_sw_mode_setup(struct iio_dev *ind= io_dev) return st->bops->sw_mode_config(indio_dev); } =20 +static int ad7606_set_gain_calib(struct ad7606_state *st) +{ + int i, ret; + + for (i =3D 0; i < st->chip_info->num_adc_channels; i++) { + ret =3D st->bops->reg_write(st, AD7606_CALIB_GAIN(i), + DIV_ROUND_CLOSEST(st->r_gain[i], + AD7606_CALIB_GAIN_STEP)); + if (ret) + return ret; + } + + return 0; +} + static int ad7606_probe_channels(struct iio_dev *indio_dev) { struct ad7606_state *st =3D iio_priv(indio_dev); @@ -1444,6 +1497,13 @@ static int ad7606_probe_channels(struct iio_dev *ind= io_dev) if (slow_bus) channels[i] =3D (struct iio_chan_spec)IIO_CHAN_SOFT_TIMESTAMP(i); =20 + /* Getting gain calibration values for all channels. */ + if (st->sw_mode_en && st->chip_info->calib_gain_setup_cb) { + ret =3D st->chip_info->calib_gain_setup_cb(indio_dev); + if (ret) + return ret; + } + indio_dev->channels =3D channels; =20 return 0; @@ -1620,6 +1680,12 @@ int ad7606_probe(struct device *dev, int irq, void _= _iomem *base_address, st->chip_info->sw_setup_cb(indio_dev); } =20 + if (st->sw_mode_en && st->chip_info->calib_gain_setup_cb) { + ret =3D ad7606_set_gain_calib(st); + if (ret) + return ret; + } + return devm_iio_device_register(dev, indio_dev); } EXPORT_SYMBOL_NS_GPL(ad7606_probe, "IIO_AD7606"); diff --git a/drivers/iio/adc/ad7606.h b/drivers/iio/adc/ad7606.h index f613583a7fa4095115b0b28e3f8e51cd32b93524..a5b0d318e2f4d73d3708288536e= 807957c5de68c 100644 --- a/drivers/iio/adc/ad7606.h +++ b/drivers/iio/adc/ad7606.h @@ -50,6 +50,7 @@ struct ad7606_state; typedef int (*ad7606_scale_setup_cb_t)(struct iio_dev *indio_dev, struct iio_chan_spec *chan); typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio_dev); +typedef int (*ad7606_calib_gain_setup_cb_t)(struct iio_dev *indio_dev); =20 /** * struct ad7606_chip_info - chip specific information @@ -66,6 +67,7 @@ typedef int (*ad7606_sw_setup_cb_t)(struct iio_dev *indio= _dev); * @init_delay_ms: required delay in milliseconds for initialization * after a restart * @offload_storagebits: storage bits used by the offload hw implementation + * @calib_gain_setup_cb: callback to setup of gain calibration * @calib_offset_avail: pointer to offset calibration range/limits array * @calib_phase_avail: pointer to phase calibration range/limits array */ @@ -81,6 +83,7 @@ struct ad7606_chip_info { bool os_req_reset; unsigned long init_delay_ms; u8 offload_storagebits; + ad7606_calib_gain_setup_cb_t calib_gain_setup_cb; const int *calib_offset_avail; const int (*calib_phase_avail)[2]; }; @@ -131,6 +134,7 @@ struct ad7606_chan_scale { * @data: buffer for reading data from the device * @offload_en: SPI offload enabled * @bus_data: bus-specific variables + * @r_gain: array to store gain calibration resistor value in ohm * @d16: be16 buffer for reading data from the device */ struct ad7606_state { @@ -161,6 +165,8 @@ struct ad7606_state { bool offload_en; void *bus_data; =20 + int r_gain[AD760X_MAX_CHANNELS]; + /* * DMA (thus cache coherency maintenance) may require the * transfer buffers to live in their own cache lines. --=20 2.49.0