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Tue, 03 Jun 2025 00:11:21 -0700 (PDT) From: Jun Nie Date: Tue, 03 Jun 2025 15:10:07 +0800 Subject: [PATCH v11 08/12] drm/msm/dpu: Use dedicated WB number definition Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-v6-15-quad-pipe-upstream-v11-8-c3af7190613d@linaro.org> References: <20250603-v6-15-quad-pipe-upstream-v11-0-c3af7190613d@linaro.org> In-Reply-To: <20250603-v6-15-quad-pipe-upstream-v11-0-c3af7190613d@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748934620; l=1716; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=e1upM+aOdYliO/dIh1k3i/FkzXto3qmBjVI/19UomkE=; b=CgR/9p+yyw53c62J4hPQLpiSpKACzV7q2lWs+QQNgAMiZCDbEiDbtB3b+Dw7VJHj5NfLllHTF +027St0KrfsDn0M/IkAQ5jiVE64mIN5CYIH8SaWl6j4l0k0+akcU2Ws X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently MAX_CHANNELS_PER_ENC is defined as 2, because 2 channels are supported at most in one encoder. The case of 4 channels per encoder is to be added. To avoid breaking current WB usage case, use dedicated WB definition before 4 WB usage case is supported in future. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index be8102691b99d3b381476ff844ddfd28fe17dc7c..8b6fa7ef78e2c0fb38daef9090d= bf747c7ba111d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -56,6 +56,7 @@ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 #define MAX_CHANNELS_PER_ENC 2 +#define MAX_CWB_PER_ENC 2 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -182,7 +183,7 @@ struct dpu_encoder_virt { struct dpu_encoder_phys *cur_master; struct dpu_encoder_phys *cur_slave; struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC]; - struct dpu_hw_cwb *hw_cwb[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_cwb *hw_cwb[MAX_CWB_PER_ENC]; struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC]; =20 unsigned int dsc_mask; @@ -2377,7 +2378,7 @@ void dpu_encoder_helper_phys_setup_cwb(struct dpu_enc= oder_phys *phys_enc, */ cwb_cfg.input =3D INPUT_MODE_LM_OUT; =20 - for (int i =3D 0; i < MAX_CHANNELS_PER_ENC; i++) { + for (int i =3D 0; i < MAX_CWB_PER_ENC; i++) { hw_cwb =3D dpu_enc->hw_cwb[i]; if (!hw_cwb) continue; --=20 2.34.1