From nobody Tue Feb 10 09:10:59 2026 Received: from mail-pf1-f176.google.com (mail-pf1-f176.google.com [209.85.210.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0BD11269B07 for ; Tue, 3 Jun 2025 07:11:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.210.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748934697; cv=none; b=HsTgz4KYO4X7EdltP/SYvq34E3iw8C49DpUzkQFiIeRtBPIsbX4qC1mF1dojSzGkla9/4zDhmCldIWdMXjaJbIrmRwsP7wcFFm2sl0kyS8q0R6JXiN52zZ7o5RxaLK/Ujq0teoKDEVYTUFaBc+jwaKBmQBKOTq38uJBnO8Fnuwg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748934697; c=relaxed/simple; bh=FXOnL3R5uQl4eFOsJMlFc1wDdgAy74j9iSMVkIWJbCQ=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=D/OyIip2/cy9p99Rs0BEN28YA/sJ2pQXIlSoiOziWfLHgWLq72KwppM7x19wBoP6UXwm4fOeyQfo3Hfzoqa6mrGLSGHDnLZqrmHNC13NeRIpRTrzb0zr7y8vk1GscKsjJEGaPaMJ1Cw+fSWS6agH1BwkMpL7ue0lFldl+Wd/F14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=DlCqfhxz; arc=none smtp.client-ip=209.85.210.176 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="DlCqfhxz" Received: by mail-pf1-f176.google.com with SMTP id d2e1a72fcca58-7390d21bb1cso3662999b3a.2 for ; Tue, 03 Jun 2025 00:11:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748934695; x=1749539495; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=iqHkt4ZGNL+3tDYfg5V4rpXNLmwpH40P5PYVLkKSXx0=; b=DlCqfhxzUA3YtPm3QRdT8k1hzoaF8VinKuvoR4fMHATyMQ2PZDqy+Z2oe6LliBca7y ji/0E54LfT99/q6vSwQ50PCWn+nqn46SMUOT8qUKQT3HCQct2flLOLPdG+mNg526tGCK 3VtoXGw3P8IbFi0L/o7DAZ58Adoc3oIs5UPl3gd4lrSyLQqglyQg62Chqsa1vnmbSpQw CRgLUrAitlpxWSvtDQTWo936d2+GsbebV59dGMAWOt77wUE9AaUwzpHzWXikCDYDrjvx tlVwu+U5WFqnMRmPhnR5DUXyB5EfYhthOr0pfcA8XL1z0+yw2fFxOuZnR/UESjEZUUAx 0ftA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748934695; x=1749539495; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=iqHkt4ZGNL+3tDYfg5V4rpXNLmwpH40P5PYVLkKSXx0=; b=onhqw9jkR1QxFCpjLLiQgN/x1cGwwq7cP64gX0fcgz5dO9/hgKcCA/ymvhD5ZPsqQ1 dz/CQLqCGFw3CpVRAc6LU+NE9zrHnmsVSl2uxpguCeNnIkCzoiVaoDswOHqJZ6tOvjuG BHkn0Ty11zuU6uUEDeRSWZE0cqaCf+Kk4vIHxFECDWAiArc0ImKpmdPKMFbuRzPJw8mj F0iN0k9Ap7tpYOPgfbmwjHnRUtqGVxN3Z09F6GuDLwAyuMt/qA8t3K41S3B2ZPBGiuKs XCdfdfjJtTEzb7Bgk++htm9r9P6XAdBu5L32PkHs1GIfPfkxJTsA85Je6PwQ7EDuKe1e FiuQ== X-Forwarded-Encrypted: i=1; AJvYcCXgQlalC/ra5TPUOmsAYiTZjEGbpa1lMULmba4TYKqAdpbFimmsm3yV+FnXiGdx3Q8LR5DN0v7V6qZQ9dI=@vger.kernel.org X-Gm-Message-State: AOJu0YwLcIf+3+Ug6gcMbSFJKyc8Ecqj70p1l4TaWd1yCV6QaL4bvFWF BTl9aj3Q/EC1BPxhMbRWEBVLY210//eR7YaXDFVAr2yCnOeW3Tp8l51Y4JAolaYkWD0= X-Gm-Gg: ASbGncupVFl+IbDwPaftz1aARRlEalgVBBtAwzB4mqCMv3+frYe6mcDxu2h/rJGIDfw FTRU7hNETUdz+k9kLT0aJ0hJco1BMI4gf9kDXZvYXmdmPswA7H3PXFT590gPjOCFGhRi5KpUhiU NfbBlUveWVH8Ir08idhwlBQnF9PPGsWij0GB0QADZShx5K1HPyDvNM6J+UY2oTztm1VnMIWGJ+O kc8NK1u76CTQaQfT7OjOfAelNVVJs2v+mB9eWGSZtvKlDFktXmNMIoX2ebgqd46JR2k8bERQuvH uFowCoIcO1WkIMgFEasx5t70uZGbgk3Cw9g30dLbxs4JaEQedA== X-Google-Smtp-Source: AGHT+IE0cKN4aWF4OP9YolseV4jjv7hUddnD61d843Hi14zGR2S1e8YizkRfust+NhWy/7IseSjSMw== X-Received: by 2002:a05:6a00:88e:b0:73e:2d76:9eb1 with SMTP id d2e1a72fcca58-747bd96bb7bmr19774685b3a.10.1748934695360; Tue, 03 Jun 2025 00:11:35 -0700 (PDT) Received: from [127.0.1.1] ([104.234.225.11]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-747afed360fsm8746481b3a.81.2025.06.03.00.11.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 Jun 2025 00:11:34 -0700 (PDT) From: Jun Nie Date: Tue, 03 Jun 2025 15:10:09 +0800 Subject: [PATCH v11 10/12] drm/msm/dpu: support SSPP assignment for quad-pipe case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250603-v6-15-quad-pipe-upstream-v11-10-c3af7190613d@linaro.org> References: <20250603-v6-15-quad-pipe-upstream-v11-0-c3af7190613d@linaro.org> In-Reply-To: <20250603-v6-15-quad-pipe-upstream-v11-0-c3af7190613d@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Dmitry Baryshkov Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748934620; l=8402; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=FXOnL3R5uQl4eFOsJMlFc1wDdgAy74j9iSMVkIWJbCQ=; b=A+X5RbNoPpPyW5ruTW9xLFLeQaqnvoADN3UrmSrGA+gxp4NJj3Br1zf4ewa2A2HXZK8vun03n QLsoU/78T1qCZNXfWgeZa7FXBqwM9DfHYrP1JpUmEIKQvKw/Jm57oPL X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= Currently, SSPPs are assigned to a maximum of two pipes. However, quad-pipe usage scenarios require four pipes and involve configuring two stages. In quad-pipe case, the first two pipes share a set of mixer configurations and enable multi-rect mode when certain conditions are met. The same applies to the subsequent two pipes. Assign SSPPs to the pipes in each stage using a unified method and to loop the stages accordingly. Signed-off-by: Jun Nie --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 148 +++++++++++++++++++-------= ---- 1 file changed, 94 insertions(+), 54 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_plane.c index 0bb153a71353ca9eaca138ebbee4cd699414771d..501b6a1bad4a1fee832f15efa7c= aec136a669da5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -961,6 +961,33 @@ static int dpu_plane_is_multirect_parallel_capable(str= uct dpu_hw_sspp *sspp, dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth); } =20 +static bool dpu_plane_get_single_pipe(struct dpu_plane_state *pstate, + struct dpu_sw_pipe **single_pipe, + struct dpu_sw_pipe_cfg **single_pipe_cfg, + bool config_pipe) +{ + int i, valid_pipe =3D 0; + struct dpu_sw_pipe *pipe; + + for (i =3D 0; i < PIPES_PER_PLANE; i++) { + if (drm_rect_width(&pstate->pipe_cfg[i].src_rect) !=3D 0) { + valid_pipe++; + if (valid_pipe > 1) + return false; + *single_pipe =3D &pstate->pipe[i]; + *single_pipe_cfg =3D &pstate->pipe_cfg[i]; + } else { + if (!config_pipe) + continue; + pipe =3D &pstate->pipe[i]; + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + pipe->sspp =3D NULL; + } + } + + return true; +} =20 static int dpu_plane_atomic_check_sspp(struct drm_plane *plane, struct drm_atomic_state *state, @@ -1028,15 +1055,15 @@ static int dpu_plane_try_multirect_shared(struct dp= u_plane_state *pstate, const struct msm_format *fmt, uint32_t max_linewidth) { - struct dpu_sw_pipe *pipe =3D &pstate->pipe[0]; - struct dpu_sw_pipe *r_pipe =3D &pstate->pipe[1]; - struct dpu_sw_pipe_cfg *pipe_cfg =3D &pstate->pipe_cfg[0]; - struct dpu_sw_pipe *prev_pipe =3D &prev_adjacent_pstate->pipe[0]; - struct dpu_sw_pipe_cfg *prev_pipe_cfg =3D &prev_adjacent_pstate->pipe_cfg= [0]; + struct dpu_sw_pipe *pipe, *prev_pipe; + struct dpu_sw_pipe_cfg *pipe_cfg, *prev_pipe_cfg; const struct msm_format *prev_fmt =3D msm_framebuffer_format(prev_adjacen= t_pstate->base.fb); u16 max_tile_height =3D 1; =20 - if (prev_adjacent_pstate->pipe[1].sspp !=3D NULL || + if (!dpu_plane_get_single_pipe(pstate, &pipe, &pipe_cfg, true)) + return false; + + if (!dpu_plane_get_single_pipe(prev_adjacent_pstate, &prev_pipe, &prev_pi= pe_cfg, false) || prev_pipe->multirect_mode !=3D DPU_SSPP_MULTIRECT_NONE) return false; =20 @@ -1050,11 +1077,6 @@ static int dpu_plane_try_multirect_shared(struct dpu= _plane_state *pstate, if (MSM_FORMAT_IS_UBWC(prev_fmt)) max_tile_height =3D max(max_tile_height, prev_fmt->tile_height); =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->sspp =3D NULL; - if (dpu_plane_is_parallel_capable(pipe_cfg, fmt, max_linewidth) && dpu_plane_is_parallel_capable(prev_pipe_cfg, prev_fmt, max_linewidth)= && (pipe_cfg->dst_rect.x1 >=3D prev_pipe_cfg->dst_rect.x2 || @@ -1183,6 +1205,51 @@ static int dpu_plane_virtual_atomic_check(struct drm= _plane *plane, return 0; } =20 +static int dpu_plane_try_multirect_in_stage(struct dpu_sw_pipe *pipe, + struct dpu_sw_pipe_cfg *pipe_cfg, + struct drm_plane_state *plane_state, + struct dpu_global_state *global_state, + struct drm_crtc *crtc, + struct dpu_rm_sspp_requirements *reqs) +{ + struct drm_plane *plane =3D plane_state->plane; + struct dpu_kms *dpu_kms =3D _dpu_plane_get_kms(plane); + struct dpu_plane *pdpu =3D to_dpu_plane(plane); + struct dpu_sw_pipe *r_pipe =3D pipe + 1; + struct dpu_sw_pipe_cfg *r_pipe_cfg =3D pipe_cfg + 1; + int i; + + for (i =3D 0; i < PIPES_PER_STAGE; i++, pipe++, pipe_cfg++) { + if (drm_rect_width(&pipe_cfg->src_rect) =3D=3D 0) + continue; + + pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, req= s); + if (!pipe->sspp) + return -ENODEV; + + /* + * If current pipe is the first pipe in a stage, check + * multi-rect opportunity for the 2nd pipe in the stage. + * SSPP multi-rect mode cross stage is not supported. + */ + if (!i && + drm_rect_width(&r_pipe_cfg->src_rect) !=3D 0 && + dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, + pipe->sspp, + msm_framebuffer_format(plane_state->fb), + dpu_kms->catalog->caps->max_linewidth)) { + goto stage_assinged; + } else { + /* multirect is not possible, use dedicated SSPP */ + pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; + pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + } + } + +stage_assinged: + return 0; +} + static int dpu_plane_virtual_assign_resources(struct drm_crtc *crtc, struct dpu_global_state *global_state, struct drm_atomic_state *state, @@ -1195,11 +1262,9 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, struct dpu_rm_sspp_requirements reqs; struct dpu_plane_state *pstate, *prev_adjacent_pstate; struct dpu_sw_pipe *pipe; - struct dpu_sw_pipe *r_pipe; struct dpu_sw_pipe_cfg *pipe_cfg; - struct dpu_sw_pipe_cfg *r_pipe_cfg; const struct msm_format *fmt; - int i; + int i, stage_id, ret; =20 if (plane_state->crtc) crtc_state =3D drm_atomic_get_new_crtc_state(state, @@ -1209,11 +1274,6 @@ static int dpu_plane_virtual_assign_resources(struct= drm_crtc *crtc, prev_adjacent_pstate =3D prev_adjacent_plane_state ? to_dpu_plane_state(prev_adjacent_plane_state) : NULL; =20 - pipe =3D &pstate->pipe[0]; - r_pipe =3D &pstate->pipe[1]; - pipe_cfg =3D &pstate->pipe_cfg[0]; - r_pipe_cfg =3D &pstate->pipe_cfg[1]; - for (i =3D 0; i < PIPES_PER_PLANE; i++) pstate->pipe[i].sspp =3D NULL; =20 @@ -1227,44 +1287,24 @@ static int dpu_plane_virtual_assign_resources(struc= t drm_crtc *crtc, =20 reqs.rot90 =3D drm_rotation_90_or_270(plane_state->rotation); =20 - if (drm_rect_width(&r_pipe_cfg->src_rect) =3D=3D 0) { - if (!prev_adjacent_pstate || - !dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, - dpu_kms->catalog->caps->max_linewidth)) { - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &r= eqs); - if (!pipe->sspp) - return -ENODEV; - - r_pipe->sspp =3D NULL; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - } - } else { - pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, &re= qs); - if (!pipe->sspp) - return -ENODEV; - - if (!dpu_plane_try_multirect_parallel(pipe, pipe_cfg, r_pipe, r_pipe_cfg, - pipe->sspp, - msm_framebuffer_format(plane_state->fb), - dpu_kms->catalog->caps->max_linewidth)) { - /* multirect is not possible, use two SSPP blocks */ - r_pipe->sspp =3D dpu_rm_reserve_sspp(&dpu_kms->rm, global_state, crtc, = &reqs); - if (!r_pipe->sspp) - return -ENODEV; - - pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; + if (prev_adjacent_pstate && + dpu_plane_try_multirect_shared(pstate, prev_adjacent_pstate, fmt, + dpu_kms->catalog->caps->max_linewidth)) { + goto assigned; + } =20 - r_pipe->multirect_index =3D DPU_SSPP_RECT_SOLO; - r_pipe->multirect_mode =3D DPU_SSPP_MULTIRECT_NONE; - } + for (stage_id =3D 0; stage_id < STAGES_PER_PLANE; stage_id++) { + pipe =3D &pstate->pipe[stage_id * PIPES_PER_STAGE]; + pipe_cfg =3D &pstate->pipe_cfg[stage_id * PIPES_PER_STAGE]; + ret =3D dpu_plane_try_multirect_in_stage(pipe, pipe_cfg, + plane_state, + global_state, + crtc, &reqs); + if (ret) + return ret; } =20 +assigned: return dpu_plane_atomic_check_sspp(plane, state, crtc_state); } =20 --=20 2.34.1