From nobody Tue Dec 16 11:06:22 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A25332820A4; Tue, 3 Jun 2025 09:04:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748941490; cv=none; b=FvEPKGFUn7SbfOJbpe4NTJPuX1fVOksCrIplHTCK+1Tg7odHU6zdEdFk+/Ie/OwdSdFqvqeXCUvgJqg4iiYWvn36km6EEUW+aOuNUpafUD+AY40AlJ1KfZqbG3ZCPHAuG8HwWypREN4Y/s5HhsoqKsUlfnVqJeveTV7mlgTxj6s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748941490; c=relaxed/simple; bh=RiNNzpjPr4KjsTVDI6K9H5gGGthr+irdefBNKpncH+8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=GV2BTazaCpIppqtbvhtfxc/SBPpDVV6wq9bMB8TExGXpFOLMxdsq0ptsO3LNOfry7pVh+B1HMqzcBUD9YjeOPhNb9PubKWLURCr/OlLpIby64mp5GODpjnSkgEiD7WrNwRm28xdYczMbWIM21jCMSwHV7thNIA12Vujgh35cQPg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=P2z4eeXh; arc=none smtp.client-ip=185.132.182.106 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="P2z4eeXh" Received: from pps.filterd (m0288072.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5537vHVb008494; Tue, 3 Jun 2025 11:04:23 +0200 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= aprRrtcxOanHlGEgCXxPfxoWn2srMRb0/PvId8f/qLY=; b=P2z4eeXhhO95O0iB rkrijNzIBLH3xJ6OUbLTXy+XrDD8G9SaDh04hM/l9sifEbvvvWc3IJGaw4lNs7m0 QsysvaLj+xaGMIeT+llTgpamc8u3PAv8ZPMlESzzFGR8UunF00ElpHv6/UbkNfQE lnMRRdSHHLNatEwpBwOJe6IIGH+JzpgMUVmavdZMhrY0BOrSc5rtCI1tNHP83MHc YNqT+tT7Yint52KP+sPNrh+ulkTna+QeWevcG/vRwWtKOleZuCcQa78/wH7FyXwQ ajAVIWGD86KYZRj3AslePuZUj+VIzwCrLCJRUHMH87xdn4SnLKBYGTed3GGwaNpX 7EfUbw== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 471g8taywr-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Tue, 03 Jun 2025 11:04:23 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id CA4B840082; Tue, 3 Jun 2025 11:03:15 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 2CE546CF2C2; Tue, 3 Jun 2025 11:02:32 +0200 (CEST) Received: from localhost (10.48.87.237) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 3 Jun 2025 11:02:31 +0200 From: Amelie Delaunay Date: Tue, 3 Jun 2025 11:02:07 +0200 Subject: [PATCH v2 1/7] ARM: dts: stm32: fullfill diversity with OPP for STM32M15xF SOCs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250603-stm32mp157f-dk2-v2-1-5be0854a9299@foss.st.com> References: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> In-Reply-To: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Himanshu Bhavani X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-03_01,2025-06-02_01,2025-03-28_01 From: Alexandre Torgue This commit creates new file to manage security features and supported OPP on STM32MP15xF SOCs. On STM32MP15xY, "Y" gives information: -Y =3D A means no cryp IP and no secure boot + A7-CPU@650MHz. -Y =3D C means cryp IP + optee + secure boot + A7-CPU@650MHz. -Y =3D D means no cryp IP and no secure boot + A7-CPU@800MHz. -Y =3D F means cryp IP + optee + secure boot + A7-CPU@800MHz. It fullfills the initial STM32MP15x SoC diversity introduced by commit 0eda69b6c5f9 ("ARM: dts: stm32: Manage security diversity for STM32M15x SOCs"). Signed-off-by: Alexandre Torgue Signed-off-by: Amelie Delaunay --- Changes in v2: - Remove empty files (stm32mp15xa.dtsi and stm32mp15xd.dtsi) - Drop stm32mp15xc.dtsi updates (no stm32mp15xa.dtsi inclusion nor license update) - Move cryp1 node under etzpc firewall bus --- arch/arm/boot/dts/st/stm32mp15xf.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15xf.dtsi b/arch/arm/boot/dts/st/s= tm32mp15xf.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..ffa55d64bea30a67c32b9e378f3= a082acdae593c --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp15xf.dtsi @@ -0,0 +1,17 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Alexandre Torgue for STMicroelec= tronics. + */ + +&etzpc { + cryp1: cryp@54001000 { + compatible =3D "st,stm32mp1-cryp"; + reg =3D <0x54001000 0x400>; + interrupts =3D ; + clocks =3D <&rcc CRYP1>; + resets =3D <&rcc CRYP1_R>; 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Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi b/arch/arm/boot/dts/= st/stm32mp15xx-dkx.dtsi index a5511b1f0ce306feea5d8657721b078161d01a36..276ed2c9be71cc59891e9b06cb0= 57ce4ff8a143e 100644 --- a/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15xx-dkx.dtsi @@ -254,7 +254,7 @@ &i2c4 { /delete-property/dmas; /delete-property/dma-names; =20 - stusb1600@28 { + stusb1600: typec@28 { compatible =3D "st,stusb1600"; reg =3D <0x28>; interrupts =3D <11 IRQ_TYPE_LEVEL_LOW>; --=20 2.25.1 From nobody Tue Dec 16 11:06:22 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5FD342820A8; Tue, 3 Jun 2025 09:04:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 03 Jun 2025 11:04:30 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 74E5540080; Tue, 3 Jun 2025 11:03:15 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 9FAD76CF2C3; Tue, 3 Jun 2025 11:02:33 +0200 (CEST) Received: from localhost (10.48.87.237) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 3 Jun 2025 11:02:33 +0200 From: Amelie Delaunay Date: Tue, 3 Jun 2025 11:02:09 +0200 Subject: [PATCH v2 3/7] dt-bindings: regulator: Add STM32MP15 SCMI regulator identifiers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250603-stm32mp157f-dk2-v2-3-5be0854a9299@foss.st.com> References: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> In-Reply-To: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Himanshu Bhavani , Etienne Carriere , Pascal Paillet X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-03_01,2025-06-02_01,2025-03-28_01 From: Etienne Carriere These bindings will be used for the SCMI voltage domain. Signed-off-by: Etienne Carriere Signed-off-by: Pascal Paillet Signed-off-by: Amelie Delaunay Acked-by: Rob Herring (Arm) --- Changes in v2: - Add external regulators and Pascal's SoB --- .../dt-bindings/regulator/st,stm32mp15-regulator.h | 40 ++++++++++++++++++= ++++ 1 file changed, 40 insertions(+) diff --git a/include/dt-bindings/regulator/st,stm32mp15-regulator.h b/inclu= de/dt-bindings/regulator/st,stm32mp15-regulator.h new file mode 100644 index 0000000000000000000000000000000000000000..7052507cb3e509c6802d74682d7= f9700377fe7c7 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp15-regulator.h @@ -0,0 +1,40 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (C) 2025, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H + +/* SCMI voltage domain identifiers */ + +/* SOC Internal regulators */ +#define VOLTD_SCMI_REG11 0 +#define VOLTD_SCMI_REG18 1 +#define VOLTD_SCMI_USB33 2 + +/* STPMIC1 regulators */ +#define VOLTD_SCMI_STPMIC1_BUCK1 3 +#define VOLTD_SCMI_STPMIC1_BUCK2 4 +#define VOLTD_SCMI_STPMIC1_BUCK3 5 +#define VOLTD_SCMI_STPMIC1_BUCK4 6 +#define VOLTD_SCMI_STPMIC1_LDO1 7 +#define VOLTD_SCMI_STPMIC1_LDO2 8 +#define VOLTD_SCMI_STPMIC1_LDO3 9 +#define VOLTD_SCMI_STPMIC1_LDO4 10 +#define VOLTD_SCMI_STPMIC1_LDO5 11 +#define VOLTD_SCMI_STPMIC1_LDO6 12 +#define VOLTD_SCMI_STPMIC1_VREFDDR 13 +#define VOLTD_SCMI_STPMIC1_BOOST 14 +#define VOLTD_SCMI_STPMIC1_PWR_SW1 15 +#define VOLTD_SCMI_STPMIC1_PWR_SW2 16 +#define VOLTD_SCMI_VREFBUF 17 + +/* External regulators */ +#define VOLTD_SCMI_REGU0 18 +#define VOLTD_SCMI_REGU1 19 +#define VOLTD_SCMI_REGU2 20 +#define VOLTD_SCMI_REGU3 21 +#define VOLTD_SCMI_REGU4 22 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */ --=20 2.25.1 From nobody Tue Dec 16 11:06:22 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 74C9A2820B8; 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Tue, 03 Jun 2025 11:04:26 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 096D14007F; Tue, 3 Jun 2025 11:03:15 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 5B8916CEED4; Tue, 3 Jun 2025 11:02:34 +0200 (CEST) Received: from localhost (10.48.87.237) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 3 Jun 2025 11:02:34 +0200 From: Amelie Delaunay Date: Tue, 3 Jun 2025 11:02:10 +0200 Subject: [PATCH v2 4/7] ARM: dts: stm32: use internal regulators bindings for MP15 scmi variants Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250603-stm32mp157f-dk2-v2-4-5be0854a9299@foss.st.com> References: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> In-Reply-To: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Himanshu Bhavani X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-03_01,2025-06-02_01,2025-03-28_01 Use the SCMI voltage domain bindings for internal regulators on stm32mp15. Signed-off-by: Amelie Delaunay --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/s= t/stm32mp15-scmi.dtsi index dc3b09f2f2af21e991cac60dc8b5a09e7fc0d8be..2f3c42a11379655a97393d91cbf= 28c22c5bdf539 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -4,6 +4,8 @@ * Author: Alexandre Torgue for STMicroelec= tronics. */ =20 +#include + / { firmware { optee: optee { @@ -35,21 +37,21 @@ scmi_reguls: regulators { #size-cells =3D <0>; =20 scmi_reg11: regulator@0 { - reg =3D <0>; + reg =3D ; regulator-name =3D "reg11"; regulator-min-microvolt =3D <1100000>; regulator-max-microvolt =3D <1100000>; }; =20 scmi_reg18: regulator@1 { - reg =3D <1>; + reg =3D ; regulator-name =3D "reg18"; regulator-min-microvolt =3D <1800000>; regulator-max-microvolt =3D <1800000>; }; =20 scmi_usb33: regulator@2 { - reg =3D <2>; + reg =3D ; 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Signed-off-by: Etienne Carriere --- arch/arm/boot/dts/st/stm32mp15-scmi.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi b/arch/arm/boot/dts/s= t/stm32mp15-scmi.dtsi index 2f3c42a11379655a97393d91cbf28c22c5bdf539..98552fe45d4e088f749275cf352= 78de7b45b6c86 100644 --- a/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-scmi.dtsi @@ -11,6 +11,8 @@ firmware { optee: optee { compatible =3D "linaro,optee-tz"; method =3D "smc"; + interrupt-parent =3D <&intc>; + interrupts =3D ; }; =20 scmi: scmi { --=20 2.25.1 From nobody Tue Dec 16 11:06:22 2025 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D33EF281528; Tue, 3 Jun 2025 09:04:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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Tue, 03 Jun 2025 11:04:41 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 887A840060; Tue, 3 Jun 2025 11:03:23 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id D8E766CF2B2; Tue, 3 Jun 2025 11:02:35 +0200 (CEST) Received: from localhost (10.48.87.237) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 3 Jun 2025 11:02:35 +0200 From: Amelie Delaunay Date: Tue, 3 Jun 2025 11:02:12 +0200 Subject: [PATCH v2 6/7] dt-bindings: arm: stm32: add STM32MP157F-DK2 board compatible Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250603-stm32mp157f-dk2-v2-6-5be0854a9299@foss.st.com> References: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> In-Reply-To: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Himanshu Bhavani , Conor Dooley X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-03_01,2025-06-02_01,2025-03-28_01 From: Himanshu Bhavani Add the "st,stm32mp157f-dk2" compatible string to the STM32 SoC bindings. The MP157F is functionally similar to the MP157C. Acked-by: Conor Dooley Signed-off-by: Himanshu Bhavani Signed-off-by: Amelie Delaunay --- Documentation/devicetree/bindings/arm/stm32/stm32.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml b/Docum= entation/devicetree/bindings/arm/stm32/stm32.yaml index 408532504a24d5e570c738b16de30dcf8deead6a..ad144c02eb7edf4fc2191ab0af2= 44342dcaa59d5 100644 --- a/Documentation/devicetree/bindings/arm/stm32/stm32.yaml +++ b/Documentation/devicetree/bindings/arm/stm32/stm32.yaml @@ -121,6 +121,7 @@ properties: - st,stm32mp157a-dk1-scmi - st,stm32mp157c-dk2 - st,stm32mp157c-dk2-scmi + - st,stm32mp157f-dk2 - const: st,stm32mp157 =20 - items: --=20 2.25.1 From nobody Tue Dec 16 11:06:22 2025 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A86E3280CC8; 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Tue, 03 Jun 2025 11:04:25 +0200 (MEST) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id 4E73640058; Tue, 3 Jun 2025 11:03:19 +0200 (CEST) Received: from Webmail-eu.st.com (shfdag1node3.st.com [10.75.129.71]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id 996476CF2C8; Tue, 3 Jun 2025 11:02:36 +0200 (CEST) Received: from localhost (10.48.87.237) by SHFDAG1NODE3.st.com (10.75.129.71) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 3 Jun 2025 11:02:36 +0200 From: Amelie Delaunay Date: Tue, 3 Jun 2025 11:02:13 +0200 Subject: [PATCH v2 7/7] ARM: dts: stm32: add stm32mp157f-dk2 board support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250603-stm32mp157f-dk2-v2-7-5be0854a9299@foss.st.com> References: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> In-Reply-To: <20250603-stm32mp157f-dk2-v2-0-5be0854a9299@foss.st.com> To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , Liam Girdwood , Mark Brown CC: , , , , Amelie Delaunay , Himanshu Bhavani X-Mailer: b4 0.14.2 X-ClientProxiedBy: SHFCAS1NODE1.st.com (10.75.129.72) To SHFDAG1NODE3.st.com (10.75.129.71) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-06-03_01,2025-06-02_01,2025-03-28_01 STM32MP157F-DK2 board embeds a STM32MP157F SoC. This SoC contains the same level of feature than a STM32MP157C SOC but A7 clock frequency can reach 800MHz, hence the inclusion of the newly introduced stm32mp15xf.dtsi. As for other latest STM32 MPU families, STM32MP157F-DK2 relies on OP-TEE SCMI services for SoC clock and reset controllers resources, and for PMIC, now under OP-TEE control. That's why stm32mp157f-dk2-scmi.dtsi is introduced, to move all clocks, resets and regulators to SCMI-based ones. To "disable" SCMI, just need to comment stm32mp157f-dk2-scmi.dtsi inclusion and to replace &scmi_v3v3 with &v3v3, then to disable arm_wdt and to enable i2c4 and its subnodes for PMIC support by Linux. Reconfigure usbotg for dual role with type-C support if needed. Signed-off-by: Amelie Delaunay --- Changes in v2: - rename stm32mp157x-dk2-scmi.dtsi into stm32mp157f-dk2-scmi.dtsi - cleanup stm32mp157f-dk2-scmi.dtsi (remove comments and useless properties) - disable iwdg2 and add arm,smc-wdt watchdog in stm32mp157f-dk2-scmi.dtsi - set 32s timeout and enable arm_wdt - move (sort) stm32mp157f-dk2.dtb in Makefile --- arch/arm/boot/dts/st/Makefile | 3 +- arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi | 196 +++++++++++++++++++++= ++++ arch/arm/boot/dts/st/stm32mp157f-dk2.dts | 179 ++++++++++++++++++++++ 3 files changed, 377 insertions(+), 1 deletion(-) diff --git a/arch/arm/boot/dts/st/Makefile b/arch/arm/boot/dts/st/Makefile index cc9948b9870f7f73629573149bfd342af75b07da..66d4f96da5ddbba337c2f290512= a74b85e5c568e 100644 --- a/arch/arm/boot/dts/st/Makefile +++ b/arch/arm/boot/dts/st/Makefile @@ -72,7 +72,8 @@ dtb-$(CONFIG_ARCH_STM32) +=3D \ stm32mp157c-odyssey.dtb \ stm32mp157c-osd32mp1-red.dtb \ stm32mp157c-phycore-stm32mp1-3.dtb \ - stm32mp157c-ultra-fly-sbc.dtb + stm32mp157c-ultra-fly-sbc.dtb \ + stm32mp157f-dk2.dtb dtb-$(CONFIG_ARCH_U8500) +=3D \ ste-snowball.dtb \ ste-hrefprev60-stuib.dtb \ diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi b/arch/arm/boot= /dts/st/stm32mp157f-dk2-scmi.dtsi new file mode 100644 index 0000000000000000000000000000000000000000..89de85a2eff327f20336552692c= 833f5627cb6f7 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2-scmi.dtsi @@ -0,0 +1,196 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectr= onics. + */ + +#include "stm32mp15-scmi.dtsi" + +/ { + reserved-memory { + optee@de000000 { + reg =3D <0xde000000 0x2000000>; + no-map; + }; + }; + + arm_wdt: watchdog { + compatible =3D "arm,smc-wdt"; + arm,smc-id =3D <0xbc000000>; + status =3D "disabled"; + }; + +}; + +&adc { + vdd-supply =3D <&scmi_vdd>; + vdda-supply =3D <&scmi_vdd>; +}; + +&cpu0 { + clocks =3D <&scmi_clk CK_SCMI_MPU>; +}; + +&cpu1 { + clocks =3D <&scmi_clk CK_SCMI_MPU>; +}; + +&cryp1 { + clocks =3D <&scmi_clk CK_SCMI_CRYP1>; + resets =3D <&scmi_reset RST_SCMI_CRYP1>; +}; + +&cs42l51 { + VL-supply =3D <&scmi_v3v3>; + VD-supply =3D <&scmi_v1v8_audio>; + VA-supply =3D <&scmi_v1v8_audio>; + VAHP-supply =3D <&scmi_v1v8_audio>; +}; + +&dsi { + phy-dsi-supply =3D <&scmi_reg18>; + clocks =3D <&rcc DSI>, <&scmi_clk CK_SCMI_HSE>, <&rcc DSI_PX>; +}; + +&gpioz { + clocks =3D <&scmi_clk CK_SCMI_GPIOZ>; +}; + +&hash1 { + clocks =3D <&scmi_clk CK_SCMI_HASH1>; + resets =3D <&scmi_reset RST_SCMI_HASH1>; +}; + +&i2c1 { + hdmi-transmitter@39 { + iovcc-supply =3D <&scmi_v3v3_hdmi>; + cvcc12-supply =3D <&scmi_v1v2_hdmi>; + }; +}; + +&iwdg2 { + clocks =3D <&rcc IWDG2>, <&scmi_clk CK_SCMI_LSI>; + status =3D "disabled"; +}; + +&m4_rproc { + /delete-property/ st,syscfg-holdboot; + resets =3D <&scmi_reset RST_SCMI_MCU>, + <&scmi_reset RST_SCMI_MCU_HOLD_BOOT>; + reset-names =3D "mcu_rst", "hold_boot"; +}; + +&mdma1 { + resets =3D <&scmi_reset RST_SCMI_MDMA>; +}; + +&optee { + interrupt-parent =3D <&intc>; + interrupts =3D ; +}; + +&pwr_regulators { + vdd-supply =3D <&scmi_vdd>; + vdd_3v3_usbfs-supply =3D <&scmi_vdd_usb>; + status =3D "disabled"; +}; + +&rcc { + compatible =3D "st,stm32mp1-rcc-secure", "syscon"; + clock-names =3D "hse", "hsi", "csi", "lse", "lsi"; + clocks =3D <&scmi_clk CK_SCMI_HSE>, + <&scmi_clk CK_SCMI_HSI>, + <&scmi_clk CK_SCMI_CSI>, + <&scmi_clk CK_SCMI_LSE>, + <&scmi_clk CK_SCMI_LSI>; +}; + +&rng1 { + clocks =3D <&scmi_clk CK_SCMI_RNG1>; + resets =3D <&scmi_reset RST_SCMI_RNG1>; +}; + +&rtc { + clocks =3D <&scmi_clk CK_SCMI_RTCAPB>, <&scmi_clk CK_SCMI_RTC>; +}; + +&scmi_reguls { + scmi_vddcore: regulator@3 { + reg =3D ; + regulator-name =3D "vddcore"; + }; + + scmi_vdd: regulator@5 { + reg =3D ; + regulator-name =3D "vdd"; + }; + + scmi_v3v3: regulator@6 { + reg =3D ; + regulator-name =3D "v3v3"; + }; + + scmi_v1v8_audio: regulator@7 { + reg =3D ; + regulator-name =3D "v1v8_audio"; + }; + + scmi_v3v3_hdmi: regulator@8 { + reg =3D ; + regulator-name =3D "v3v3_hdmi"; + }; + + scmi_vdd_usb: regulator@a { + reg =3D ; + regulator-name =3D "vdd_usb"; + }; + + scmi_vdda: regulator@b { + reg =3D ; + regulator-name =3D "vdda"; + }; + + scmi_v1v2_hdmi: regulator@c { + reg =3D ; + regulator-name =3D "v1v2_hdmi"; + regulator-min-microvolt =3D <1200000>; + regulator-max-microvolt =3D <1200000>; + regulator-always-on; + }; + + scmi_vbus_otg: regulator@f { + reg =3D ; + regulator-name =3D "vbus_otg"; + }; + + scmi_vbus_sw: regulator@10 { + reg =3D ; + regulator-name =3D "vbus_sw"; + }; +}; + +&sdmmc1 { + vmmc-supply =3D <&scmi_v3v3>; +}; + +&sdmmc3 { + vmmc-supply =3D <&scmi_v3v3>; +}; + +&usbh_ehci { + hub@1 { + vdd-supply =3D <&scmi_v3v3>; + }; +}; + +&usbphyc_port0 { + phy-supply =3D <&scmi_vdd_usb>; +}; + +&usbphyc_port1 { + phy-supply =3D <&scmi_vdd_usb>; +}; + +&vrefbuf { + vdda-supply =3D <&scmi_vdd>; +}; diff --git a/arch/arm/boot/dts/st/stm32mp157f-dk2.dts b/arch/arm/boot/dts/s= t/stm32mp157f-dk2.dts new file mode 100644 index 0000000000000000000000000000000000000000..43375c4d62a3cd07609a99b91be= 42f87f3f4ed96 --- /dev/null +++ b/arch/arm/boot/dts/st/stm32mp157f-dk2.dts @@ -0,0 +1,179 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2025 - All Rights Reserved + * Author: Amelie Delaunay for STMicroelectr= onics. + */ + +/dts-v1/; + +#include "stm32mp157.dtsi" +#include "stm32mp15xf.dtsi" +#include "stm32mp15-pinctrl.dtsi" +#include "stm32mp15xxac-pinctrl.dtsi" +#include "stm32mp15xx-dkx.dtsi" +#include "stm32mp157f-dk2-scmi.dtsi" + +/ { + model =3D "STMicroelectronics STM32MP157F-DK2 Discovery Board"; + compatible =3D "st,stm32mp157f-dk2", "st,stm32mp157"; + + aliases { + ethernet0 =3D ðernet0; + serial3 =3D &usart2; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + wifi_pwrseq: wifi-pwrseq { + compatible =3D "mmc-pwrseq-simple"; + reset-gpios =3D <&gpioh 4 GPIO_ACTIVE_LOW>; + }; +}; + +&arm_wdt { + timeout-sec =3D <32>; + status =3D "okay"; +}; + +&cryp1 { + status =3D "okay"; +}; + +&dsi { + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + panel@0 { + compatible =3D "orisetech,otm8009a"; + reg =3D <0>; + reset-gpios =3D <&gpioe 4 GPIO_ACTIVE_LOW>; + power-supply =3D <&scmi_v3v3>; + status =3D "okay"; + + port { + panel_in: endpoint { + remote-endpoint =3D <&dsi_out>; + }; + }; + }; +}; + +&dsi_in { + remote-endpoint =3D <<dc_ep1_out>; +}; + +&dsi_out { + remote-endpoint =3D <&panel_in>; +}; + +&i2c1 { + touchscreen@38 { + compatible =3D "focaltech,ft6236"; + reg =3D <0x38>; + interrupts =3D <2 IRQ_TYPE_EDGE_FALLING>; + interrupt-parent =3D <&gpiof>; + touchscreen-size-x =3D <480>; + touchscreen-size-y =3D <800>; + status =3D "okay"; + }; +}; + +/* I2C4 is managed by OP-TEE */ +&i2c4 { + status =3D "disabled"; + + /* i2c4 subnodes, which won't be managed by Linux */ + typec@28 { + status =3D "disabled"; + connector { + status =3D "disabled"; + }; + }; + + stpmic@33 { + status =3D "disabled"; + }; +}; + +<dc { + status =3D "okay"; + + port { + #address-cells =3D <1>; + #size-cells =3D <0>; + + ltdc_ep1_out: endpoint@1 { + reg =3D <1>; + remote-endpoint =3D <&dsi_in>; + }; + }; +}; + +&rtc { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_rsvd_pins_a>; + + rtc_lsco_pins_a: rtc-lsco-0 { + pins =3D "out2_rmp"; + function =3D "lsco"; + }; +}; + +/* Wifi */ +&sdmmc2 { + pinctrl-names =3D "default", "opendrain", "sleep"; + pinctrl-0 =3D <&sdmmc2_b4_pins_a>; + pinctrl-1 =3D <&sdmmc2_b4_od_pins_a>; + pinctrl-2 =3D <&sdmmc2_b4_sleep_pins_a>; + non-removable; + cap-sdio-irq; + st,neg-edge; + bus-width =3D <4>; + vmmc-supply =3D <&scmi_v3v3>; + mmc-pwrseq =3D <&wifi_pwrseq>; + #address-cells =3D <1>; + #size-cells =3D <0>; + status =3D "okay"; + + brcmf: wifi@1 { + reg =3D <1>; + compatible =3D "brcm,bcm4329-fmac"; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&rtc_lsco_pins_a>; + }; +}; + +/* Bluetooth */ +&usart2 { + pinctrl-names =3D "default", "sleep", "idle"; + pinctrl-0 =3D <&usart2_pins_c>; + pinctrl-1 =3D <&usart2_sleep_pins_c>; + pinctrl-2 =3D <&usart2_idle_pins_c>; + uart-has-rtscts; + status =3D "okay"; + + bluetooth { + shutdown-gpios =3D <&gpioz 6 GPIO_ACTIVE_HIGH>; + compatible =3D "brcm,bcm43438-bt"; + max-speed =3D <3000000>; + vbat-supply =3D <&scmi_v3v3>; + vddio-supply =3D <&scmi_v3v3>; + }; +}; + +/* Since I2C4 is disabled, STUSB1600 is also disabled so there is no Type-= C support */ +&usbotg_hs { + dr_mode =3D "peripheral"; + role-switch-default-mode =3D "peripheral"; + /* + * Forcing dr_mode =3D "peripheral"/"role-switch-default-mode =3D "periph= eral"; + * will cause the pull-up on D+/D- to be raised as soon as the OTG is con= figured at runtime, + * regardless of the presence of VBUS. Notice that on self-powered device= s like + * stm32mp157f-dk2, this isn't compliant with the USB standard. That's wh= y usbotg_hs is kept + * disabled here. + */ + status =3D "disabled"; +}; --=20 2.25.1