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AJvYcCUZ0irhp5UpNuna0Dk7R3KiKaZ7jk0HxVMrCH45aBktt3Mb0z4K9fV+Fj3WmtsjTU84IRu5Zyn69UCpNdI=@vger.kernel.org X-Gm-Message-State: AOJu0YyrW/b78/4mBfpWHrE96PjXA2bbH6EA6slFEDLoartrlnJf3ZoD M1ahcxDwJqU5dk15wvYEP78wtpQcPWkbIPJ0IJMukT5XWgH9ORIGpmrAlJuPwQJvqHNs81QDK4s De66LVQLW9DPZgfM/fGkUozfR1w== X-Google-Smtp-Source: AGHT+IFMVeKyETkycXmBUpASHlOBIqAlJOgdAa/bpyVkcS9jV+S6qkzUphiHGfVK6q8KTzMSYrzDWRGuInC2fMT41A== X-Received: from ilbbk6.prod.google.com ([2002:a05:6e02:3286:b0:3dd:b580:4100]) (user=coltonlewis job=prod-delivery.src-stubby-dispatcher) by 2002:a05:6e02:4515:10b0:3dd:b5c6:421f with SMTP id e9e14a558f8ab-3ddb5c642c8mr13690965ab.6.1748892547783; Mon, 02 Jun 2025 12:29:07 -0700 (PDT) Date: Mon, 2 Jun 2025 19:26:55 +0000 In-Reply-To: <20250602192702.2125115-1-coltonlewis@google.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20250602192702.2125115-1-coltonlewis@google.com> X-Mailer: git-send-email 2.49.0.1204.g71687c7c1d-goog Message-ID: <20250602192702.2125115-11-coltonlewis@google.com> Subject: [PATCH 10/17] KVM: arm64: Writethrough trapped PMEVTYPER register From: Colton Lewis To: kvm@vger.kernel.org Cc: Paolo Bonzini , Jonathan Corbet , Russell King , Catalin Marinas , Will Deacon , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mark Rutland , Shuah Khan , linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-perf-users@vger.kernel.org, linux-kselftest@vger.kernel.org, Colton Lewis Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" With FGT in place, the remaining trapped registers need to be written through to the underlying physical registers as well as the virtual ones. Failing to do this means delaying when guest writes take effect. Signed-off-by: Colton Lewis --- arch/arm64/kvm/sys_regs.c | 27 +++++++++++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index d368eeb4f88e..afd06400429a 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -18,6 +18,7 @@ #include #include #include +#include #include =20 #include @@ -942,7 +943,11 @@ static bool pmu_counter_idx_valid(struct kvm_vcpu *vcp= u, u64 idx) { u64 pmcr, val; =20 - pmcr =3D kvm_vcpu_read_pmcr(vcpu); + if (kvm_vcpu_pmu_is_partitioned(vcpu)) + pmcr =3D read_pmcr(); + else + pmcr =3D kvm_vcpu_read_pmcr(vcpu); + val =3D FIELD_GET(ARMV8_PMU_PMCR_N, pmcr); if (idx >=3D val && idx !=3D ARMV8_PMU_CYCLE_IDX) { kvm_inject_undefined(vcpu); @@ -1037,6 +1042,22 @@ static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, return true; } =20 +static void writethrough_pmevtyper(struct kvm_vcpu *vcpu, struct sys_reg_p= arams *p, + u64 reg, u64 idx) +{ + u64 evmask =3D kvm_pmu_evtyper_mask(vcpu->kvm); + u64 val =3D p->regval & evmask; + + __vcpu_sys_reg(vcpu, reg) =3D val; + + if (idx =3D=3D ARMV8_PMU_CYCLE_IDX) + write_pmccfiltr(val); + else if (idx =3D=3D ARMV8_PMU_INSTR_IDX) + write_pmicfiltr(val); + else + write_pmevtypern(idx, val); +} + static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_param= s *p, const struct sys_reg_desc *r) { @@ -1063,7 +1084,9 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,= struct sys_reg_params *p, if (!pmu_counter_idx_valid(vcpu, idx)) return false; =20 - if (p->is_write) { + if (kvm_vcpu_pmu_is_partitioned(vcpu) && p->is_write) { + writethrough_pmevtyper(vcpu, p, reg, idx); + } else if (p->is_write) { kvm_pmu_set_counter_event_type(vcpu, p->regval, idx); kvm_vcpu_pmu_restore_guest(vcpu); } else { --=20 2.49.0.1204.g71687c7c1d-goog