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[141.95.202.232]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-747afeabb13sm7717558b3a.62.2025.06.02.05.15.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 02 Jun 2025 05:15:48 -0700 (PDT) From: Alexandre Ghiti To: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Cyril Bur , Andy Chiu , Deepak Gupta , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Cc: Alexandre Ghiti Subject: [PATCH v2] riscv: uaccess: Only restore the CSR_STATUS SUM bit Date: Mon, 2 Jun 2025 12:15:43 +0000 Message-Id: <20250602121543.1544278-1-alexghiti@rivosinc.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=3042; i=alexghiti@rivosinc.com; h=from:subject; bh=QR8/6bas1i5/uuucvXOTT2dS9uCkrhYuqeChIu397zo=; b=owGbwMvMwCGWYr9pz6TW912Mp9WSGDJsp+7xv/FpyfOAyAnx+5OMt+/98OSGzSqedU4xBxXyo 5Wby3k7OkpZGMQ4GGTFFFkUzBO6WuzP1s/+c+k9zBxWJpAhDFycAjARt7cM/9O2tifwbXyTkmtz 9+b3FbHNsYuPnG9dGuKhfeGWlMOdN74M/2Nk7k89Zhv07Zbim+9Lnxz4HH3p1Ub2nULFb+QzyyX 3ObMDAA== X-Developer-Key: i=alexghiti@rivosinc.com; a=openpgp; fpr=DC049C97114ED82152FE79A783E4BA75438E93E3 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Cyril Bur During switch to csrs will OR the value of the register into the corresponding csr. In this case we're only interested in restoring the SUM bit not the entire register. Fixes: 788aa64c0c01 ("riscv: save the SR_SUM status over switches") Signed-off-by: Cyril Bur Link: https://lore.kernel.org/r/20250522160954.429333-1-cyrilbur@tenstorren= t.com Co-developed-by: Alexandre Ghiti Signed-off-by: Alexandre Ghiti --- Changes in v2: - Rename status field - Remove a comment - Fix Fixes tag arch/riscv/include/asm/processor.h | 2 +- arch/riscv/kernel/asm-offsets.c | 6 +++--- arch/riscv/kernel/entry.S | 9 +++++---- 3 files changed, 9 insertions(+), 8 deletions(-) diff --git a/arch/riscv/include/asm/processor.h b/arch/riscv/include/asm/pr= ocessor.h index 7bcbb908798f2..05eb65fe95789 100644 --- a/arch/riscv/include/asm/processor.h +++ b/arch/riscv/include/asm/processor.h @@ -111,7 +111,7 @@ struct thread_struct { struct __riscv_d_ext_state fstate; unsigned long bad_cause; unsigned long envcfg; - unsigned long status; + unsigned long sum; u32 riscv_v_flags; u32 vstate_ctrl; struct __riscv_v_ext_state vstate; diff --git a/arch/riscv/kernel/asm-offsets.c b/arch/riscv/kernel/asm-offset= s.c index 3aa5f56a84e9a..e4d55126dc3eb 100644 --- a/arch/riscv/kernel/asm-offsets.c +++ b/arch/riscv/kernel/asm-offsets.c @@ -34,7 +34,7 @@ void asm_offsets(void) OFFSET(TASK_THREAD_S9, task_struct, thread.s[9]); OFFSET(TASK_THREAD_S10, task_struct, thread.s[10]); OFFSET(TASK_THREAD_S11, task_struct, thread.s[11]); - OFFSET(TASK_THREAD_STATUS, task_struct, thread.status); + OFFSET(TASK_THREAD_SUM, task_struct, thread.sum); =20 OFFSET(TASK_TI_CPU, task_struct, thread_info.cpu); OFFSET(TASK_TI_PREEMPT_COUNT, task_struct, thread_info.preempt_count); @@ -351,8 +351,8 @@ void asm_offsets(void) offsetof(struct task_struct, thread.s[11]) - offsetof(struct task_struct, thread.ra) ); - DEFINE(TASK_THREAD_STATUS_RA, - offsetof(struct task_struct, thread.status) + DEFINE(TASK_THREAD_SUM_RA, + offsetof(struct task_struct, thread.sum) - offsetof(struct task_struct, thread.ra) ); =20 diff --git a/arch/riscv/kernel/entry.S b/arch/riscv/kernel/entry.S index d3cb515fb1596..77e334f7cbe4b 100644 --- a/arch/riscv/kernel/entry.S +++ b/arch/riscv/kernel/entry.S @@ -427,14 +427,15 @@ SYM_FUNC_START(__switch_to) REG_S s11, TASK_THREAD_S11_RA(a3) =20 /* save the user space access flag */ - li s0, SR_SUM - csrr s1, CSR_STATUS - REG_S s1, TASK_THREAD_STATUS_RA(a3) + csrr s0, CSR_STATUS + REG_S s0, TASK_THREAD_SUM_RA(a3) =20 /* Save the kernel shadow call stack pointer */ scs_save_current /* Restore context from next->thread */ - REG_L s0, TASK_THREAD_STATUS_RA(a4) + REG_L s0, TASK_THREAD_SUM_RA(a4) + li s1, SR_SUM + and s0, s0, s1 csrs CSR_STATUS, s0 REG_L ra, TASK_THREAD_RA_RA(a4) REG_L sp, TASK_THREAD_SP_RA(a4) --=20 2.34.1