From nobody Tue Oct 7 10:17:07 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D00B71AAA1D for ; Mon, 2 Jun 2025 06:09:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748844545; cv=none; b=cBHduxO7KfYnbLZlRI3COKy34HNIDmkpeMhlfz290WOBEufqw3zqUaJPtyD/XBeYr22Cgq5ahkjhkeLXGUK2vWZGqFU1tGFkfJPn93tOTZ1rWPeK3ahDjSF5Y9ognBWcBhO0DVND3KvvdgwUTYJPacQPiXvYuW+I3Ne3vexETVw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748844545; c=relaxed/simple; bh=nm54TMUcRYIAPqYH3hllnzIl0n9PJUYqWR00cVuBRxU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=JUHYUiVGDP02D34kuMfqLhzbmoqcKOs4ZC0ojxQxIIPhTqOyPcRoZgFzYN11Mwd42hlP0VY68qYrEJIVzPquiN4GWsS6fh2ngF0jHxdKtsDN2UMBl3p8aNNMw6xWwHBKlYypoHbRnf5DqoALY4bbL8lHO7QiwcIQKuvX0UoXQVQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 552684It096309 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 2 Jun 2025 14:08:04 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 2 Jun 2025 14:08:04 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie , Conor Dooley Subject: [PATCH v5 8/8] riscv: defconfig: enable Andes SoC Date: Mon, 2 Jun 2025 14:07:47 +0800 Message-ID: <20250602060747.689824-9-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602060747.689824-1-ben717@andestech.com> References: <20250602060747.689824-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 552684It096309 Content-Type: text/plain; charset="utf-8" Enable Andes SoC config in defconfig to allow the default upstream kernel to boot on Voyager board. Acked-by: Conor Dooley Signed-off-by: Ben Zong-You Xie --- arch/riscv/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/configs/defconfig b/arch/riscv/configs/defconfig index 3c8e16d71e17..c9214635fb2f 100644 --- a/arch/riscv/configs/defconfig +++ b/arch/riscv/configs/defconfig @@ -25,6 +25,7 @@ CONFIG_BLK_DEV_INITRD=3Dy CONFIG_EXPERT=3Dy # CONFIG_SYSFS_SYSCALL is not set CONFIG_PROFILING=3Dy +CONFIG_ARCH_ANDES=3Dy CONFIG_ARCH_MICROCHIP=3Dy CONFIG_ARCH_SIFIVE=3Dy CONFIG_ARCH_SOPHGO=3Dy --=20 2.34.1