From nobody Tue Oct 7 10:15:41 2025 Received: from Atcsqr.andestech.com (60-248-80-70.hinet-ip.hinet.net [60.248.80.70]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA84215CD74 for ; Mon, 2 Jun 2025 06:08:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.248.80.70 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748844492; cv=none; b=rfCvam4CAP93eAEzuizUd1YUgSMMyvFkFZIlo6eH4LU4yI6JPiYKIY5FRABxwEd1Yg+OW00RyP1N5g6ytaYZYnKLvoPEKOpAQ1y7LkA+HnJOfRL+7ZGE0F6BQ2f0MIqrLV+I4ktSoYWXUKUb57VeGXa5lzfVhtwiD6M9CVG3nfc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748844492; c=relaxed/simple; bh=zfl/DujTII3ytNn/NJszdtb6aPj8qKUZQIPwANwmzMM=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=YYGgqb91J5zO9QlYulSoqWdxnm2qliVgVtcv5GmBqc0Y+EWUwFPF35O1s132IZZEYY1O67CQBQ5mCzfZxzWgx+qmwJMOMEyjQncLg/YwEAMd6wRbja75ZvNqfihQ9ZpxFn6+WPIDmFCh/z3XNhqq0QExujDciLTgqts+ZQZbkaM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com; spf=pass smtp.mailfrom=andestech.com; arc=none smtp.client-ip=60.248.80.70 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=andestech.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=andestech.com Received: from mail.andestech.com (ATCPCS31.andestech.com [10.0.1.89]) by Atcsqr.andestech.com with ESMTPS id 55267uDC096172 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Mon, 2 Jun 2025 14:07:56 +0800 (+08) (envelope-from ben717@andestech.com) Received: from swlinux02.andestech.com (10.0.15.183) by ATCPCS31.andestech.com (10.0.1.89) with Microsoft SMTP Server id 14.3.498.0; Mon, 2 Jun 2025 14:07:56 +0800 From: Ben Zong-You Xie To: CC: , , , , , , , , , , , , , , Ben Zong-You Xie Subject: [PATCH v5 3/8] dt-bindings: interrupt-controller: add Andes QiLai PLIC Date: Mon, 2 Jun 2025 14:07:42 +0800 Message-ID: <20250602060747.689824-4-ben717@andestech.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250602060747.689824-1-ben717@andestech.com> References: <20250602060747.689824-1-ben717@andestech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-DKIM-Results: atcpcs31.andestech.com; dkim=none; X-DNSRBL: X-SPAM-SOURCE-CHECK: pass X-MAIL: Atcsqr.andestech.com 55267uDC096172 Content-Type: text/plain; charset="utf-8" Add a new compatible string for Andes QiLai PLIC. Acked-by: Rob Herring (Arm) Signed-off-by: Ben Zong-You Xie --- .../bindings/interrupt-controller/sifive,plic-1.0.0.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sifive,= plic-1.0.0.yaml b/Documentation/devicetree/bindings/interrupt-controller/si= five,plic-1.0.0.yaml index 3dfe425909d1..7ae61518e9b7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sifive,plic-1.= 0.0.yaml @@ -53,6 +53,7 @@ properties: oneOf: - items: - enum: + - andestech,qilai-plic - renesas,r9a07g043-plic - const: andestech,nceplic100 - items: --=20 2.34.1