From nobody Mon Feb 9 08:15:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CB5141E5B93; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858005; cv=none; b=MRS4au5FZk6mV6EdipVP4utq6C9zIPJ4BfjYWnadVK+TThARBnJApab/bElDcbUWUmCtwLPP4LKLYn4dwgIfL9tlXuS6Afi4zyG9Zwh+q2WNCbSo9lhAyvaKQ7oY++5l6kFh+8zhLnzFjt43gS4impJmcZfQkqHml+3hpOu2TCM= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858005; c=relaxed/simple; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=BMTAQrtTOwe/YDR4NGAQjlwgvXsenpkUx6XNjO68soJ65XtitV3tH24XHoVaXugG7RKrweZ4nCm4pddQSAxVb+jnlkm4ZFFnpD5ByxiwYHH/d818nexB40OyCF82EfuVbvAhrVF9vYlVhGXBl7fo+ajCqvylzqbYhtd8AkEOi6E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=lBCM0S0y; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="lBCM0S0y" Received: by smtp.kernel.org (Postfix) with ESMTPS id 4E91EC4CEED; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748858005; bh=8Y2htiPy5meWxzHXQzhyzo1AQtbeIgcyev3Yn6FKh6Q=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=lBCM0S0y/D4P0m0kmcOJUOickcrkT+90ogntcc8NUdYaVip2sKZ27Ai+mbTplj1a2 +pZGDzxDHFyGcqTTTj9ZG0cFGSzk/au2N3INE57f5X3DVxSsCjcR2sUyKibqVLfI8h etYivN9iY03b/S3CA7t5kEGbKg/antLlrfwyPeHE/rjGPbDH6x2Ol3tWPVJ5VgwclI V2pth6CfJ8ThAdNHaGBPiCYr/kBnlCdxuFmp8mV9qEIjg6bFvaQaf4VZ7X7S9Fq7xM ZM+O1FrOdmShf3ioWMWsddq0LPkyr5ZE9BVc/NreaOqaBKA+WzKU6mLovDUrFNySqj TJ3lKTC8HqwDw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 41B95C5B549; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 02 Jun 2025 13:53:13 +0400 Subject: [PATCH v3 1/5] clk: qcom: gcc-ipq5018: fix GE PHY reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250602-ipq5018-ge-phy-v3-1-421337a031b2@outlook.com> References: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> In-Reply-To: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748858002; l=1220; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=y65n0Od6u+x9wP3HKotpTyPdgu84le/dyFb7G8W0t/E=; b=J6i0CeRvA6g5yfnnvPEPnspy0W4sPcvgdG5EcbLeQhgXVqwXY1YIytvnXRH869FgzGyuuCWa3 AxNKZ38L9DvAw7yZdgy63eo6MBHB863p9FcohFqR+evggmHPFCtpVz7 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit= /00743c3e82fa87cba4460e7a2ba32f473a9ce932 Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..6eb86c034fda18c38dcd9726f09= 03841252381da 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets= [] =3D { [GCC_WCSS_AXI_S_ARES] =3D { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] =3D { 0x18004, 0 }, [GCC_WCSSAON_RESET] =3D { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] =3D { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] =3D { 0x56004, .bitmask =3D GENMASK(3, 0) }, }; =20 static const struct of_device_id gcc_ipq5018_match_table[] =3D { --=20 2.49.0 From nobody Mon Feb 9 08:15:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A56321E3DFA; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858005; cv=none; b=Do4DS5ER7QQE2EUti4OrMJ9pKUWF5UZ3rv4QJg2SAQThoxW9dojiYMD5QvD35JN0YpGPgzIfpaIsTa+CalJK8ahm0TbKNSPjlYv5t2P5gu1a46y+VrHdc1LtgUjiI5h2qia5ESTP3oQjQmwR1ftLLoiOweTujJws+KriVmWnDbk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858005; c=relaxed/simple; bh=fVctS97OJmoSSqGiLs9Cd6dSp+7xO3b3gQPaAh6v7E0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=QvtnFGXU8l0/oqik7gbwMcyM0ZVj7lCH5fDMHYvfn31hv2ws0quI4ULQgLIDx4lJwVi4LFXVkSn1zhelgPoQS/5kh0dTEBzzvPpERyoMhQWVKtOt32E3NG74xaRNO/AIx752+9ri8hWQyqllvpfxD5RbyuVPQYSxN1jtErx19bI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UWer+feN; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UWer+feN" Received: by smtp.kernel.org (Postfix) with ESMTPS id 621B4C4AF0C; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748858005; bh=fVctS97OJmoSSqGiLs9Cd6dSp+7xO3b3gQPaAh6v7E0=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UWer+feNx4d/j92SK3sDBs/6LKTsuy3GNIFGkqxb6/TPk/i3xzQP8Pf/Kbx26bRzA haiTIhluTU1GGJzB4MgtMSFZ5cKP2JxDs+WKgitQSremWMJkpL5PTHtYiZDmTX5qv/ Jrv6u2cKcbvmEL3mJDgRaMP63L62xjUwWzm32UqV+M0GmUpFKQVgkFUS7VkHJQg/o4 djxJIv80ObWozQLOR10WrWAZu+rm4OKlq+FBlEGxEN6KcdK/DuRDHWBMT0Mc/V2gcn /LairMF2fVlK15CqnJR46eUkxVl6NixkDUpbga4nHmJZFGcb1lTpGtCIgJmfd0DCFU l6eO6kSxmmo7g== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 528CCC5B559; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 02 Jun 2025 13:53:14 +0400 Subject: [PATCH v3 2/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250602-ipq5018-ge-phy-v3-2-421337a031b2@outlook.com> References: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> In-Reply-To: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748858002; l=2979; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=I1imHb1fBZfRCiC+EjS8oo2zUnv/w8RwXOYxT/Ymdy8=; b=5MvFeNyKnfj8noeucwmXIfpOlLsooSsex0B8FFxDR6toKJzsESIfEqjuGvyFV4SRabwTc7GWi M5aRqphy7XJAqTEajzYXVRDRl3kbcPGYQt8EnY232PSN2XkZkwbAMkg X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 SoC. Its output pins provide an MDI interface to either an external switch in a PHY to PHY link scenario or is directly attached to an RJ45 connector. The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and 802.3az EEE. For operation, the LDO controller found in the IPQ5018 SoC for which there is provision in the mdio-4019 driver. Two common archictures across IPQ5018 boards are: 1. IPQ5018 PHY --> MDI --> RJ45 connector 2. IPQ5018 PHY --> MDI --> External PHY In a phy to phy architecture, the DAC needs to be configured to accommodate for the short cable length. As such, add an optional boolean property so the driver sets preset DAC register values accordingly. Signed-off-by: George Moussalem --- .../devicetree/bindings/net/qca,ar803x.yaml | 39 ++++++++++++++++++= ++++ 1 file changed, 39 insertions(+) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Docume= ntation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da863137f8a05e435a1fd28a536c2acd..fce167412896edbf49371129e3e= 7e87312eee051 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -16,8 +16,32 @@ description: | =20 allOf: - $ref: ethernet-phy.yaml# + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d0c0 + + then: + properties: + reg: + const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 = SoC + resets: + items: + - description: + GE PHY MISC reset which triggers a reset across MDC, DSP, = RX, and TX lines. + qcom,dac-preset-short-cable: + description: + Set if this phy is connected to another phy to adjust the valu= es for + MDAC and EDAC to adjust amplitude, bias current settings, and = error + detection and correction algorithm to accommodate for short ca= ble length. + If not set, it is assumed the MDI output pins of this PHY are = directly + connected to an RJ45 connector and default DAC values will be = used. + type: boolean =20 properties: + qca,clk-out-frequency: description: Clock output frequency in Hertz. $ref: /schemas/types.yaml#/definitions/uint32 @@ -132,3 +156,18 @@ examples: }; }; }; + - | + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* add alias to set qcom,dac-preset-short-cable on boards that nee= d it */ + ge_phy: ethernet-phy@7 { + compatible =3D "ethernet-phy-id004d.d0c0"; + reg =3D <7>; + + resets =3D <&gcc GCC_GEPHY_MISC_ARES>; + }; + }; --=20 2.49.0 From nobody Mon Feb 9 08:15:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3ED31E9915; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858006; cv=none; b=ard/vRBuOC92fUQFdTb/rp98/0DRrHK1EX+m7Uw0npq/xpfupLYVoBUZd0Jw0L7Gk06NWo7YbXcOI9fhqeS5xJxsrcsF9ygL8kDLBQK6hYW0Yc0uj3CV3aM7pCuLXBOJC6K9iP+M7y1WJxxh0HgseKjhrvYFDlAiaCVP7H5/5uo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858006; c=relaxed/simple; bh=o9XnE86p7e/+vKba6ZL/A7DxDymIWvcFNdXSEZJcqKI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=uaWX5lVOqrl5wdzhs9at5LI2SuwE4zgThMB1mPfkUUcXnhKSzYxkIXdizrZSclZEP9zz+Yg/8mJ9/7GlU4xOglzdXBFXvBOhdJqkK+538FuIFFL6q/GGlScgS9xgkdxqvyXl5cy6XXchwvhSYd643pYQJd0ItARPoNNk7s2Wjlw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=UTDSKe4L; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="UTDSKe4L" Received: by smtp.kernel.org (Postfix) with ESMTPS id 6EC04C4CEF8; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748858005; bh=o9XnE86p7e/+vKba6ZL/A7DxDymIWvcFNdXSEZJcqKI=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=UTDSKe4LpdTDKea9JoNcDm4H46IeMtz+MP9+TYqG1+V2G813bAp68kBIGOz3rFe7i Q+gOOjFu1Vj3gg81C8eHyd5bWZrvVItlVvEt/092pek/orjWNVXhwtLlaMBX22mMoo 9X9uIaAnkvHWcbvYNhrs28fcm0jtYgUOucxEDqbVQHjzIxLtz4rIH46d4zRluiL99W 77USKPLCqER2nJQKVf3yOC5mg0MSxh5KfWRJlk7Gz5czjnNOotFcE+KWUkgQrhscrH IRPfOqp+mZkwFm7VunvTfYeGIEmHOO3YlKaFJVTxQ2bpZdWT8WuhR2eFilt4HF+9JK q405S7yHiFB0A== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 62106C54FB3; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 02 Jun 2025 13:53:15 +0400 Subject: [PATCH v3 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250602-ipq5018-ge-phy-v3-3-421337a031b2@outlook.com> References: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> In-Reply-To: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748858002; l=10020; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=fAqFmmrHS9SwsM+fagAKrdxW+B0gISXJNK2eufuTxAE=; b=1jEHfObbPpTzD9u2xb3aLh2JCIWIEBj6p3owC+sbqV/tBUJSxEBUkZ3yujhZbZkD6f3o7dzsg BY7hczqevTIB/gueIq+n2Xh/P23r4LsgsUzmTaLfq5poRWQdJWsFCfN X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which provides an MDI interface directly to an RJ45 connector or an external switch over a PHY to PHY link. The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and 802.3az EEE. Let's add support for this PHY in the at803x driver as it falls within the Qualcomm Atheros OUI. Signed-off-by: George Moussalem --- drivers/net/phy/qcom/Kconfig | 2 +- drivers/net/phy/qcom/at803x.c | 185 ++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 178 insertions(+), 9 deletions(-) diff --git a/drivers/net/phy/qcom/Kconfig b/drivers/net/phy/qcom/Kconfig index 570626cc8e14d3e6615f74a6377f0f7c9f723e89..84239e08a8dfa466b0a7b2a5ec7= 24a168b692cd2 100644 --- a/drivers/net/phy/qcom/Kconfig +++ b/drivers/net/phy/qcom/Kconfig @@ -7,7 +7,7 @@ config AT803X_PHY select QCOM_NET_PHYLIB depends on REGULATOR help - Currently supports the AR8030, AR8031, AR8033, AR8035 model + Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model =20 config QCA83XX_PHY tristate "Qualcomm Atheros QCA833x PHYs" diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c index 26350b962890b0321153d74758b13d817407d094..c148e245b5391c5da374ace8609= dcdfd8284732d 100644 --- a/drivers/net/phy/qcom/at803x.c +++ b/drivers/net/phy/qcom/at803x.c @@ -7,19 +7,24 @@ * Author: Matus Ujhelyi */ =20 -#include -#include -#include -#include +#include +#include +#include #include #include -#include -#include -#include -#include +#include +#include +#include #include +#include #include +#include +#include +#include +#include +#include #include +#include #include =20 #include "qcom.h" @@ -96,6 +101,8 @@ #define ATH8035_PHY_ID 0x004dd072 #define AT8030_PHY_ID_MASK 0xffffffef =20 +#define IPQ5018_PHY_ID 0x004dd0c0 + #define QCA9561_PHY_ID 0x004dd042 =20 #define AT803X_PAGE_FIBER 0 @@ -108,6 +115,50 @@ /* disable hibernation mode */ #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) =20 +#define IPQ5018_PHY_FIFO_CONTROL 0x19 +#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + +#define IPQ5018_PHY_DEBUG_EDAC 0x4380 +#define IPQ5018_PHY_MMD1_MDAC 0x8100 +#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8) + +/* MDAC and EDAC values for short cable length */ +#define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10 +#define IPQ5018_PHY_MMD1_MDAC_VAL 0x10 + +#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 +#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 +#define IPQ5018_PHY_PCS_AZ_CTRL1 0x8008 +#define IPQ5018_PHY_PCS_AZ_CTRL2 0x8009 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f + +#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 +#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 +#define IPQ5018_PHY_PCS_AZ_CTRL1_VAL 0x7880 +#define IPQ5018_PHY_PCS_AZ_CTRL2_VAL 0xc8 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060 +#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0 + +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4) +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 +#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 + +#define IPQ5018_TCSR_ETH_LDO_READY BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -133,6 +184,11 @@ struct at803x_context { u16 led_control; }; =20 +struct ipq5018_priv { + struct reset_control *rst; + bool set_short_cable_dac; +}; + static int at803x_write_page(struct phy_device *phydev, int page) { int mask; @@ -987,6 +1043,105 @@ static int at8035_probe(struct phy_device *phydev) return at8035_parse_dt(phydev); } =20 +static int ipq5018_cable_test_start(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, + IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL); + + /* we do all the (time consuming) work later */ + return 0; +} + +static int ipq5018_config_init(struct phy_device *phydev) +{ + struct ipq5018_priv *priv =3D phydev->priv; + u16 val =3D 0; + + /* + * set LDO efuse: first temporarily store ANA_DAC_FILTER value from + * debug register as it will be reset once the ANA_LDO_EFUSE register + * is written to + */ + val =3D at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); + at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); + + /* set 8023AZ CTRL values */ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL1, + IPQ5018_PHY_PCS_AZ_CTRL1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL2, + IPQ5018_PHY_PCS_AZ_CTRL2_VAL); + + /* set MSE threshold values */ + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, + IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, + IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); + + /* PHY DAC values are optional and only set in a PHY to PHY link architec= ture */ + if (priv->set_short_cable_dac) { + /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */ + phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, + IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL); + + /* setting EDAC (Error-detection and Correction) in debug register */ + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, + IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL); + } + + return 0; +} + +static void ipq5018_link_change_notify(struct phy_device *phydev) +{ + mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, + IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET, + phydev->link ? IPQ5018_PHY_FIFO_RESET : 0); +} + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct device *dev =3D &phydev->mdio.dev; + struct ipq5018_priv *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->set_short_cable_dac =3D of_property_read_bool(dev->of_node, + "qcom,dac-preset-short-cable"); + + priv->rst =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret =3D reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, "failed to reset\n"); + + phydev->priv =3D priv; + + return 0; +} + static struct phy_driver at803x_driver[] =3D { { /* Qualcomm Atheros AR8035 */ @@ -1078,6 +1233,19 @@ static struct phy_driver at803x_driver[] =3D { .read_status =3D at803x_read_status, .soft_reset =3D genphy_soft_reset, .config_aneg =3D at803x_config_aneg, +}, { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name =3D "Qualcomm Atheros IPQ5018 internal PHY", + .flags =3D PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, + .probe =3D ipq5018_probe, + .config_init =3D ipq5018_config_init, + .link_change_notify =3D ipq5018_link_change_notify, + .read_status =3D at803x_read_status, + .config_intr =3D at803x_config_intr, + .handle_interrupt =3D at803x_handle_interrupt, + .cable_test_start =3D ipq5018_cable_test_start, + .cable_test_get_status =3D qca808x_cable_test_get_status, + .soft_reset =3D genphy_soft_reset, }, { /* Qualcomm Atheros QCA9561 */ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), @@ -1104,6 +1272,7 @@ static const struct mdio_device_id __maybe_unused ath= eros_tbl[] =3D { { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { } }; --=20 2.49.0 From nobody Mon Feb 9 08:15:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B45591E5B79; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858005; cv=none; b=JCwlcH7uqo37Wbe0xtrhDilnPDjbY3VJUt6G+H7eTPoMNXTjzv5gDSwTVdGkXqYMMECX7KPIfTWKYw2WafdpGZKXeofi5o1Ag4lGuIaD2dMYYlPoXqxU6JPaBlgyZSuHDefM0e8WBmpWUsfa1t8zBTW8Iun2GWgeQ23soe56ZUY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858005; c=relaxed/simple; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=rlf3lMj7GvNAOkL4P3trR0qJRQdIjtw1H6DymzcTWJiuTsP5HUOE1KM39BriHjHFfeGDuDpoZ0L5tBtEGjSRRfkyz2ZCNg/mtqnBcVdmNSqg0/RVghRXziYAuzGg9UFRF1ptRcbKkbXojRs/FsEl4kFwN02LVGbjkvtYWvacWsU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=tX1dr5eW; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="tX1dr5eW" Received: by smtp.kernel.org (Postfix) with ESMTPS id 79780C4CEF6; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748858005; bh=WzM5y2OoQkwywYk7ze1eYenAU+huZ1+9rx3teZ27zKM=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=tX1dr5eWKynSKfmWSAYpOyg3ugGUosfD+f9PiOpf8uYe/qmJ1eUPF2CJ1pSE6KKj2 LrJHvfA26P8Ts4uANSKh9LRniSVKiRbJ6vfJOgm0+ypiwfyyMdgoTpqCpcx0EmCCdj SMyDKn63YJmvGEtOBYDXC6j/xaVxAMZ1Tqa1WlR7wXGrL1v67wmxwmvZOg3ofoALqz IzHrh9Xv9tITranVkvWW0+5JUHeF3XGOZMJcgrtCCRoHCFOc9Dx+qbOEz6hISqSell smAneXBGqZ2vlIycQNE+5okpRR0teqyVwBqnVHrzqIGUhbAxb8c5Ab1qa3mlr50UMH zr00rRFqrWK3Q== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6FF8AC5B549; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 02 Jun 2025 13:53:16 +0400 Subject: [PATCH v3 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250602-ipq5018-ge-phy-v3-4-421337a031b2@outlook.com> References: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> In-Reply-To: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748858002; l=1519; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=jA4BQsaw0tlEf36IZrwvZtR6C1am2pcwyAdrevsj4Hk=; b=NKCtDXN7RAmyNzxNa/6j+qVmGVrCf1O3gdGM/jwcWO5FteGqhVjf2noBORSB+3q62GOwf28hv nwuz2+YP+0QDanIMtL3pfWcLD21c7Q3IFgiJ01pyWz2BW4rMrSd8D5D X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce4= 7a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status =3D "disabled"; }; =20 + mdio0: mdio@88000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00088000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO0_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + + mdio1: mdio@90000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00090000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO1_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5018-tlmm"; reg =3D <0x01000000 0x300000>; --=20 2.49.0 From nobody Mon Feb 9 08:15:50 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3A69E1EE02F; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858006; cv=none; b=B5iL9RK0hni3flrRddkhcA08+DeRpNpUtmq2pF08Qxa2fzpO0NN+RTbW8bJd8RwKkpMKnrwMACAUv9F+Kf5KJYI7G7Awzzbycc+XwXKcvUJ7c1wIpANd/BYr5TNFbpdXGw9b0z9TeYvrUq9GcbZ8kKyVgK4c1kyYYUbwoWBfrQs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748858006; c=relaxed/simple; bh=YW0aYGk44OBGXMXwnXBPhhKQgB+lh/nINEBWmVaTupA=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=nSvbY4074TBWqToP9tWk1y643SLKmmORv5hoY1r/Y0URR9CdWT3W8qy08WLmwXyL9nhzkqJvjq5wRdoCryccEitSrJrax5VqRUsUtADDawNXf1D+2jtXmMfj+dN9hjnro3alnyCeTYzmrUK6WQxZ2soZ6sojYPpC9jKeUU8bkPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=h7covpRT; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="h7covpRT" Received: by smtp.kernel.org (Postfix) with ESMTPS id 871FCC4AF0B; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748858005; bh=YW0aYGk44OBGXMXwnXBPhhKQgB+lh/nINEBWmVaTupA=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=h7covpRTh3TWctaSOHielhkRdC+O2qJwj1qh7JPnZTo7i1QKzENJBzN8rueMHgUJp 6EZfL15aKWwLCEmDN2RsbsTgCHN3XJjKLl+l5QpzxooUpzIkV31Q5KBEhSob6HlJ9I D54LDGcf7vy/AoN9XnXzTahHDUxRE5tU8DXy82A44psLmwZtfM+7ve85lbMauo4WBY MEhf3FKqWn2t7dMeatvyVFtnRYq0RkITSXd1SJE/e0YBkAJaeCHbW61qAj7npGkGFS P2uryx7vqSf2oWgh+Afek/yj4pB+cIVYthJ66bMtkrx0V3Nh4SiPcS5vVQ3gk4nmZz 0tOI0tGRhnrWg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7D973C61CE5; Mon, 2 Jun 2025 09:53:25 +0000 (UTC) From: George Moussalem via B4 Relay Date: Mon, 02 Jun 2025 13:53:17 +0400 Subject: [PATCH v3 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250602-ipq5018-ge-phy-v3-5-421337a031b2@outlook.com> References: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> In-Reply-To: <20250602-ipq5018-ge-phy-v3-0-421337a031b2@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem , Konrad Dybcio X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748858002; l=2285; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=hFpy0osU/0n+A52muRC0D3Drst6JCZAX5hmtJZDrLks=; b=N49n6bXKezFjPN5GJPRT+nh05uSgQVNbY4Dz+Qo7xmhVhq7Ajjuu+u12p/VRDTiYU3yFSOF0D B9lgYJLAsIHDStM+rLG60GYWVlZU1VyEHjd0n5g4WNRwnLHpOP+cxJ+ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. The LDO controller found in the SoC must be enabled to provide constant low voltages to the PHY. The mdio-ipq4019 driver already has support for this, so adding the appropriate TCSR register offset. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Reviewed-by: Konrad Dybcio Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 26 +++++++++++++++++++++++--- 1 file changed, 23 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 03ebc3e305b267c98a034c41ce47a39269afce75..d47ad62b01991fafa51e7082bd1= fcf6670d9b0bc 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -16,6 +16,18 @@ / { #size-cells =3D <2>; =20 clocks { + gephy_rx_clk: gephy-rx-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -184,7 +196,8 @@ pcie0_phy: phy@86000 { =20 mdio0: mdio@88000 { compatible =3D "qcom,ipq5018-mdio"; - reg =3D <0x00088000 0x64>; + reg =3D <0x00088000 0x64>, + <0x019475c4 0x4>; #address-cells =3D <1>; #size-cells =3D <0>; =20 @@ -192,6 +205,13 @@ mdio0: mdio@88000 { clock-names =3D "gcc_mdio_ahb_clk"; =20 status =3D "disabled"; + + ge_phy: ethernet-phy@7 { + compatible =3D "ethernet-phy-id004d.d0c0"; + reg =3D <7>; + + resets =3D <&gcc GCC_GEPHY_MISC_ARES>; + }; }; =20 mdio1: mdio@90000 { @@ -232,8 +252,8 @@ gcc: clock-controller@1800000 { <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells =3D <1>; --=20 2.49.0