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charset="utf-8" This patch corrects several typographical issues and improves phrasing in memory-devices.rst: - Fixes duplicate word ("1 one") and adjusts phrasing for clarity. - Adds missing hyphen in "on-device". - Corrects "a give memory device" to "a given memory device". - fix singular/plural "decoder resource" -> "decoder resources". - Clarifies "spans to Host Bridges" -> "spans two Host Bridges". These changes improve readability and accuracy of the documentation. Signed-off-by: Alok Tiwari Reviewed-by: Gregory Price Reviewed-by: Jonathan Cameron Reviewed-by: Randy Dunlap --- Documentation/driver-api/cxl/memory-devices.rst | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/Documentation/driver-api/cxl/memory-devices.rst b/Documentatio= n/driver-api/cxl/memory-devices.rst index d732c42526df..e9e2952a967d 100644 --- a/Documentation/driver-api/cxl/memory-devices.rst +++ b/Documentation/driver-api/cxl/memory-devices.rst @@ -29,8 +29,8 @@ Platform firmware enumerates a menu of interleave options= at the "CXL root port" (Linux term for the top of the CXL decode topology). From there, PCIe topo= logy dictates which endpoints can participate in which Host Bridge decode regim= es. Each PCIe Switch in the path between the root and an endpoint introduces a= point -at which the interleave can be split. For example platform firmware may sa= y at a -given range only decodes to 1 one Host Bridge, but that Host Bridge may in= turn +at which the interleave can be split. For example, platform firmware may s= ay at a +given range only decodes to one Host Bridge, but that Host Bridge may in t= urn interleave cycles across multiple Root Ports. An intervening Switch betwee= n a port and an endpoint may interleave cycles across multiple Downstream Swit= ch Ports, etc. @@ -187,7 +187,7 @@ decodes them to "ports", "ports" decode to "endpoints",= and "endpoints" represent the decode from SPA (System Physical Address) to DPA (Device Phy= sical Address). =20 -Continuing the RAID analogy, disks have both topology metadata and on devi= ce +Continuing the RAID analogy, disks have both topology metadata and on-devi= ce metadata that determine RAID set assembly. CXL Port topology and CXL Port = link status is metadata for CXL.mem set assembly. The CXL Port topology is enum= erated by the arrival of a CXL.mem device. I.e. unless and until the PCIe core at= taches @@ -197,7 +197,7 @@ the Linux PCI core to tear down switch-level CXL resour= ces because the endpoint ->remove() event cleans up the port data that was established to support t= hat Memory Expander. =20 -The port metadata and potential decode schemes that a give memory device m= ay +The port metadata and potential decode schemes that a given memory device = may participate can be determined via a command like:: =20 # cxl list -BDMu -d root -m mem3 @@ -249,8 +249,8 @@ participate can be determined via a command like:: ...which queries the CXL topology to ask "given CXL Memory Expander with a= kernel device name of 'mem3' which platform level decode ranges may this device participate". A given expander can participate in multiple CXL.mem interle= ave -sets simultaneously depending on how many decoder resource it has. In this -example mem3 can participate in one or more of a PMEM interleave that span= s to +sets simultaneously depending on how many decoder resources it has. In this +example mem3 can participate in one or more of a PMEM interleave that span= s two Host Bridges, a PMEM interleave that targets a single Host Bridge, a Volat= ile memory interleave that spans 2 Host Bridges, and a Volatile memory interle= ave that only targets a single Host Bridge. --=20 2.47.1