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Fri, 30 May 2025 10:18:52 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:bcab:7ec7:2377:13b0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f00972c1sm5395963f8f.68.2025.05.30.10.18.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 10:18:51 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v6 1/4] clk: renesas: rzv2h-cpg: Add support for DSI clocks Date: Fri, 30 May 2025 18:18:38 +0100 Message-ID: <20250530171841.423274-2-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add support for PLLDSI and PLLDSI divider clocks. Introduce the `renesas-rzv2h-dsi.h` header to centralize and share PLLDSI-related data structures, limits, and algorithms between the RZ/V2H CPG and DSI drivers. The DSI PLL is functionally similar to the CPG's PLLDSI, but has slightly different parameter limits and omits the programmable divider present in CPG. To ensure precise frequency calculations-especially for milliHz-level accuracy needed by the DSI driver-the shared algorithm allows both drivers to compute PLL parameters consistently using the same logic and input clock. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v5->v6: - Renamed CPG_PLL_STBY_SSCGEN_WEN to CPG_PLL_STBY_SSC_EN_WEN - Updated CPG_PLL_CLK1_DIV_K, CPG_PLL_CLK1_DIV_M, and CPG_PLL_CLK1_DIV_P macros to use GENMASK - Updated req->rate in rzv2h_cpg_plldsi_div_determine_rate() - Dropped the cast in rzv2h_cpg_plldsi_div_set_rate() - Dropped rzv2h_cpg_plldsi_round_rate() and implemented rzv2h_cpg_plldsi_determine_rate() instead - Made use of FIELD_PREP() - Moved CPG_CSDIV1 macro in patch 2/4 - Dropped two_pow_s in rzv2h_dsi_get_pll_parameters_values() - Used mul_u32_u32() while calculating output_m and output_k_range - Used div_s64() instead of div64_s64() while calculating pll_k - Used mul_u32_u32() while calculating fvco and fvco checks - Rounded the final output using DIV_U64_ROUND_CLOSEST() v4->v5: - No changes v3->v4: - Corrected parameter name in rzv2h_dsi_get_pll_parameters_values() description freq_millihz v2->v3: - Update the commit message to clarify the purpose of `renesas-rzv2h-dsi.h` header - Used mul_u32_u32() in rzv2h_cpg_plldsi_div_determine_rate() - Replaced *_mhz to *_millihz for clarity - Updated u64->u32 for fvco limits - Initialized the members in declaration order for RZV2H_CPG_PLL_DSI_LIMITS() macro - Used clk_div_mask() in rzv2h_cpg_plldsi_div_recalc_rate() - Replaced `unsigned long long` with u64 - Dropped rzv2h_cpg_plldsi_clk_recalc_rate() and reused rzv2h_cpg_pll_clk_recalc_rate() instead - In rzv2h_cpg_plldsi_div_set_rate() followed the same style of RMW-operation as done in the other functions - Renamed rzv2h_cpg_plldsi_set_rate() to rzv2h_cpg_pll_set_rate() - Dropped rzv2h_cpg_plldsi_clk_register() and reused rzv2h_cpg_pll_clk_register() instead - Added a gaurd in renesas-rzv2h-dsi.h header v1->v2: - No changes --- drivers/clk/renesas/rzv2h-cpg.c | 278 +++++++++++++++++++++++++- drivers/clk/renesas/rzv2h-cpg.h | 13 ++ include/linux/clk/renesas-rzv2h-dsi.h | 210 +++++++++++++++++++ 3 files changed, 492 insertions(+), 9 deletions(-) create mode 100644 include/linux/clk/renesas-rzv2h-dsi.h diff --git a/drivers/clk/renesas/rzv2h-cpg.c b/drivers/clk/renesas/rzv2h-cp= g.c index 761da3bf77ce..d590f9f47371 100644 --- a/drivers/clk/renesas/rzv2h-cpg.c +++ b/drivers/clk/renesas/rzv2h-cpg.c @@ -14,9 +14,13 @@ #include #include #include +#include #include #include #include +#include +#include +#include #include #include #include @@ -26,6 +30,7 @@ #include #include #include +#include =20 #include =20 @@ -48,12 +53,13 @@ #define CPG_PLL_STBY(x) ((x)) #define CPG_PLL_STBY_RESETB BIT(0) #define CPG_PLL_STBY_RESETB_WEN BIT(16) +#define CPG_PLL_STBY_SSC_EN_WEN BIT(18) #define CPG_PLL_CLK1(x) ((x) + 0x004) -#define CPG_PLL_CLK1_KDIV(x) ((s16)FIELD_GET(GENMASK(31, 16), (x))) -#define CPG_PLL_CLK1_MDIV(x) FIELD_GET(GENMASK(15, 6), (x)) -#define CPG_PLL_CLK1_PDIV(x) FIELD_GET(GENMASK(5, 0), (x)) +#define CPG_PLL_CLK1_KDIV GENMASK(31, 16) +#define CPG_PLL_CLK1_MDIV GENMASK(15, 6) +#define CPG_PLL_CLK1_PDIV GENMASK(5, 0) #define CPG_PLL_CLK2(x) ((x) + 0x008) -#define CPG_PLL_CLK2_SDIV(x) FIELD_GET(GENMASK(2, 0), (x)) +#define CPG_PLL_CLK2_SDIV GENMASK(2, 0) #define CPG_PLL_MON(x) ((x) + 0x010) #define CPG_PLL_MON_RESETB BIT(0) #define CPG_PLL_MON_LOCK BIT(4) @@ -79,6 +85,8 @@ * @last_dt_core_clk: ID of the last Core Clock exported to DT * @mstop_count: Array of mstop values * @rcdev: Reset controller entity + * @dsi_limits: PLL DSI parameters limits + * @plldsi_div_parameters: PLL DSI and divider parameters configuration */ struct rzv2h_cpg_priv { struct device *dev; @@ -95,6 +103,9 @@ struct rzv2h_cpg_priv { atomic_t *mstop_count; =20 struct reset_controller_dev rcdev; + + const struct rzv2h_pll_div_limits *dsi_limits; + struct rzv2h_plldsi_parameters plldsi_div_parameters; }; =20 #define rcdev_to_priv(x) container_of(x, struct rzv2h_cpg_priv, rcdev) @@ -150,6 +161,24 @@ struct ddiv_clk { =20 #define to_ddiv_clock(_div) container_of(_div, struct ddiv_clk, div) =20 +/** + * struct rzv2h_plldsi_div_clk - PLL DSI DDIV clock + * + * @dtable: divider table + * @priv: CPG private data + * @hw: divider clk + * @ddiv: divider configuration + */ +struct rzv2h_plldsi_div_clk { + const struct clk_div_table *dtable; + struct rzv2h_cpg_priv *priv; + struct clk_hw hw; + struct ddiv ddiv; +}; + +#define to_plldsi_div_clk(_hw) \ + container_of(_hw, struct rzv2h_plldsi_div_clk, hw) + static int rzv2h_cpg_pll_clk_is_enabled(struct clk_hw *hw) { struct pll_clk *pll_clk =3D to_pll(hw); @@ -198,6 +227,214 @@ static int rzv2h_cpg_pll_clk_enable(struct clk_hw *hw) return ret; } =20 +static unsigned long rzv2h_cpg_plldsi_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct rzv2h_plldsi_div_clk *dsi_div =3D to_plldsi_div_clk(hw); + struct rzv2h_cpg_priv *priv =3D dsi_div->priv; + struct ddiv ddiv =3D dsi_div->ddiv; + u32 div; + + div =3D readl(priv->base + ddiv.offset); + div >>=3D ddiv.shift; + div &=3D clk_div_mask(ddiv.width); + div =3D dsi_div->dtable[div].div; + + return DIV_ROUND_CLOSEST_ULL(parent_rate, div); +} + +static int rzv2h_cpg_plldsi_div_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rzv2h_plldsi_div_clk *dsi_div =3D to_plldsi_div_clk(hw); + struct rzv2h_cpg_priv *priv =3D dsi_div->priv; + struct rzv2h_plldsi_parameters *dsi_dividers =3D &priv->plldsi_div_parame= ters; + u64 rate_millihz; + + /* + * Adjust the requested clock rate (`req->rate`) to ensure it falls within + * the supported range of 5.44 MHz to 187.5 MHz. + */ + req->rate =3D clamp(req->rate, 5440000UL, 187500000UL); + + rate_millihz =3D mul_u32_u32(req->rate, MILLI); + if (rate_millihz =3D=3D dsi_dividers->error_millihz + dsi_dividers->freq_= millihz) + goto exit_determine_rate; + + if (!rzv2h_dsi_get_pll_parameters_values(priv->dsi_limits, + dsi_dividers, rate_millihz)) { + dev_err(priv->dev, + "failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + +exit_determine_rate: + req->best_parent_rate =3D req->rate * dsi_dividers->csdiv; + req->rate =3D DIV_ROUND_CLOSEST_ULL(dsi_dividers->freq_millihz, MILLI); + + return 0; +}; + +static int rzv2h_cpg_plldsi_div_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct rzv2h_plldsi_div_clk *dsi_div =3D to_plldsi_div_clk(hw); + struct rzv2h_cpg_priv *priv =3D dsi_div->priv; + struct rzv2h_plldsi_parameters *dsi_dividers =3D &priv->plldsi_div_parame= ters; + struct ddiv ddiv =3D dsi_div->ddiv; + const struct clk_div_table *clkt; + bool div_found =3D false; + u32 val, shift, div; + + div =3D dsi_dividers->csdiv; + for (clkt =3D dsi_div->dtable; clkt->div; clkt++) { + if (clkt->div =3D=3D div) { + div_found =3D true; + break; + } + } + + if (!div_found) + return -EINVAL; + + shift =3D ddiv.shift; + val =3D readl(priv->base + ddiv.offset) | DDIV_DIVCTL_WEN(shift); + val &=3D ~(clk_div_mask(ddiv.width) << shift); + val |=3D clkt->val << shift; + writel(val, priv->base + ddiv.offset); + + return 0; +}; + +static const struct clk_ops rzv2h_cpg_plldsi_div_ops =3D { + .recalc_rate =3D rzv2h_cpg_plldsi_div_recalc_rate, + .determine_rate =3D rzv2h_cpg_plldsi_div_determine_rate, + .set_rate =3D rzv2h_cpg_plldsi_div_set_rate, +}; + +static struct clk * __init +rzv2h_cpg_plldsi_div_clk_register(const struct cpg_core_clk *core, + struct rzv2h_cpg_priv *priv) +{ + struct rzv2h_plldsi_div_clk *clk_hw_data; + struct clk **clks =3D priv->clks; + struct clk_init_data init; + const struct clk *parent; + const char *parent_name; + struct clk_hw *clk_hw; + int ret; + + parent =3D clks[core->parent]; + if (IS_ERR(parent)) + return ERR_CAST(parent); + + clk_hw_data =3D devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL); + if (!clk_hw_data) + return ERR_PTR(-ENOMEM); + + clk_hw_data->priv =3D priv; + clk_hw_data->ddiv =3D core->cfg.ddiv; + clk_hw_data->dtable =3D core->dtable; + + parent_name =3D __clk_get_name(parent); + init.name =3D core->name; + init.ops =3D &rzv2h_cpg_plldsi_div_ops; + init.flags =3D core->flag; + init.parent_names =3D &parent_name; + init.num_parents =3D 1; + + clk_hw =3D &clk_hw_data->hw; + clk_hw->init =3D &init; + + ret =3D devm_clk_hw_register(priv->dev, clk_hw); + if (ret) + return ERR_PTR(ret); + + return clk_hw->clk; +} + +static int rzv2h_cpg_plldsi_determine_rate(struct clk_hw *hw, + struct clk_rate_request *req) +{ + struct rzv2h_pll_div_limits dsi_limits; + struct rzv2h_plldsi_parameters dsi_dividers; + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzv2h_cpg_priv *priv =3D pll_clk->priv; + u64 rate_millihz; + + memcpy(&dsi_limits, priv->dsi_limits, sizeof(dsi_limits)); + dsi_limits.csdiv.min =3D 1; + dsi_limits.csdiv.max =3D 1; + + req->rate =3D clamp(req->rate, 25000000UL, 375000000UL); + + rate_millihz =3D mul_u32_u32(req->rate, MILLI); + if (!rzv2h_dsi_get_pll_parameters_values(priv->dsi_limits, + &dsi_dividers, rate_millihz)) { + dev_err(priv->dev, + "failed to determine rate for req->rate: %lu\n", + req->rate); + return -EINVAL; + } + + req->best_parent_rate =3D req->rate * dsi_dividers.csdiv; + req->rate =3D DIV_ROUND_CLOSEST_ULL(dsi_dividers.freq_millihz, MILLI); + + return 0; +} + +static int rzv2h_cpg_pll_set_rate(struct clk_hw *hw, + unsigned long rate, + unsigned long parent_rate) +{ + struct pll_clk *pll_clk =3D to_pll(hw); + struct rzv2h_cpg_priv *priv =3D pll_clk->priv; + struct rzv2h_plldsi_parameters *dsi_dividers; + struct pll pll =3D pll_clk->pll; + u16 offset =3D pll.offset; + u32 val; + int ret; + + /* Put PLL into standby mode */ + writel(CPG_PLL_STBY_RESETB_WEN, priv->base + CPG_PLL_STBY(offset)); + ret =3D readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), + val, !(val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + dev_err(priv->dev, "Failed to put PLLDSI into standby mode"); + return ret; + } + + dsi_dividers =3D &priv->plldsi_div_parameters; + /* Output clock setting 1 */ + writel(FIELD_PREP(CPG_PLL_CLK1_KDIV, (u16)dsi_dividers->k) | + FIELD_PREP(CPG_PLL_CLK1_MDIV, dsi_dividers->m) | + FIELD_PREP(CPG_PLL_CLK1_PDIV, dsi_dividers->p), + priv->base + CPG_PLL_CLK1(offset)); + + /* Output clock setting 2 */ + val =3D readl(priv->base + CPG_PLL_CLK2(offset)); + writel((val & ~CPG_PLL_CLK2_SDIV) | FIELD_PREP(CPG_PLL_CLK2_SDIV, dsi_div= iders->s), + priv->base + CPG_PLL_CLK2(offset)); + + /* Put PLL to normal mode */ + writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB, + priv->base + CPG_PLL_STBY(offset)); + + /* PLL normal mode transition, output clock stability check */ + ret =3D readl_poll_timeout_atomic(priv->base + CPG_PLL_MON(offset), + val, (val & CPG_PLL_MON_LOCK), + 100, 2000); + if (ret) { + dev_err(priv->dev, "Failed to put PLLDSI into normal mode"); + return ret; + } + + return 0; +}; + static unsigned long rzv2h_cpg_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -213,12 +450,19 @@ static unsigned long rzv2h_cpg_pll_clk_recalc_rate(st= ruct clk_hw *hw, clk1 =3D readl(priv->base + CPG_PLL_CLK1(pll.offset)); clk2 =3D readl(priv->base + CPG_PLL_CLK2(pll.offset)); =20 - rate =3D mul_u64_u32_shr(parent_rate, (CPG_PLL_CLK1_MDIV(clk1) << 16) + - CPG_PLL_CLK1_KDIV(clk1), 16 + CPG_PLL_CLK2_SDIV(clk2)); + rate =3D mul_u64_u32_shr(parent_rate, (FIELD_GET(CPG_PLL_CLK1_MDIV, clk1)= << 16) + + (s16)FIELD_GET(CPG_PLL_CLK1_KDIV, clk1), + 16 + FIELD_GET(CPG_PLL_CLK2_SDIV, clk2)); =20 - return DIV_ROUND_CLOSEST_ULL(rate, CPG_PLL_CLK1_PDIV(clk1)); + return DIV_ROUND_CLOSEST_ULL(rate, FIELD_GET(CPG_PLL_CLK1_PDIV, clk1)); } =20 +static const struct clk_ops rzv2h_cpg_plldsi_ops =3D { + .recalc_rate =3D rzv2h_cpg_pll_clk_recalc_rate, + .determine_rate =3D rzv2h_cpg_plldsi_determine_rate, + .set_rate =3D rzv2h_cpg_pll_set_rate, +}; + static const struct clk_ops rzv2h_cpg_pll_ops =3D { .is_enabled =3D rzv2h_cpg_pll_clk_is_enabled, .enable =3D rzv2h_cpg_pll_clk_enable, @@ -228,7 +472,8 @@ static const struct clk_ops rzv2h_cpg_pll_ops =3D { static struct clk * __init rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *core, struct rzv2h_cpg_priv *priv, - const struct clk_ops *ops) + const struct clk_ops *ops, + bool turn_on) { void __iomem *base =3D priv->base; struct device *dev =3D priv->dev; @@ -258,6 +503,13 @@ rzv2h_cpg_pll_clk_register(const struct cpg_core_clk *= core, pll_clk->base =3D base; pll_clk->priv =3D priv; =20 + if (turn_on) { + /* Disable SSC and turn on PLL clock when init */ + writel(CPG_PLL_STBY_RESETB_WEN | CPG_PLL_STBY_RESETB | + CPG_PLL_STBY_SSC_EN_WEN, + base + CPG_PLL_STBY(pll_clk->pll.offset)); + } + ret =3D devm_clk_hw_register(dev, &pll_clk->hw); if (ret) return ERR_PTR(ret); @@ -500,7 +752,7 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk *= core, clk =3D clk_hw->clk; break; case CLK_TYPE_PLL: - clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops); + clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_pll_ops, false= ); break; case CLK_TYPE_DDIV: clk =3D rzv2h_cpg_ddiv_clk_register(core, priv); @@ -508,6 +760,12 @@ rzv2h_cpg_register_core_clk(const struct cpg_core_clk = *core, case CLK_TYPE_SMUX: clk =3D rzv2h_cpg_mux_clk_register(core, priv); break; + case CLK_TYPE_PLLDSI: + clk =3D rzv2h_cpg_pll_clk_register(core, priv, &rzv2h_cpg_plldsi_ops, tr= ue); + break; + case CLK_TYPE_PLLDSI_DIV: + clk =3D rzv2h_cpg_plldsi_div_clk_register(core, priv); + break; default: goto fail; } @@ -1043,6 +1301,8 @@ static int __init rzv2h_cpg_probe(struct platform_dev= ice *pdev) priv->last_dt_core_clk =3D info->last_dt_core_clk; priv->num_resets =3D info->num_resets; =20 + priv->dsi_limits =3D info->plldsi_limits; + for (i =3D 0; i < nclks; i++) clks[i] =3D ERR_PTR(-ENOENT); =20 diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 7321b085f937..1f1ef2fcf878 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -166,6 +166,8 @@ enum clk_types { CLK_TYPE_PLL, CLK_TYPE_DDIV, /* Dynamic Switching Divider */ CLK_TYPE_SMUX, /* Static Mux */ + CLK_TYPE_PLLDSI, /* PLLDSI */ + CLK_TYPE_PLLDSI_DIV, /* PLLDSI divider */ }; =20 #define DEF_TYPE(_name, _id, _type...) \ @@ -193,6 +195,14 @@ enum clk_types { .num_parents =3D ARRAY_SIZE(_parent_names), \ .flag =3D CLK_SET_RATE_PARENT, \ .mux_flags =3D CLK_MUX_HIWORD_MASK) +#define DEF_PLLDSI(_name, _id, _parent, _pll_packed) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI, .parent =3D _parent, .cfg.pll =3D _= pll_packed) +#define DEF_PLLDSI_DIV(_name, _id, _parent, _ddiv_packed, _dtable) \ + DEF_TYPE(_name, _id, CLK_TYPE_PLLDSI_DIV, \ + .cfg.ddiv =3D _ddiv_packed, \ + .dtable =3D _dtable, \ + .parent =3D _parent, \ + .flag =3D CLK_SET_RATE_PARENT) =20 /** * struct rzv2h_mod_clk - Module Clocks definitions @@ -293,6 +303,7 @@ struct rzv2h_reset { * * @num_mstop_bits: Maximum number of MSTOP bits supported, equivalent to = the * number of CPG_BUS_m_MSTOP registers multiplied by 16. + * @plldsi_limits: PLL DSI parameters limits */ struct rzv2h_cpg_info { /* Core Clocks */ @@ -311,6 +322,8 @@ struct rzv2h_cpg_info { unsigned int num_resets; =20 unsigned int num_mstop_bits; + + const struct rzv2h_pll_div_limits *plldsi_limits; }; =20 extern const struct rzv2h_cpg_info r9a09g047_cpg_info; diff --git a/include/linux/clk/renesas-rzv2h-dsi.h b/include/linux/clk/rene= sas-rzv2h-dsi.h new file mode 100644 index 000000000000..b77f9bc3777e --- /dev/null +++ b/include/linux/clk/renesas-rzv2h-dsi.h @@ -0,0 +1,210 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Renesas RZ/V2H(P) DSI CPG helper + * + * Copyright (C) 2025 Renesas Electronics Corp. + */ +#ifndef __RENESAS_RZV2H_DSI_H__ +#define __RENESAS_RZV2H_DSI_H__ + +#include +#include +#include +#include + +#define OSC_CLK_IN_MEGA (24 * MEGA) + +struct rzv2h_pll_div_limits { + struct { + u32 min; + u32 max; + } fvco; + + struct { + u16 min; + u16 max; + } m; + + struct { + u8 min; + u8 max; + } p; + + struct { + u8 min; + u8 max; + } s; + + struct { + s16 min; + s16 max; + } k; + + struct { + u8 min; + u8 max; + } csdiv; +}; + +struct rzv2h_plldsi_parameters { + u64 freq_millihz; + s64 error_millihz; + u16 m; + s16 k; + u8 csdiv; + u8 p; + u8 s; +}; + +#define RZV2H_CPG_PLL_DSI_LIMITS(name) \ + static const struct rzv2h_pll_div_limits (name) =3D { \ + .fvco =3D { .min =3D 1600 * MEGA, .max =3D 3200 * MEGA }, \ + .m =3D { .min =3D 64, .max =3D 533 }, \ + .p =3D { .min =3D 1, .max =3D 4 }, \ + .s =3D { .min =3D 0, .max =3D 6 }, \ + .k =3D { .min =3D -32768, .max =3D 32767 }, \ + .csdiv =3D { .min =3D 2, .max =3D 32 }, \ + } \ + +/** + * rzv2h_dsi_get_pll_parameters_values - Finds the best combination of PLL= parameters + * and divider value for a given frequency. + * + * @limits: Pointer to the structure containing the limits for the PLL par= ameters and + * divider values + * @pars: Pointer to the structure where the best calculated PLL parameter= s and divider + * values will be stored + * @freq_millihz: Target output frequency in millihertz + * + * This function calculates the best set of PLL parameters (M, K, P, S) an= d divider + * value (CSDIV) to achieve the desired frequency. + * There is no direct formula to calculate the PLL parameters and the divi= der value, + * as it's an open system of equations, therefore this function uses an it= erative + * approach to determine the best solution. The best solution is one that = minimizes + * the error (desired frequency - actual frequency). + * + * Return: true if a valid set of divider values is found, false otherwise. + */ +static __maybe_unused bool +rzv2h_dsi_get_pll_parameters_values(const struct rzv2h_pll_div_limits *lim= its, + struct rzv2h_plldsi_parameters *pars, + u64 freq_millihz) +{ + struct rzv2h_plldsi_parameters p, best; + + /* Initialize best error to maximum possible value */ + best.error_millihz =3D S64_MAX; + + for (p.csdiv =3D limits->csdiv.min; p.csdiv <=3D limits->csdiv.max; p.csd= iv +=3D 2) { + for (p.p =3D limits->p.min; p.p <=3D limits->p.max; p.p++) { + u32 fref =3D OSC_CLK_IN_MEGA / p.p; + u16 divider; + + for (divider =3D p.csdiv << limits->s.min, p.s =3D limits->s.min; + p.s <=3D limits->s.max; p.s++, divider *=3D 2) { + for (p.m =3D limits->m.min; p.m <=3D limits->m.max; p.m++) { + u64 output_m, output_k_range; + s64 pll_k, output_k; + u64 fvco, output; + + /* + * The frequency generated by the combination of the + * PLL + divider is calculated as follows: + * + * Freq =3D Ffout / csdiv + * + * With: + * Ffout =3D Ffvco / 2^(pll_s) + * Ffvco =3D (pll_m + (pll_k / 65536)) * Ffref + * Ffref =3D 24MHz / pll_p + * + * Freq can also be rewritten as: + * Freq =3D Ffvco / (2^(pll_s) * csdiv)) + * =3D Ffvco / divider + * =3D (pll_m * Ffref) / divider + ((pll_k / 65536) * Ffref) / d= ivider + * =3D output_m + output_k + * + * Every parameter has been determined at this point, but pll_k. + * Considering that: + * -32768 <=3D pll_k <=3D 32767 + * Then: + * -0.5 <=3D (pll_k / 65536) < 0.5 + * Therefore: + * -Ffref / (2 * divider) <=3D output_k < Ffref / (2 * divider) + */ + + /* Compute output M component (in mHz) */ + output_m =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(p.m, fref) * MILLI, + divider); + /* Compute range for output K (in mHz) */ + output_k_range =3D DIV_ROUND_CLOSEST_ULL(mul_u32_u32(fref, MILLI), + divider * 2); + /* + * No point in continuing if we can't achieve the + * desired frequency + */ + if (freq_millihz < (output_m - output_k_range) || + freq_millihz >=3D (output_m + output_k_range)) + continue; + + /* + * Compute the K component + * + * Since: + * Freq =3D output_m + output_k + * Then: + * output_k =3D Freq - output_m + * =3D ((pll_k / 65536) * Ffref) / divider + * Therefore: + * pll_k =3D (output_k * 65536 * divider) / Ffref + */ + output_k =3D freq_millihz - output_m; + pll_k =3D div_s64(output_k * 65536ULL * divider, fref); + pll_k =3D DIV_S64_ROUND_CLOSEST(pll_k, MILLI); + + /* Validate K value within allowed limits */ + if (pll_k < limits->k.min || pll_k > limits->k.max) + continue; + + p.k =3D pll_k; + + /* Compute (Ffvco * 65536) */ + fvco =3D mul_u32_u32(p.m * 65536 + p.k, fref); + if ((fvco < mul_u32_u32(limits->fvco.min, 65536)) || + (fvco > mul_u32_u32(limits->fvco.max, 65536))) + continue; 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Fri, 30 May 2025 10:18:53 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:bcab:7ec7:2377:13b0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f00972c1sm5395963f8f.68.2025.05.30.10.18.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 10:18:52 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v6 2/4] clk: renesas: r9a09g057: Add clock and reset entries for DSI and LCDC Date: Fri, 30 May 2025 18:18:39 +0100 Message-ID: <20250530171841.423274-3-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add clock and reset entries for the DSI and LCDC peripherals. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v5->v6: - Renamed CLK_DIV_PLLETH_LPCLK to CLK_CDIV4_PLLETH_LPCLK - Renamed CLK_CSDIV_PLLETH_LPCLK to CLK_PLLETH_LPCLK_GEAR - Renamed CLK_PLLDSI_SDIV2 to CLK_PLLDSI_GEAR - Renamed plldsi_sdiv2 to plldsi_gear v4->v5: - No changes v3->v4: - No changes v2->v3: - Reverted CSDIV0_DIVCTL2() to use DDIV_PACK() - Renamed plleth_lpclk_div4 -> cdiv4_plleth_lpclk - Renamed plleth_lpclk -> plleth_lpclk_gear v1->v2: - Changed CSDIV0_DIVCTL2 to the NO_RMW --- drivers/clk/renesas/r9a09g057-cpg.c | 63 +++++++++++++++++++++++++++++ drivers/clk/renesas/rzv2h-cpg.h | 4 ++ 2 files changed, 67 insertions(+) diff --git a/drivers/clk/renesas/r9a09g057-cpg.c b/drivers/clk/renesas/r9a0= 9g057-cpg.c index 0a877cd30219..4be8240b2505 100644 --- a/drivers/clk/renesas/r9a09g057-cpg.c +++ b/drivers/clk/renesas/r9a09g057-cpg.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -30,6 +31,7 @@ enum clk_ids { CLK_PLLCA55, CLK_PLLVDO, CLK_PLLETH, + CLK_PLLDSI, CLK_PLLGPU, =20 /* Internal Core Clocks */ @@ -63,6 +65,9 @@ enum clk_ids { CLK_SMUX2_GBE0_RXCLK, CLK_SMUX2_GBE1_TXCLK, CLK_SMUX2_GBE1_RXCLK, + CLK_CDIV4_PLLETH_LPCLK, + CLK_PLLETH_LPCLK_GEAR, + CLK_PLLDSI_GEAR, CLK_PLLGPU_GEAR, =20 /* Module Clocks */ @@ -91,6 +96,26 @@ static const struct clk_div_table dtable_2_16[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_2_32[] =3D { + {0, 2}, + {1, 4}, + {2, 6}, + {3, 8}, + {4, 10}, + {5, 12}, + {6, 14}, + {7, 16}, + {8, 18}, + {9, 20}, + {10, 22}, + {11, 24}, + {12, 26}, + {13, 28}, + {14, 30}, + {15, 32}, + {0, 0}, +}; + static const struct clk_div_table dtable_2_64[] =3D { {0, 2}, {1, 4}, @@ -107,6 +132,14 @@ static const struct clk_div_table dtable_2_100[] =3D { {0, 0}, }; =20 +static const struct clk_div_table dtable_16_128[] =3D { + {0, 16}, + {1, 32}, + {2, 64}, + {3, 128}, + {0, 0}, +}; + /* Mux clock tables */ static const char * const smux2_gbe0_rxclk[] =3D { ".plleth_gbe0", "et0_rx= clk" }; static const char * const smux2_gbe0_txclk[] =3D { ".plleth_gbe0", "et0_tx= clk" }; @@ -128,6 +161,7 @@ static const struct cpg_core_clk r9a09g057_core_clks[] = __initconst =3D { DEF_PLL(".pllca55", CLK_PLLCA55, CLK_QEXTAL, PLLCA55), DEF_FIXED(".pllvdo", CLK_PLLVDO, CLK_QEXTAL, 105, 2), DEF_FIXED(".plleth", CLK_PLLETH, CLK_QEXTAL, 125, 3), + DEF_PLLDSI(".plldsi", CLK_PLLDSI, CLK_QEXTAL, PLLDSI), DEF_PLL(".pllgpu", CLK_PLLGPU, CLK_QEXTAL, PLLGPU), =20 /* Internal Core Clocks */ @@ -169,6 +203,12 @@ static const struct cpg_core_clk r9a09g057_core_clks[]= __initconst =3D { DEF_SMUX(".smux2_gbe0_rxclk", CLK_SMUX2_GBE0_RXCLK, SSEL0_SELCTL3, smux2_= gbe0_rxclk), DEF_SMUX(".smux2_gbe1_txclk", CLK_SMUX2_GBE1_TXCLK, SSEL1_SELCTL0, smux2_= gbe1_txclk), DEF_SMUX(".smux2_gbe1_rxclk", CLK_SMUX2_GBE1_RXCLK, SSEL1_SELCTL1, smux2_= gbe1_rxclk), + DEF_FIXED(".cdiv4_plleth_lpclk", CLK_CDIV4_PLLETH_LPCLK, CLK_PLLETH, 1, 4= ), + DEF_CSDIV(".plleth_lpclk_gear", CLK_PLLETH_LPCLK_GEAR, CLK_CDIV4_PLLETH_L= PCLK, + CSDIV0_DIVCTL2, dtable_16_128), + + DEF_PLLDSI_DIV(".plldsi_gear", CLK_PLLDSI_GEAR, CLK_PLLDSI, + CSDIV1_DIVCTL2, dtable_2_32), =20 DEF_DDIV(".pllgpu_gear", CLK_PLLGPU_GEAR, CLK_PLLGPU, CDDIV3_DIVCTL1, dta= ble_2_64), =20 @@ -347,6 +387,22 @@ static const struct rzv2h_mod_clk r9a09g057_mod_clks[]= __initconst =3D { BUS_MSTOP(9, BIT(7))), DEF_MOD("cru_3_pclk", CLK_PLLDTY_DIV16, 13, 13, 6, 29, BUS_MSTOP(9, BIT(7))), + DEF_MOD("dsi_0_pclk", CLK_PLLDTY_DIV16, 14, 8, 7, 8, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_aclk", CLK_PLLDTY_ACPU_DIV2, 14, 9, 7, 9, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_vclk1", CLK_PLLDSI_GEAR, 14, 10, 7, 10, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_lpclk", CLK_PLLETH_LPCLK_GEAR, 14, 11, 7, 11, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("dsi_0_pllref_clk", CLK_QEXTAL, 14, 12, 7, 12, + BUS_MSTOP(9, BIT(14) | BIT(15))), + DEF_MOD("lcdc_0_clk_a", CLK_PLLDTY_ACPU_DIV2, 14, 13, 7, 13, + BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))), + DEF_MOD("lcdc_0_clk_p", CLK_PLLDTY_DIV16, 14, 14, 7, 14, + BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))), + DEF_MOD("lcdc_0_clk_d", CLK_PLLDSI_GEAR, 14, 15, 7, 15, + BUS_MSTOP(10, BIT(1) | BIT(2) | BIT(3))), DEF_MOD("gpu_0_clk", CLK_PLLGPU_GEAR, 15, 0, 7, 16, BUS_MSTOP(3, BIT(4))), DEF_MOD("gpu_0_axi_clk", CLK_PLLDTY_ACPU_DIV2, 15, 1, 7, 17, @@ -410,11 +466,16 @@ static const struct rzv2h_reset r9a09g057_resets[] __= initconst =3D { DEF_RST(12, 14, 5, 31), /* CRU_3_PRESETN */ DEF_RST(12, 15, 6, 0), /* CRU_3_ARESETN */ DEF_RST(13, 0, 6, 1), /* CRU_3_S_RESETN */ + DEF_RST(13, 7, 6, 8), /* DSI_0_PRESETN */ + DEF_RST(13, 8, 6, 9), /* DSI_0_ARESETN */ + DEF_RST(13, 12, 6, 13), /* LCDC_0_RESET_N */ DEF_RST(13, 13, 6, 14), /* GPU_0_RESETN */ DEF_RST(13, 14, 6, 15), /* GPU_0_AXI_RESETN */ DEF_RST(13, 15, 6, 16), /* GPU_0_ACE_RESETN */ }; =20 +RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits); + const struct rzv2h_cpg_info r9a09g057_cpg_info __initconst =3D { /* Core Clocks */ .core_clks =3D r9a09g057_core_clks, @@ -432,4 +493,6 @@ const struct rzv2h_cpg_info r9a09g057_cpg_info __initco= nst =3D { .num_resets =3D ARRAY_SIZE(r9a09g057_resets), =20 .num_mstop_bits =3D 192, + + .plldsi_limits =3D &rzv2h_cpg_pll_dsi_limits, }; diff --git a/drivers/clk/renesas/rzv2h-cpg.h b/drivers/clk/renesas/rzv2h-cp= g.h index 1f1ef2fcf878..864f5e7e8745 100644 --- a/drivers/clk/renesas/rzv2h-cpg.h +++ b/drivers/clk/renesas/rzv2h-cpg.h @@ -28,6 +28,7 @@ struct pll { }) =20 #define PLLCA55 PLL_PACK(0x60, 1) +#define PLLDSI PLL_PACK(0xc0, 1) #define PLLGPU PLL_PACK(0x120, 1) =20 /** @@ -100,6 +101,7 @@ struct smuxed { #define CPG_CDDIV3 (0x40C) #define CPG_CDDIV4 (0x410) #define CPG_CSDIV0 (0x500) +#define CPG_CSDIV1 (0x504) =20 #define CDDIV0_DIVCTL1 DDIV_PACK(CPG_CDDIV0, 4, 3, 1) #define CDDIV0_DIVCTL2 DDIV_PACK(CPG_CDDIV0, 8, 3, 2) @@ -116,7 +118,9 @@ struct smuxed { =20 #define CSDIV0_DIVCTL0 DDIV_PACK(CPG_CSDIV0, 0, 2, CSDIV_NO_MON) #define CSDIV0_DIVCTL1 DDIV_PACK(CPG_CSDIV0, 4, 2, CSDIV_NO_MON) +#define CSDIV0_DIVCTL2 DDIV_PACK(CPG_CSDIV0, 8, 2, CSDIV_NO_MON) #define CSDIV0_DIVCTL3 DDIV_PACK_NO_RMW(CPG_CSDIV0, 12, 2, CSDIV_NO_MON) +#define CSDIV1_DIVCTL2 DDIV_PACK(CPG_CSDIV1, 8, 4, CSDIV_NO_MON) =20 #define SSEL0_SELCTL2 SMUX_PACK(CPG_SSEL0, 8, 1) #define SSEL0_SELCTL3 SMUX_PACK(CPG_SSEL0, 12, 1) --=20 2.49.0 From nobody Thu Dec 18 04:32:29 2025 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DA0EF236A9F; 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Fri, 30 May 2025 10:18:54 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:bcab:7ec7:2377:13b0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f00972c1sm5395963f8f.68.2025.05.30.10.18.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 10:18:54 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar , Krzysztof Kozlowski Subject: [PATCH v6 3/4] dt-bindings: display: bridge: renesas,dsi: Add support for RZ/V2H(P) SoC Date: Fri, 30 May 2025 18:18:40 +0100 Message-ID: <20250530171841.423274-4-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar The MIPI DSI interface on the RZ/V2H(P) SoC is nearly identical to that of the RZ/G2L SoC. While the LINK registers are the same for both SoCs, the D-PHY registers differ. Additionally, the number of resets for DSI on RZ/V2H(P) is two compared to three on the RZ/G2L. To accommodate these differences, a SoC-specific `renesas,r9a09g057-mipi-dsi` compatible string has been added for the RZ/V2H(P) SoC. Signed-off-by: Lad Prabhakar Reviewed-by: Krzysztof Kozlowski Reviewed-by: Geert Uytterhoeven --- v5->v6: - Preserved the sort order (by part number). - Added reviewed tag from Geert. v4->v5: - No changes v3->v4: - No changes v2->v3: - Collected reviewed tag from Krzysztof v1->v2: - Kept the sort order for schema validation - Added `port@1: false` for RZ/V2H(P) SoC --- .../bindings/display/bridge/renesas,dsi.yaml | 116 +++++++++++++----- 1 file changed, 87 insertions(+), 29 deletions(-) diff --git a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.y= aml b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml index e08c24633926..8c7e2b17ba79 100644 --- a/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml +++ b/Documentation/devicetree/bindings/display/bridge/renesas,dsi.yaml @@ -14,16 +14,17 @@ description: | RZ/G2L alike family of SoC's. The encoder can operate in DSI mode, with up to four data lanes. =20 -allOf: - - $ref: /schemas/display/dsi-controller.yaml# - properties: compatible: - items: + oneOf: + - items: + - enum: + - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} + - renesas,r9a07g054-mipi-dsi # RZ/V2L + - const: renesas,rzg2l-mipi-dsi + - enum: - - renesas,r9a07g044-mipi-dsi # RZ/G2{L,LC} - - renesas,r9a07g054-mipi-dsi # RZ/V2L - - const: renesas,rzg2l-mipi-dsi + - renesas,r9a09g057-mipi-dsi # RZ/V2H(P) =20 reg: maxItems: 1 @@ -49,34 +50,56 @@ properties: - const: debug =20 clocks: - items: - - description: DSI D-PHY PLL multiplied clock - - description: DSI D-PHY system clock - - description: DSI AXI bus clock - - description: DSI Register access clock - - description: DSI Video clock - - description: DSI D-PHY Escape mode transmit clock + oneOf: + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI D-PHY system clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock + - items: + - description: DSI D-PHY PLL multiplied clock + - description: DSI AXI bus clock + - description: DSI Register access clock + - description: DSI Video clock + - description: DSI D-PHY Escape mode transmit clock =20 clock-names: - items: - - const: pllclk - - const: sysclk - - const: aclk - - const: pclk - - const: vclk - - const: lpclk + oneOf: + - items: + - const: pllclk + - const: sysclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk + - items: + - const: pllclk + - const: aclk + - const: pclk + - const: vclk + - const: lpclk =20 resets: - items: - - description: MIPI_DSI_CMN_RSTB - - description: MIPI_DSI_ARESET_N - - description: MIPI_DSI_PRESET_N + oneOf: + - items: + - description: MIPI_DSI_CMN_RSTB + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N + - items: + - description: MIPI_DSI_ARESET_N + - description: MIPI_DSI_PRESET_N =20 reset-names: - items: - - const: rst - - const: arst - - const: prst + oneOf: + - items: + - const: rst + - const: arst + - const: prst + - items: + - const: arst + - const: prst =20 power-domains: maxItems: 1 @@ -130,6 +153,41 @@ required: =20 additionalProperties: false =20 +allOf: + - $ref: ../dsi-controller.yaml# + + - if: + properties: + compatible: + contains: + const: renesas,r9a09g057-mipi-dsi + then: + properties: + clocks: + maxItems: 5 + + clock-names: + maxItems: 5 + + resets: + maxItems: 2 + + reset-names: + maxItems: 2 + else: + properties: + clocks: + minItems: 6 + + clock-names: + minItems: 6 + + resets: + minItems: 3 + + reset-names: + minItems: 3 + examples: - | #include --=20 2.49.0 From nobody Thu Dec 18 04:32:29 2025 Received: from mail-wr1-f54.google.com (mail-wr1-f54.google.com [209.85.221.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 14F7B237165; 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Fri, 30 May 2025 10:18:56 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:bcab:7ec7:2377:13b0]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a4f00972c1sm5395963f8f.68.2025.05.30.10.18.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 10:18:55 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Geert Uytterhoeven , Andrzej Hajda , Neil Armstrong , Robert Foss , Laurent Pinchart , Jonas Karlman , Jernej Skrabec , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Biju Das , Magnus Damm Cc: dri-devel@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-clk@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v6 4/4] drm: renesas: rz-du: mipi_dsi: Add support for RZ/V2H(P) SoC Date: Fri, 30 May 2025 18:18:41 +0100 Message-ID: <20250530171841.423274-5-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250530171841.423274-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add DSI support for Renesas RZ/V2H(P) SoC. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar --- v5->v6: - Made use of GENMASK() macro for PLLCLKSET0R_PLL_*, PHYTCLKSETR_* and PHYTHSSETR_* macros. - Replaced 10000000UL with 10 * MEGA - Renamed mode_freq_hz to mode_freq_khz in rzv2h_dsi_mode_calc - Replaced `i -=3D 1;` with `i--;` - Renamed RZV2H_MIPI_DPHY_FOUT_MIN_IN_MEGA to RZV2H_MIPI_DPHY_FOUT_MIN_IN_MHZ and RZV2H_MIPI_DPHY_FOUT_MAX_IN_MEGA to RZV2H_MIPI_DPHY_FOUT_MAX_IN_MHZ. v4->v5: - No changes v3->v4 - In rzv2h_dphy_find_ulpsexit() made the array static const. v2->v3: - Simplifed V2H DSI timings array to save space - Switched to use fsleep() instead of udelay() v1->v2: - Dropped unused macros - Added missing LPCLK flag to rzv2h info --- .../gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 345 ++++++++++++++++++ .../drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h | 34 ++ 2 files changed, 379 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index a31f9b6aa920..ea554ced6713 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -5,6 +5,7 @@ * Copyright (C) 2022 Renesas Electronics Corporation */ #include +#include #include #include #include @@ -30,6 +31,9 @@ =20 #define RZ_MIPI_DSI_FEATURE_16BPP BIT(0) =20 +#define RZV2H_MIPI_DPHY_FOUT_MIN_IN_MHZ (80 * MEGA) +#define RZV2H_MIPI_DPHY_FOUT_MAX_IN_MHZ (1500 * MEGA) + struct rzg2l_mipi_dsi; =20 struct rzg2l_mipi_dsi_hw_info { @@ -40,6 +44,7 @@ struct rzg2l_mipi_dsi_hw_info { u64 *hsfreq_millihz); unsigned int (*dphy_mode_clk_check)(struct rzg2l_mipi_dsi *dsi, unsigned long mode_freq); + const struct rzv2h_pll_div_limits *cpg_dsi_limits; u32 phy_reg_offset; u32 link_reg_offset; unsigned long min_dclk; @@ -47,6 +52,11 @@ struct rzg2l_mipi_dsi_hw_info { u8 features; }; =20 +struct rzv2h_dsi_mode_calc { + unsigned long mode_freq_khz; + u64 mode_freq_hz; +}; + struct rzg2l_mipi_dsi { struct device *dev; void __iomem *mmio; @@ -68,6 +78,18 @@ struct rzg2l_mipi_dsi { unsigned int num_data_lanes; unsigned int lanes; unsigned long mode_flags; + + struct rzv2h_dsi_mode_calc mode_calc; + struct rzv2h_plldsi_parameters dsi_parameters; +}; + +static const struct rzv2h_pll_div_limits rzv2h_plldsi_div_limits =3D { + .fvco =3D { .min =3D 1050 * MEGA, .max =3D 2100 * MEGA }, + .m =3D { .min =3D 64, .max =3D 1023 }, + .p =3D { .min =3D 1, .max =3D 4 }, + .s =3D { .min =3D 0, .max =3D 5 }, + .k =3D { .min =3D -32768, .max =3D 32767 }, + .csdiv =3D { .min =3D 1, .max =3D 1 }, }; =20 static inline struct rzg2l_mipi_dsi * @@ -184,6 +206,155 @@ static const struct rzg2l_mipi_dsi_timings rzg2l_mipi= _dsi_global_timings[] =3D { }, }; =20 +struct rzv2h_mipi_dsi_timings { + const u8 *hsfreq; + u8 len; + u8 start_index; +}; + +enum { + TCLKPRPRCTL, + TCLKZEROCTL, + TCLKPOSTCTL, + TCLKTRAILCTL, + THSPRPRCTL, + THSZEROCTL, + THSTRAILCTL, + TLPXCTL, + THSEXITCTL, +}; + +static const u8 tclkprprctl[] =3D { + 15, 26, 37, 47, 58, 69, 79, 90, 101, 111, 122, 133, 143, 150, +}; + +static const u8 tclkzeroctl[] =3D { + 9, 11, 13, 15, 18, 21, 23, 24, 25, 27, 29, 31, 34, 36, 38, + 41, 43, 45, 47, 50, 52, 54, 57, 59, 61, 63, 66, 68, 70, 73, + 75, 77, 79, 82, 84, 86, 89, 91, 93, 95, 98, 100, 102, 105, + 107, 109, 111, 114, 116, 118, 121, 123, 125, 127, 130, 132, + 134, 137, 139, 141, 143, 146, 148, 150, +}; + +static const u8 tclkpostctl[] =3D { + 8, 21, 34, 48, 61, 74, 88, 101, 114, 128, 141, 150, +}; + +static const u8 tclktrailctl[] =3D { + 14, 25, 37, 48, 59, 71, 82, 94, 105, 117, 128, 139, 150, +}; + +static const u8 thsprprctl[] =3D { + 11, 19, 29, 40, 50, 61, 72, 82, 93, 103, 114, 125, 135, 146, 150, +}; + +static const u8 thszeroctl[] =3D { + 18, 24, 29, 35, 40, 46, 51, 57, 62, 68, 73, 79, 84, 90, + 95, 101, 106, 112, 117, 123, 128, 134, 139, 145, 150, +}; + +static const u8 thstrailctl[] =3D { + 10, 21, 32, 42, 53, 64, 75, 85, 96, 107, 118, 128, 139, 150, +}; + +static const u8 tlpxctl[] =3D { + 13, 26, 39, 53, 66, 79, 93, 106, 119, 133, 146, 150, +}; + +static const u8 thsexitctl[] =3D { + 15, 23, 31, 39, 47, 55, 63, 71, 79, 87, + 95, 103, 111, 119, 127, 135, 143, 150, +}; + +static const struct rzv2h_mipi_dsi_timings rzv2h_dsi_timings_tables[] =3D { + [TCLKPRPRCTL] =3D { + .hsfreq =3D tclkprprctl, + .len =3D ARRAY_SIZE(tclkprprctl), + .start_index =3D 0, + }, + [TCLKZEROCTL] =3D { + .hsfreq =3D tclkzeroctl, + .len =3D ARRAY_SIZE(tclkzeroctl), + .start_index =3D 2, + }, + [TCLKPOSTCTL] =3D { + .hsfreq =3D tclkpostctl, + .len =3D ARRAY_SIZE(tclkpostctl), + .start_index =3D 6, + }, + [TCLKTRAILCTL] =3D { + .hsfreq =3D tclktrailctl, + .len =3D ARRAY_SIZE(tclktrailctl), + .start_index =3D 1, + }, + [THSPRPRCTL] =3D { + .hsfreq =3D thsprprctl, + .len =3D ARRAY_SIZE(thsprprctl), + .start_index =3D 0, + }, + [THSZEROCTL] =3D { + .hsfreq =3D thszeroctl, + .len =3D ARRAY_SIZE(thszeroctl), + .start_index =3D 0, + }, + [THSTRAILCTL] =3D { + .hsfreq =3D thstrailctl, + .len =3D ARRAY_SIZE(thstrailctl), + .start_index =3D 3, + }, + [TLPXCTL] =3D { + .hsfreq =3D tlpxctl, + .len =3D ARRAY_SIZE(tlpxctl), + .start_index =3D 0, + }, + [THSEXITCTL] =3D { + .hsfreq =3D thsexitctl, + .len =3D ARRAY_SIZE(thsexitctl), + .start_index =3D 1, + }, +}; + +static u16 rzv2h_dphy_find_ulpsexit(unsigned long freq) +{ + static const unsigned long hsfreq[] =3D { + 1953125UL, + 3906250UL, + 7812500UL, + 15625000UL, + }; + static const u16 ulpsexit[] =3D {49, 98, 195, 391}; + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(hsfreq); i++) { + if (freq <=3D hsfreq[i]) + break; + } + + if (i =3D=3D ARRAY_SIZE(hsfreq)) + i--; + + return ulpsexit[i]; +} + +static u16 rzv2h_dphy_find_timings_val(unsigned long freq, u8 index) +{ + const struct rzv2h_mipi_dsi_timings *timings; + u16 i; + + timings =3D &rzv2h_dsi_timings_tables[index]; + for (i =3D 0; i < timings->len; i++) { + unsigned long hsfreq =3D timings->hsfreq[i] * 10 * MEGA; + + if (freq <=3D hsfreq) + break; + } + + if (i =3D=3D timings->len) + i--; + + return timings->start_index + i; +}; + static void rzg2l_mipi_dsi_phy_write(struct rzg2l_mipi_dsi *dsi, u32 reg, = u32 data) { iowrite32(data, dsi->mmio + dsi->info->phy_reg_offset + reg); @@ -308,6 +479,160 @@ static int rzg2l_dphy_conf_clks(struct rzg2l_mipi_dsi= *dsi, unsigned long mode_f return 0; } =20 +static unsigned int rzv2h_dphy_mode_clk_check(struct rzg2l_mipi_dsi *dsi, + unsigned long mode_freq) +{ + struct rzv2h_plldsi_parameters cpg_dsi_parameters; + struct rzv2h_plldsi_parameters dsi_parameters; + u64 hsfreq_millihz, mode_freq_hz, mode_freq_millihz; + unsigned int bpp, i; + + bpp =3D mipi_dsi_pixel_format_to_bpp(dsi->format); + + for (i =3D 0; i < 10; i +=3D 1) { + unsigned long hsfreq; + bool parameters_found; + + mode_freq_hz =3D mul_u32_u32(mode_freq, KILO) + i; + mode_freq_millihz =3D mode_freq_hz * MILLI; + parameters_found =3D rzv2h_dsi_get_pll_parameters_values(dsi->info->cpg_= dsi_limits, + &cpg_dsi_parameters, + mode_freq_millihz); + if (!parameters_found) + continue; + + hsfreq_millihz =3D DIV_ROUND_CLOSEST_ULL(cpg_dsi_parameters.freq_millihz= * bpp, + dsi->lanes); + parameters_found =3D rzv2h_dsi_get_pll_parameters_values(&rzv2h_plldsi_d= iv_limits, + &dsi_parameters, + hsfreq_millihz); + if (!parameters_found) + continue; + + if (abs(dsi_parameters.error_millihz) >=3D 500) + continue; + + hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); + if (hsfreq >=3D RZV2H_MIPI_DPHY_FOUT_MIN_IN_MHZ && + hsfreq <=3D RZV2H_MIPI_DPHY_FOUT_MAX_IN_MHZ) { + memcpy(&dsi->dsi_parameters, &dsi_parameters, sizeof(dsi->dsi_parameter= s)); + dsi->mode_calc.mode_freq_khz =3D mode_freq; + dsi->mode_calc.mode_freq_hz =3D mode_freq_hz; + return MODE_OK; + } + } + + return MODE_CLOCK_RANGE; +} + +static int rzv2h_dphy_conf_clks(struct rzg2l_mipi_dsi *dsi, unsigned long = mode_freq, + u64 *hsfreq_millihz) +{ + struct rzv2h_plldsi_parameters *dsi_parameters =3D &dsi->dsi_parameters; + unsigned long status; + + if (dsi->mode_calc.mode_freq_khz !=3D mode_freq) { + status =3D rzv2h_dphy_mode_clk_check(dsi, mode_freq); + if (status !=3D MODE_OK) { + dev_err(dsi->dev, "No PLL parameters found for mode clk %lu\n", + mode_freq); + return -EINVAL; + } + } + + clk_set_rate(dsi->vclk, dsi->mode_calc.mode_freq_hz); + *hsfreq_millihz =3D dsi_parameters->freq_millihz; + + return 0; +} + +static int rzv2h_mipi_dsi_dphy_init(struct rzg2l_mipi_dsi *dsi, + u64 hsfreq_millihz) +{ + struct rzv2h_plldsi_parameters *dsi_parameters =3D &dsi->dsi_parameters; + unsigned long lpclk_rate =3D clk_get_rate(dsi->lpclk); + u32 phytclksetr, phythssetr, phytlpxsetr, phycr; + struct rzg2l_mipi_dsi_timings dphy_timings; + u16 ulpsexit; + u64 hsfreq; + + hsfreq =3D DIV_ROUND_CLOSEST_ULL(hsfreq_millihz, MILLI); + + if (dsi_parameters->freq_millihz =3D=3D hsfreq_millihz) + goto parameters_found; + + if (rzv2h_dsi_get_pll_parameters_values(&rzv2h_plldsi_div_limits, + dsi_parameters, hsfreq_millihz)) + goto parameters_found; + + dev_err(dsi->dev, "No PLL parameters found for HSFREQ %lluHz\n", hsfreq); + return -EINVAL; + +parameters_found: + dphy_timings.tclk_trail =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKTRAILCTL); + dphy_timings.tclk_post =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKPOSTCTL); + dphy_timings.tclk_zero =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKZEROCTL); + dphy_timings.tclk_prepare =3D + rzv2h_dphy_find_timings_val(hsfreq, TCLKPRPRCTL); + dphy_timings.ths_exit =3D + rzv2h_dphy_find_timings_val(hsfreq, THSEXITCTL); + dphy_timings.ths_trail =3D + rzv2h_dphy_find_timings_val(hsfreq, THSTRAILCTL); + dphy_timings.ths_zero =3D + rzv2h_dphy_find_timings_val(hsfreq, THSZEROCTL); + dphy_timings.ths_prepare =3D + rzv2h_dphy_find_timings_val(hsfreq, THSPRPRCTL); + dphy_timings.tlpx =3D + rzv2h_dphy_find_timings_val(hsfreq, TLPXCTL); + ulpsexit =3D rzv2h_dphy_find_ulpsexit(lpclk_rate); + + phytclksetr =3D FIELD_PREP(PHYTCLKSETR_TCLKTRAILCTL, dphy_timings.tclk_tr= ail) | + FIELD_PREP(PHYTCLKSETR_TCLKPOSTCTL, dphy_timings.tclk_post) | + FIELD_PREP(PHYTCLKSETR_TCLKZEROCTL, dphy_timings.tclk_zero) | + FIELD_PREP(PHYTCLKSETR_TCLKPRPRCTL, dphy_timings.tclk_prepare); + phythssetr =3D FIELD_PREP(PHYTHSSETR_THSEXITCTL, dphy_timings.ths_exit) | + FIELD_PREP(PHYTHSSETR_THSTRAILCTL, dphy_timings.ths_trail) | + FIELD_PREP(PHYTHSSETR_THSZEROCTL, dphy_timings.ths_zero) | + FIELD_PREP(PHYTHSSETR_THSPRPRCTL, dphy_timings.ths_prepare); + phytlpxsetr =3D rzg2l_mipi_dsi_phy_read(dsi, PHYTLPXSETR) & ~PHYTLPXSETR_= TLPXCTL; + phytlpxsetr |=3D FIELD_PREP(PHYTLPXSETR_TLPXCTL, dphy_timings.tlpx); + phycr =3D rzg2l_mipi_dsi_phy_read(dsi, PHYCR) & ~GENMASK(9, 0); + phycr |=3D FIELD_PREP(PHYCR_ULPSEXIT, ulpsexit); + + /* Setting all D-PHY Timings Registers */ + rzg2l_mipi_dsi_phy_write(dsi, PHYTCLKSETR, phytclksetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYTHSSETR, phythssetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYTLPXSETR, phytlpxsetr); + rzg2l_mipi_dsi_phy_write(dsi, PHYCR, phycr); + + rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET0R, + FIELD_PREP(PLLCLKSET0R_PLL_S, dsi_parameters->s) | + FIELD_PREP(PLLCLKSET0R_PLL_P, dsi_parameters->p) | + FIELD_PREP(PLLCLKSET0R_PLL_M, dsi_parameters->m)); + rzg2l_mipi_dsi_phy_write(dsi, PLLCLKSET1R, + FIELD_PREP(PLLCLKSET1R_PLL_K, dsi_parameters->k)); + fsleep(20); + + rzg2l_mipi_dsi_phy_write(dsi, PLLENR, PLLENR_PLLEN); + fsleep(500); + + return 0; +} + +static void rzv2h_mipi_dsi_dphy_startup_late_init(struct rzg2l_mipi_dsi *d= si) +{ + fsleep(220); + rzg2l_mipi_dsi_phy_write(dsi, PHYRSTR, PHYRSTR_PHYMRSTN); +} + +static void rzv2h_mipi_dsi_dphy_exit(struct rzg2l_mipi_dsi *dsi) +{ + rzg2l_mipi_dsi_phy_write(dsi, PLLENR, 0); +} + static int rzg2l_mipi_dsi_startup(struct rzg2l_mipi_dsi *dsi, const struct drm_display_mode *mode) { @@ -410,6 +735,9 @@ static void rzg2l_mipi_dsi_set_display_timing(struct rz= g2l_mipi_dsi *dsi, case 18: vich1ppsetr =3D VICH1PPSETR_DT_RGB18; break; + case 16: + vich1ppsetr =3D VICH1PPSETR_DT_RGB16; + break; } =20 if ((dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) && @@ -862,6 +1190,22 @@ static void rzg2l_mipi_dsi_remove(struct platform_dev= ice *pdev) pm_runtime_disable(&pdev->dev); } =20 +RZV2H_CPG_PLL_DSI_LIMITS(rzv2h_cpg_pll_dsi_limits); + +static const struct rzg2l_mipi_dsi_hw_info rzv2h_mipi_dsi_info =3D { + .dphy_init =3D rzv2h_mipi_dsi_dphy_init, + .dphy_startup_late_init =3D rzv2h_mipi_dsi_dphy_startup_late_init, + .dphy_exit =3D rzv2h_mipi_dsi_dphy_exit, + .dphy_mode_clk_check =3D rzv2h_dphy_mode_clk_check, + .dphy_conf_clks =3D rzv2h_dphy_conf_clks, + .cpg_dsi_limits =3D &rzv2h_cpg_pll_dsi_limits, + .phy_reg_offset =3D 0x10000, + .link_reg_offset =3D 0, + .min_dclk =3D 5440, + .max_dclk =3D 187500, + .features =3D RZ_MIPI_DSI_FEATURE_16BPP, +}; + static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_dsi_info =3D { .dphy_init =3D rzg2l_mipi_dsi_dphy_init, .dphy_exit =3D rzg2l_mipi_dsi_dphy_exit, @@ -872,6 +1216,7 @@ static const struct rzg2l_mipi_dsi_hw_info rzg2l_mipi_= dsi_info =3D { }; =20 static const struct of_device_id rzg2l_mipi_dsi_of_table[] =3D { + { .compatible =3D "renesas,r9a09g057-mipi-dsi", .data =3D &rzv2h_mipi_dsi= _info, }, { .compatible =3D "renesas,rzg2l-mipi-dsi", .data =3D &rzg2l_mipi_dsi_inf= o, }, { /* sentinel */ } }; diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h b/drivers/= gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h index 16efe4dc59f4..87963871cacd 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi_regs.h @@ -40,6 +40,39 @@ #define DSIDPHYTIM3_THS_TRAIL(x) ((x) << 8) #define DSIDPHYTIM3_THS_ZERO(x) ((x) << 0) =20 +/* RZ/V2H DPHY Registers */ +#define PLLENR 0x000 +#define PLLENR_PLLEN BIT(0) + +#define PHYRSTR 0x004 +#define PHYRSTR_PHYMRSTN BIT(0) + +#define PLLCLKSET0R 0x010 +#define PLLCLKSET0R_PLL_S GENMASK(2, 0) +#define PLLCLKSET0R_PLL_P GENMASK(13, 8) +#define PLLCLKSET0R_PLL_M GENMASK(25, 16) + +#define PLLCLKSET1R 0x014 +#define PLLCLKSET1R_PLL_K GENMASK(15, 0) + +#define PHYTCLKSETR 0x020 +#define PHYTCLKSETR_TCLKTRAILCTL GENMASK(7, 0) +#define PHYTCLKSETR_TCLKPOSTCTL GENMASK(15, 8) +#define PHYTCLKSETR_TCLKZEROCTL GENMASK(23, 16) +#define PHYTCLKSETR_TCLKPRPRCTL GENMASK(31, 24) + +#define PHYTHSSETR 0x024 +#define PHYTHSSETR_THSEXITCTL GENMASK(7, 0) +#define PHYTHSSETR_THSTRAILCTL GENMASK(15, 8) +#define PHYTHSSETR_THSZEROCTL GENMASK(23, 16) +#define PHYTHSSETR_THSPRPRCTL GENMASK(31, 24) + +#define PHYTLPXSETR 0x028 +#define PHYTLPXSETR_TLPXCTL GENMASK(7, 0) + +#define PHYCR 0x030 +#define PHYCR_ULPSEXIT GENMASK(9, 0) + /* --------------------------------------------------------*/ =20 /* Link Status Register */ @@ -116,6 +149,7 @@ =20 /* Video-Input Channel 1 Pixel Packet Set Register */ #define VICH1PPSETR 0x420 +#define VICH1PPSETR_DT_RGB16 (0x0e << 16) #define VICH1PPSETR_DT_RGB18 (0x1e << 16) #define VICH1PPSETR_DT_RGB18_LS (0x2e << 16) #define VICH1PPSETR_DT_RGB24 (0x3e << 16) --=20 2.49.0