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Fri, 30 May 2025 09:59:25 -0700 (PDT) Received: from iku.example.org ([2a06:5906:61b:2d00:bcab:7ec7:2377:13b0]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450d7f9efa3sm22733455e9.9.2025.05.30.09.59.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 09:59:25 -0700 (PDT) From: Prabhakar X-Google-Original-From: Prabhakar To: Biju Das , Laurent Pinchart , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm Cc: dri-devel@lists.freedesktop.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Fabrizio Castro , Lad Prabhakar Subject: [PATCH v6 12/12] drm: renesas: rz-du: mipi_dsi: Add support for LPCLK clock handling Date: Fri, 30 May 2025 17:59:06 +0100 Message-ID: <20250530165906.411144-13-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailer: git-send-email 2.49.0 In-Reply-To: <20250530165906.411144-1-prabhakar.mahadev-lad.rj@bp.renesas.com> References: <20250530165906.411144-1-prabhakar.mahadev-lad.rj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Lad Prabhakar Add LPCLK clock support in the RZ/G2L MIPI DSI driver via the optional clock API. This clock is required by some SoCs like RZ/V2H(P) for proper DPHY configuration, whereas it is absent on others like RZ/G2L. Introduce a new `lpclk` field in the `rzg2l_mipi_dsi` structure and conditionally acquire the "lpclk" clock using `devm_clk_get_optional()` during probe. This allows LPCLK-aware SoCs to pass the clock via device tree without impacting existing platforms. Co-developed-by: Fabrizio Castro Signed-off-by: Fabrizio Castro Signed-off-by: Lad Prabhakar Reviewed-by: Biju Das --- v5->v6: - No changes v4->v5: - Made use of devm_clk_get_optional() for lpclk - Added Reviewed tag from Biju v3->v4 - No changes v2->v3: - No changes v1->v2: - Added LPCLK as feature flag --- drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c b/drivers/gpu/d= rm/renesas/rz-du/rzg2l_mipi_dsi.c index f9f2d883c40d..a31f9b6aa920 100644 --- a/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c +++ b/drivers/gpu/drm/renesas/rz-du/rzg2l_mipi_dsi.c @@ -62,6 +62,7 @@ struct rzg2l_mipi_dsi { struct drm_bridge *next_bridge; =20 struct clk *vclk; + struct clk *lpclk; =20 enum mipi_dsi_pixel_format format; unsigned int num_data_lanes; @@ -791,6 +792,10 @@ static int rzg2l_mipi_dsi_probe(struct platform_device= *pdev) if (IS_ERR(dsi->vclk)) return PTR_ERR(dsi->vclk); =20 + dsi->lpclk =3D devm_clk_get_optional(dsi->dev, "lpclk"); + if (IS_ERR(dsi->lpclk)) + return PTR_ERR(dsi->lpclk); + dsi->rstc =3D devm_reset_control_get_optional_exclusive(dsi->dev, "rst"); if (IS_ERR(dsi->rstc)) return dev_err_probe(dsi->dev, PTR_ERR(dsi->rstc), --=20 2.49.0