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Fri, 30 May 2025 06:35:53 -0700 From: Sumit Gupta To: , , , , , , , CC: <--to=tbergstrom@nvidia.com>, , Subject: [Patch 7/8] soc: tegra: cbb: add support for cbb fabrics in Tegra264 Date: Fri, 30 May 2025 19:03:35 +0530 Message-ID: <20250530133336.1419971-8-sumitg@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250530133336.1419971-1-sumitg@nvidia.com> References: <20250530133336.1419971-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB78:EE_|LV8PR12MB9335:EE_ X-MS-Office365-Filtering-Correlation-Id: 7fdc2c6d-1dc6-4c98-ee00-08dd9f7ef2d5 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2025 13:36:14.3765 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7fdc2c6d-1dc6-4c98-ee00-08dd9f7ef2d5 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB78.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV8PR12MB9335 Content-Type: text/plain; charset="utf-8" Add support for CBB 2.0 based fabrics in Tegra264 SoC using DT. Fabrics reporting errors are: SYSTEM, TOP0, UPHY0, VISION. Signed-off-by: Sumit Gupta --- drivers/soc/tegra/cbb/tegra234-cbb.c | 279 +++++++++++++++++++++++++++ 1 file changed, 279 insertions(+) diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/t= egra234-cbb.c index aab0cd85dea5..69c704938679 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -89,6 +89,34 @@ enum tegra234_cbb_fabric_ids { T234_MAX_FABRIC_ID, }; =20 +enum tegra264_cbb_fabric_ids { + T264_SYSTEM_CBB_FABRIC_ID, + T264_TOP_0_CBB_FABRIC_ID, + T264_VISION_CBB_FABRIC_ID, + T264_DISP_USB_CBB_FABRIC_ID, + T264_UPHY0_CBB_FABRIC_ID, + T264_RSVD0_FABRIC_ID, + T264_RSVD1_FABRIC_ID, + T264_RSVD2_FABRIC_ID, + T264_RSVD3_FABRIC_ID, + T264_RSVD4_FABRIC_ID, + T264_RSVD5_FABRIC_ID, + T264_AON_FABRIC_ID, + T264_PSC_FABRIC_ID, + T264_OESP_FABRIC_ID, + T264_APE_FABRIC_ID, + T264_BPMP_FABRIC_ID, + T264_RCE_0_FABRIC_ID, + T264_RCE_1_FABRIC_ID, + T264_RSVD6_FABRIC_ID, + T264_DCE_FABRIC_ID, + T264_FSI_FABRIC_ID, + T264_ISC_FABRIC_ID, + T264_SB_FABRIC_ID, + T264_ISC_CPU_FABRIC_ID, + T264_RSVD7_FABRIC_ID, +}; + struct tegra234_target_lookup { const char *name; unsigned int offset; @@ -455,6 +483,17 @@ static void print_errlog_err(struct seq_file *file, st= ruct tegra234_cbb *cbb) tegra_cbb_print_err(file, "\t Fabric\t\t: %s (id:%#x)\n", cbb->fabric->fab_list[fab_id].name, fab_id); =20 + if (of_machine_is_compatible("nvidia,tegra264") && fab_id =3D=3D T264_UPH= Y0_CBB_FABRIC_ID) { + /* + * In T264, AON Fabric ID value is incorrectly same as UPHY0 fabric ID. + * For 'ID =3D 0x4', we must check for the address which caused the error + * to find the correct fabric which returned error. + */ + tegra_cbb_print_err(file, "\t or Fabric\t\t: %s\n", + cbb->fabric->fab_list[T264_AON_FABRIC_ID].name); + tegra_cbb_print_err(file, "\t Please use Address to determine correct f= abric.\n"); + } + tegra_cbb_print_err(file, "\t Target_Id\t\t: %#x\n", target_id); tegra_cbb_print_err(file, "\t Burst_length\t\t: %#x\n", burst_length); tegra_cbb_print_err(file, "\t Burst_type\t\t: %#x\n", burst_type); @@ -1143,6 +1182,242 @@ static const struct tegra234_cbb_fabric tegra241_bp= mp_fabric =3D { .firewall_wr_ctl =3D 0x8e8, }; =20 +static const char * const tegra264_initiator_id[] =3D { + [0x0] =3D "TZ", + [0x1] =3D "CCPLEX", + [0x2] =3D "ISC", + [0x3] =3D "BPMP_FW", + [0x4] =3D "AON", + [0x5] =3D "MSS_SEQ", + [0x6] =3D "GPCDMA_P", + [0x7] =3D "TSECA_NONSECURE", + [0x8] =3D "TSECA_LIGHTSECURE", + [0x9] =3D "TSECA_HEAVYSECURE", + [0xa] =3D "CORESIGHT", + [0xb] =3D "APE_0", + [0xc] =3D "APE_1", + [0xd] =3D "PEATRANS", + [0xe] =3D "JTAGM_DFT", + [0xf] =3D "RCE", + [0x10] =3D "DCE", + [0x11] =3D "PSC_FW_USER", + [0x12] =3D "PSC_FW_SUPERVISOR", + [0x13] =3D "PSC_FW_MACHINE", + [0x14] =3D "PSC_BOOT", + [0x15] =3D "BPMP_BOOT", + [0x16] =3D "GPU_0", + [0x17] =3D "GPU_1", + [0x18] =3D "GPU_2", + [0x19] =3D "GPU_3", + [0x1a] =3D "GPU_4", + [0x1b] =3D "PSC_EXT_BOOT", + [0x1c] =3D "PSC_EXT_RUNTIME", + [0x1d] =3D "OESP_EXT", + [0x1e] =3D "SB_EXT", + [0x1f] =3D "FSI_SAFETY_0", + [0x20] =3D "FSI_SAFETY_1", + [0x21] =3D "FSI_SAFETY_2", + [0x22] =3D "FSI_SAFETY_3", + [0x23] =3D "FSI_CHSM", + [0x24] =3D "RCE_1", + [0x25] =3D "BPMP_OEM_FW", + [0x26 ... 0x3d] =3D "RSVD", + [0x3e] =3D "CBB_SMN", + [0x3f] =3D "CBB_RSVD" +}; + +static const struct tegra234_target_lookup tegra264_top0_cbb_target_map[] = =3D { + { "RSVD", 0x000000 }, + { "CBB_CENTRAL", 0xC020000 }, + { "AXI2APB_1", 0x80000 }, + { "AXI2APB_10", 0x81000 }, + { "AXI2APB_11", 0x82000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_14", 0x83000 }, + { "AXI2APB_15", 0x84000 }, + { "AXI2APB_16", 0x85000 }, + { "AXI2APB_17", 0x86000 }, + { "AXI2APB_2", 0x87000 }, + { "AXI2APB_3", 0x88000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_5", 0x8A000 }, + { "AXI2APB_6", 0x8B000 }, + { "AXI2APB_7", 0x8C000 }, + { "AXI2APB_8", 0x8D000 }, + { "AXI2APB_9", 0x8E000 }, + { "FSI_SLAVE", 0x64000 }, + { "DISP_USB_CBB_T", 0x65000 }, + { "SYSTEM_CBB_T", 0x66000 }, + { "UPHY0_CBB_T", 0x67000 }, + { "VISION_CBB_T", 0x68000 }, + { "CCPLEX_SLAVE", 0x69000 }, + { "PCIE_C0", 0x6A000 }, + { "SMN_UCF_RX_0", 0x6B000 }, + { "SMN_UCF_RX_1", 0x6C000 }, + { "AXI2APB_4", 0x89000 }, +}; + +static const struct tegra234_target_lookup tegra264_sys_cbb_target_map[] = =3D { + { "RSVD", 0x00000 }, + { "AXI2APB_1", 0xE1000 }, + { "RSVD", 0x00000 }, + { "AON_SLAVE", 0x79000 }, + { "APE_SLAVE", 0x73000 }, + { "BPMP_SLAVE", 0x74000 }, + { "OESP_SLAVE", 0x75000 }, + { "PSC_SLAVE", 0x76000 }, + { "SB_SLAVE", 0x7A000 }, + { "SMN_SYSTEM_RX", 0x7B000 }, + { "STM", 0x77000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_3", 0xE3000 }, + { "TOP_CBB_T", 0x7C000 }, + { "AXI2APB_2", 0xE4000 }, + { "AXI2APB_4", 0xE5000 }, + { "AXI2APB_5", 0xE6000 }, +}; + +static const struct tegra234_target_lookup tegra264_uphy0_cbb_target_map[]= =3D { + [0 ... 20] =3D { "RSVD", 0x00000 }, + { "AXI2APB_1", 0x71000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_3", 0x75000 }, + { "SMN_UPHY0_RX", 0x53000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "PCIE_C4", 0x4B000 }, + { "AXI2APB_2", 0x74000 }, + { "AXI2APB_4", 0x76000 }, + { "AXI2APB_5", 0x77000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_7", 0x79000 }, + { "PCIE_C2", 0x56000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "PCIE_C1", 0x55000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_10", 0x72000 }, + { "AXI2APB_11", 0x7C000 }, + { "AXI2APB_8", 0x7A000 }, + { "AXI2APB_9", 0x7B000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "PCIE_C5", 0x4E000 }, + { "PCIE_C3", 0x58000 }, + { "RSVD", 0x00000 }, + { "ISC_SLAVE", 0x54000 }, + { "TOP_CBB_T", 0x57000 }, + { "AXI2APB_12", 0x7D000 }, + { "AXI2APB_13", 0x70000 }, + { "AXI2APB_6", 0x7E000 }, +}; + +static const struct tegra234_target_lookup tegra264_vision_cbb_target_map[= ] =3D { + [0 ... 5] =3D { "RSVD", 0x0 }, + { "HOST1X", 0x45000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "AXI2APB_2", 0x71000 }, + { "RSVD", 0x00000 }, + { "RSVD", 0x00000 }, + { "SMN_VISION_RX", 0x47000 }, + [13 ... 19] =3D { "RSVD", 0x0 }, + { "RCE_0_SLAVE", 0x4B000 }, + { "RCE_1_SLAVE", 0x4C000 }, + { "AXI2APB_1", 0x72000 }, + { "AXI2APB_3", 0x73000 }, + { "TOP_CBB_T", 0x4D000 }, + +}; + +static const struct tegra234_fabric_lookup tegra264_cbb_fab_list[] =3D { + [T264_SYSTEM_CBB_FABRIC_ID] =3D { "system-cbb-fabric", true, + tegra264_sys_cbb_target_map, + ARRAY_SIZE(tegra264_sys_cbb_target_map) }, + [T264_TOP_0_CBB_FABRIC_ID] =3D { "top0-cbb-fabric", true, + tegra264_top0_cbb_target_map, + ARRAY_SIZE(tegra264_top0_cbb_target_map) }, + [T264_VISION_CBB_FABRIC_ID] =3D { "vision-cbb-fabric", true, + tegra264_vision_cbb_target_map, + ARRAY_SIZE(tegra264_vision_cbb_target_map) }, + [T264_DISP_USB_CBB_FABRIC_ID] =3D { "disp-usb-cbb-fabric" }, + [T264_UPHY0_CBB_FABRIC_ID] =3D { "uphy0-cbb-fabric", true, + tegra264_uphy0_cbb_target_map, + ARRAY_SIZE(tegra264_uphy0_cbb_target_map) }, + [T264_AON_FABRIC_ID] =3D { "aon-fabric" }, + [T264_PSC_FABRIC_ID] =3D { "psc-fabric" }, + [T264_OESP_FABRIC_ID] =3D { "oesp-fabric" }, + [T264_APE_FABRIC_ID] =3D { "ape-fabirc" }, + [T264_BPMP_FABRIC_ID] =3D { "bpmp-fabric" }, + [T264_RCE_0_FABRIC_ID] =3D { "rce0-fabric" }, + [T264_RCE_1_FABRIC_ID] =3D { "rce1-fabric" }, + [T264_DCE_FABRIC_ID] =3D { "dce-fabric" }, + [T264_FSI_FABRIC_ID] =3D { "fsi-fabric" }, + [T264_ISC_FABRIC_ID] =3D { "isc-fabric" }, + [T264_SB_FABRIC_ID] =3D { "sb-fabric" }, + [T264_ISC_CPU_FABRIC_ID] =3D { "isc-cpu-fabric" }, +}; + +static const struct tegra234_cbb_fabric tegra264_top0_cbb_fabric =3D { + .fab_id =3D T264_TOP_0_CBB_FABRIC_ID, + .fab_list =3D tegra264_cbb_fab_list, + .initiator_id =3D tegra264_initiator_id, + .errors =3D tegra241_cbb_errors, + .max_errors =3D ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl =3D 0x7, + .err_status_clr =3D 0x1ff007f, + .notifier_offset =3D 0x90000, + .off_mask_erd =3D 0x4a004, + .firewall_base =3D 0x3c0000, + .firewall_ctl =3D 0x5b0, + .firewall_wr_ctl =3D 0x5a8, +}; + +static const struct tegra234_cbb_fabric tegra264_sys_cbb_fabric =3D { + .fab_id =3D T264_SYSTEM_CBB_FABRIC_ID, + .fab_list =3D tegra264_cbb_fab_list, + .initiator_id =3D tegra264_initiator_id, + .errors =3D tegra241_cbb_errors, + .max_errors =3D ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl =3D 0xf, + .err_status_clr =3D 0x1ff007f, + .notifier_offset =3D 0x40000, + .firewall_base =3D 0x29c000, + .firewall_ctl =3D 0x170, + .firewall_wr_ctl =3D 0x168, +}; + +static const struct tegra234_cbb_fabric tegra264_uphy0_cbb_fabric =3D { + .fab_id =3D T264_UPHY0_CBB_FABRIC_ID, + .fab_list =3D tegra264_cbb_fab_list, + .initiator_id =3D tegra264_initiator_id, + .errors =3D tegra241_cbb_errors, + .max_errors =3D ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl =3D 0x1, + .err_status_clr =3D 0x1ff007f, + .notifier_offset =3D 0x80000, + .firewall_base =3D 0x360000, + .firewall_ctl =3D 0x590, + .firewall_wr_ctl =3D 0x588, +}; + +static const struct tegra234_cbb_fabric tegra264_vision_cbb_fabric =3D { + .fab_id =3D T264_VISION_CBB_FABRIC_ID, + .fab_list =3D tegra264_cbb_fab_list, + .initiator_id =3D tegra264_initiator_id, + .errors =3D tegra241_cbb_errors, + .max_errors =3D ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl =3D 0x1, + .err_status_clr =3D 0x1ff007f, + .notifier_offset =3D 0x80000, + .firewall_base =3D 0x290000, + .firewall_ctl =3D 0x5d0, + .firewall_wr_ctl =3D 0x5c8, +}; + static const struct of_device_id tegra234_cbb_dt_ids[] =3D { { .compatible =3D "nvidia,tegra234-cbb-fabric", .data =3D &tegra234_cbb_f= abric }, { .compatible =3D "nvidia,tegra234-aon-fabric", .data =3D &tegra234_aon_f= abric }, @@ -1150,6 +1425,10 @@ static const struct of_device_id tegra234_cbb_dt_ids= [] =3D { { .compatible =3D "nvidia,tegra234-dce-fabric", .data =3D &tegra234_dce_f= abric }, { .compatible =3D "nvidia,tegra234-rce-fabric", .data =3D &tegra234_rce_f= abric }, { .compatible =3D "nvidia,tegra234-sce-fabric", .data =3D &tegra234_sce_f= abric }, + { .compatible =3D "nvidia,tegra264-sys-cbb-fabric", .data =3D &tegra264_s= ys_cbb_fabric }, + { .compatible =3D "nvidia,tegra264-top0-cbb-fabric", .data =3D &tegra264_= top0_cbb_fabric }, + { .compatible =3D "nvidia,tegra264-uphy0-cbb-fabric", .data =3D &tegra264= _uphy0_cbb_fabric }, + { .compatible =3D "nvidia,tegra264-vision-cbb-fabric", .data =3D &tegra26= 4_vision_cbb_fabric }, { /* sentinel */ }, }; MODULE_DEVICE_TABLE(of, tegra234_cbb_dt_ids); --=20 2.25.1