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Fri, 30 May 2025 06:34:24 -0700 From: Sumit Gupta To: , , , , , , , CC: <--to=tbergstrom@nvidia.com>, , Subject: [Patch 3/8] soc: tegra: cbb: make error interrupt enable and status per SoC Date: Fri, 30 May 2025 19:03:31 +0530 Message-ID: <20250530133336.1419971-4-sumitg@nvidia.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250530133336.1419971-1-sumitg@nvidia.com> References: <20250530133336.1419971-1-sumitg@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-NVConfidentiality: public Content-Transfer-Encoding: quoted-printable X-NV-OnPremToCloud: AnonymousSubmission X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS1PEPF00017098:EE_|SA1PR12MB9245:EE_ X-MS-Office365-Filtering-Correlation-Id: 54585be9-eade-4252-7ace-08dd9f7ebd72 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|376014|82310400026|36860700013; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 May 2025 13:34:44.8457 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 54585be9-eade-4252-7ace-08dd9f7ebd72 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: DS1PEPF00017098.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA1PR12MB9245 Content-Type: text/plain; charset="utf-8" Make the error interrupt enable and error status fields as per SoC. Both these fields can change for different SoC's. Moving them to per SoC data helps to set or clear the required bits only for a SoC. Signed-off-by: Sumit Gupta --- drivers/soc/tegra/cbb/tegra234-cbb.c | 22 ++++++++++++++++++++-- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/drivers/soc/tegra/cbb/tegra234-cbb.c b/drivers/soc/tegra/cbb/t= egra234-cbb.c index 5d04ed3b2d50..6116221f0ca6 100644 --- a/drivers/soc/tegra/cbb/tegra234-cbb.c +++ b/drivers/soc/tegra/cbb/tegra234-cbb.c @@ -102,6 +102,8 @@ struct tegra234_cbb_fabric { const int max_errors; const struct tegra234_target_lookup *target_map; const int max_targets; + const u32 err_intr_enbl; + const u32 err_status_clr; }; =20 struct tegra234_cbb { @@ -177,7 +179,7 @@ static void tegra234_cbb_fault_enable(struct tegra_cbb = *cbb) void __iomem *addr; =20 addr =3D priv->regs + priv->fabric->notifier_offset; - writel(0x1ff, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE_0_0); + writel(priv->fabric->err_intr_enbl, addr + FABRIC_EN_CFG_INTERRUPT_ENABLE= _0_0); dsb(sy); } =20 @@ -187,7 +189,7 @@ static void tegra234_cbb_error_clear(struct tegra_cbb *= cbb) =20 writel(0, priv->mon + FABRIC_MN_INITIATOR_ERR_FORCE_0); =20 - writel(0x3f, priv->mon + FABRIC_MN_INITIATOR_ERR_STATUS_0); + writel(priv->fabric->err_status_clr, priv->mon + FABRIC_MN_INITIATOR_ERR_= STATUS_0); dsb(sy); } =20 @@ -709,6 +711,8 @@ static const struct tegra234_cbb_fabric tegra234_aon_fa= bric =3D { .max_targets =3D ARRAY_SIZE(tegra234_aon_target_map), .errors =3D tegra234_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl =3D 0x7, + .err_status_clr =3D 0x3f, .notifier_offset =3D 0x17000, .firewall_base =3D 0x30000, .firewall_ctl =3D 0x8d0, @@ -730,6 +734,8 @@ static const struct tegra234_cbb_fabric tegra234_bpmp_f= abric =3D { .max_targets =3D ARRAY_SIZE(tegra234_bpmp_target_map), .errors =3D tegra234_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl =3D 0xf, + .err_status_clr =3D 0x3f, .notifier_offset =3D 0x19000, .firewall_base =3D 0x30000, .firewall_ctl =3D 0x8f0, @@ -807,6 +813,8 @@ static const struct tegra234_cbb_fabric tegra234_cbb_fa= bric =3D { .max_targets =3D ARRAY_SIZE(tegra234_cbb_target_map), .errors =3D tegra234_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl =3D 0x7f, + .err_status_clr =3D 0x3f, .notifier_offset =3D 0x60000, .off_mask_erd =3D 0x3a004, .firewall_base =3D 0x10000, @@ -830,6 +838,8 @@ static const struct tegra234_cbb_fabric tegra234_dce_fa= bric =3D { .max_targets =3D ARRAY_SIZE(tegra234_common_target_map), .errors =3D tegra234_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl =3D 0xf, + .err_status_clr =3D 0x3f, .notifier_offset =3D 0x19000, .firewall_base =3D 0x30000, .firewall_ctl =3D 0x290, @@ -843,6 +853,8 @@ static const struct tegra234_cbb_fabric tegra234_rce_fa= bric =3D { .max_targets =3D ARRAY_SIZE(tegra234_common_target_map), .errors =3D tegra234_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl =3D 0xf, + .err_status_clr =3D 0x3f, .notifier_offset =3D 0x19000, .firewall_base =3D 0x30000, .firewall_ctl =3D 0x290, @@ -856,6 +868,8 @@ static const struct tegra234_cbb_fabric tegra234_sce_fa= bric =3D { .max_targets =3D ARRAY_SIZE(tegra234_common_target_map), .errors =3D tegra234_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra234_cbb_errors), + .err_intr_enbl =3D 0xf, + .err_status_clr =3D 0x3f, .notifier_offset =3D 0x19000, .firewall_base =3D 0x30000, .firewall_ctl =3D 0x290, @@ -1040,6 +1054,8 @@ static const struct tegra234_cbb_fabric tegra241_cbb_= fabric =3D { .max_targets =3D ARRAY_SIZE(tegra241_cbb_target_map), .errors =3D tegra241_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl =3D 0x7, + .err_status_clr =3D 0x1ff007f, .notifier_offset =3D 0x60000, .off_mask_erd =3D 0x40004, .firewall_base =3D 0x20000, @@ -1065,6 +1081,8 @@ static const struct tegra234_cbb_fabric tegra241_bpmp= _fabric =3D { .max_targets =3D ARRAY_SIZE(tegra241_bpmp_target_map), .errors =3D tegra241_cbb_errors, .max_errors =3D ARRAY_SIZE(tegra241_cbb_errors), + .err_intr_enbl =3D 0xf, + .err_status_clr =3D 0x1ff007f, .notifier_offset =3D 0x19000, .firewall_base =3D 0x30000, .firewall_ctl =3D 0x8f0, --=20 2.25.1