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([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 2/8] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the PCIe Date: Fri, 30 May 2025 14:19:11 +0300 Message-ID: <20250530111917.1495023-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add clocks, resets and power domains for the PCIe IP available on the Renesas RZ/G3S SoC. The clkl1pm clock is required for PCIe link power management (PM) control and should be enabled based on the state of the CLKREQ# pin. Therefore, mark it as a no_pm clock to allow the PCIe driver to manage it during link PM transitions. Signed-off-by: Claudiu Beznea --- Changes in v2: - none drivers/clk/renesas/r9a08g045-cpg.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 4035f3443598..33219164a19a 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -243,6 +243,8 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = =3D { DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0), + DEF_MOD("pci_aclk", R9A08G045_PCI_ACLK, R9A08G045_CLK_M0, 0x608, 0), + DEF_MOD("pci_clk1pm", R9A08G045_PCI_CLKL1PM, R9A08G045_CLK_ZT, 0x608, 1), DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; =20 @@ -282,6 +284,13 @@ static const struct rzg2l_reset r9a08g045_resets[] =3D= { DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0), + DEF_RST(R9A08G045_PCI_ARESETN, 0x908, 0), + DEF_RST(R9A08G045_PCI_RST_B, 0x908, 1), + DEF_RST(R9A08G045_PCI_RST_GP_B, 0x908, 2), + DEF_RST(R9A08G045_PCI_RST_PS_B, 0x908, 3), + DEF_RST(R9A08G045_PCI_RST_RSM_B, 0x908, 4), + DEF_RST(R9A08G045_PCI_RST_CFG_B, 0x908, 5), + DEF_RST(R9A08G045_PCI_RST_LOAD_B, 0x908, 6), DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; =20 @@ -358,6 +367,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08= g045_pm_domains[] =3D { DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), DEF_PD("tsu", R9A08G045_PD_TSU, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0), + DEF_PD("pci", R9A08G045_PD_PCI, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(10)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), @@ -365,6 +376,10 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a0= 8g045_pm_domains[] =3D { DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0), }; =20 +static const unsigned int r9a08g045_no_pm_mod_clks[] =3D { + MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM, +}; + const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { /* Core Clocks */ .core_clks =3D r9a08g045_core_clks, @@ -381,6 +396,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { .num_mod_clks =3D ARRAY_SIZE(r9a08g045_mod_clks), .num_hw_mod_clks =3D R9A08G045_VBAT_BCLK + 1, =20 + /* No PM modules Clocks */ + .no_pm_mod_clks =3D r9a08g045_no_pm_mod_clks, + .num_no_pm_mod_clks =3D ARRAY_SIZE(r9a08g045_no_pm_mod_clks), + /* Resets */ .resets =3D r9a08g045_resets, .num_resets =3D R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ --=20 2.43.0