From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 946E5226D0B for ; Fri, 30 May 2025 11:19:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.54 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603989; cv=none; b=SKyzh1DOQ1L+cqUY44unkWIV9h3FHQDh5HMZiwiFYFjL1QfCcqrZc/dBA5iTCjpNVvc4BGPt6R5L+oLWcom5nx7BIL7KyDRi1lc+bf9o2mT2yQvGnjoGCwFCfklHD+k/b7Fr+XxGnjtWTYSSJk7gcuFCI7PltSDCI4u7auMh9c4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603989; c=relaxed/simple; bh=9gMdTLQyNxVz7af3fV90ZGtGbx4kngU4HShq2JFBz3M=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=duh89a7BIeaxnHrj78xl0oBTKYRtfJ9xeDr7i1BvsAmfr2xlUTJY3Jod3MgoD1I0qCJcD2De9+faMgGCtbX12TyCv0tjHyci3YxjiLGYsdge4qD8jwFPi6iqSwdn+CYcFOlZWxB7T97zljGjQWv4jo0xaYl0nJLyJ8bC1+ZI+bs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=RVjWQ0ps; arc=none smtp.client-ip=209.85.128.54 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="RVjWQ0ps" Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-43ce71582e9so15637615e9.1 for ; Fri, 30 May 2025 04:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603986; x=1749208786; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=8gq3kcPvzJsccZDf4CUDvMYgsYUhJg6mS1FeaP1e3W0=; b=RVjWQ0psJ3ytgrKa2M7/4bsm3/zExuTE5ddGWayoTbRe7S1AmCf8D+g1WlmOB9JjVl 4oA00orTEDAdVw76NqL4pDe37U9ySUWdzHhxd9LWCzeo4IQbmr9h0cTCxLcr85vYWv9D AOnlwBunRT8dMW2QhZkdMPMQrKi3+AIxG8dIek4JfhsP+xpPNSYYPsqIS0xPHLzutw0I SLdq8qlztMW+X5Mhj16Rj4piA5lALEYg7F2A2rAmOxitXFw68TyirDFZV33m1e25f3t5 Ww2vHC/OxsNQn8/NMtdU23OJLlJxP1oa91Q8bpn8HGkxe7mYCVjcojAcNWUz2GnHjHNO qtIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603986; x=1749208786; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=8gq3kcPvzJsccZDf4CUDvMYgsYUhJg6mS1FeaP1e3W0=; b=GCY5LzHpB5SCv7+tL33B3NT3m0xqtxQF3LnFwh8R4sgm9EXxDU3rVJgCy74Un+KX+E o+rTeVa1D2q6bLyTly7X2W9fmuL0H9O2N3Kp4Gud4/RURIYsoOhFPj+IhlIrKDXbXRRR D6ozF8JKh1mmxpHI5CKpJmIixb1W/JQVpkb4CEMLxcTZ50g0zxK0s8qhrNN08Hk5IE00 7A6qpPetuGlHuUMByUr9htkKSMG1HOBdAzYHtHX2TlqPLoqSW2Cmw4IF5RdM9QEa4O9O AFbB+dgKGpIDroyRDs9u0Cc/NdbNfOnS9Zcfgfn/HoVJRPi8q2LxPje4kdKj+09OPKbs /m9w== X-Forwarded-Encrypted: i=1; AJvYcCVRu4OUpFhxxpoHfyGWrkj/8k5aJwFrPszmt8ocQ6ZyGloTULhhnKRWNhrIiuHwb60d4ZfQQNlNpYfVuLM=@vger.kernel.org X-Gm-Message-State: AOJu0Yx/0VM1XSBFhPcjiYeeUSHaM27Wlsv/WQ4mVFT5tJ2Iu4yR/N64 nNuGAmi6ARzf9HO919zP+9AUOHZHEa1L3l9KW0UMRwWE79Xtp+LkAxEy160n64ZGPfw= X-Gm-Gg: ASbGncsH5qRAIDF6OMmU8vvQ5oZCZEc9BVL2CxNMF/9OKFJ9EO1jZoKXdHitxfdMRJ3 99vOoB1sL9IcxfAHCTkn87oiP39PQ4oPFjL6OXyCWBIj2bPglxO4qzwqu48jNGUBWQd4O/dcKIo 9NqOanwE2+a/qv9vuIYQT0JQokiTH3utC07qfJZZrn9koONH4W9PSMhc6fLQG48XBpzerT265J/ Xl2MEnLWrCbvW4AyTNn6C5YpRMME1EbyNERpCLEvv2x9MhxpiOsuVMdE9M4jFFRsEX8odqvHhzI z/00mUFKmWyqxPJF46qNPN2ZMspO8EffdMkSJ47VJ7VT3ulgHvs8urgW4b2nTLCmFpeBFd9voDJ 0acQFNSbR+A5ql56R X-Google-Smtp-Source: AGHT+IHxP8yrQk0faz+i2kakVOIuZar9snW+APNS7fIiJYJ6lw0GyyoJSXv4ka1hHNrf4oEIpPYSzQ== X-Received: by 2002:a05:600c:4f4d:b0:43c:f8fc:f697 with SMTP id 5b1f17b1804b1-450d65338acmr30683445e9.9.1748603985804; Fri, 30 May 2025 04:19:45 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:45 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 1/8] soc: renesas: rz-sysc: Add syscon/regmap support Date: Fri, 30 May 2025 14:19:10 +0300 Message-ID: <20250530111917.1495023-2-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: John Madieu The RZ/G3E system controller has various registers that control or report some properties specific to individual IPs. The regmap is registered as a syscon device to allow these IP drivers to access the registers through the regmap API. As other RZ SoCs might have custom read/write callbacks or max-offsets, add register a custom regmap configuration. [claudiu.beznea: - s/rzg3e_sysc_regmap/rzv2h_sysc_regmap in RZ/V2H sysc file - do not check the match->data validity in rz_sysc_probe() as it is always valid - register the regmap if data->regmap_cfg is valid] Signed-off-by: John Madieu Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - picked the latest version from John after he addressed the review comments received at [1]; - I adjusted as specified in the SoB area [1] https://lore.kernel.org/all/20250330214945.185725-2-john.madieu.xa@bp.r= enesas.com/ drivers/soc/renesas/Kconfig | 1 + drivers/soc/renesas/r9a08g045-sysc.c | 10 ++++++++++ drivers/soc/renesas/r9a09g047-sys.c | 10 ++++++++++ drivers/soc/renesas/r9a09g057-sys.c | 10 ++++++++++ drivers/soc/renesas/rz-sysc.c | 17 ++++++++++++++++- drivers/soc/renesas/rz-sysc.h | 3 +++ 6 files changed, 50 insertions(+), 1 deletion(-) diff --git a/drivers/soc/renesas/Kconfig b/drivers/soc/renesas/Kconfig index fbc3b69d21a7..f3b7546092d6 100644 --- a/drivers/soc/renesas/Kconfig +++ b/drivers/soc/renesas/Kconfig @@ -437,6 +437,7 @@ config RST_RCAR =20 config SYSC_RZ bool "System controller for RZ SoCs" if COMPILE_TEST + select MFD_SYSCON =20 config SYSC_R9A08G045 bool "Renesas RZ/G3S System controller support" if COMPILE_TEST diff --git a/drivers/soc/renesas/r9a08g045-sysc.c b/drivers/soc/renesas/r9a= 08g045-sysc.c index f4db1431e036..0ef6df77e25f 100644 --- a/drivers/soc/renesas/r9a08g045-sysc.c +++ b/drivers/soc/renesas/r9a08g045-sysc.c @@ -18,6 +18,16 @@ static const struct rz_sysc_soc_id_init_data rzg3s_sysc_= soc_id_init_data __initc .specific_id_mask =3D GENMASK(27, 0), }; =20 +static const struct regmap_config rzg3s_sysc_regmap __initconst =3D { + .name =3D "rzg3s_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0xe20, +}; + const struct rz_sysc_init_data rzg3s_sysc_init_data __initconst =3D { .soc_id_init_data =3D &rzg3s_sysc_soc_id_init_data, + .regmap_cfg =3D &rzg3s_sysc_regmap, }; diff --git a/drivers/soc/renesas/r9a09g047-sys.c b/drivers/soc/renesas/r9a0= 9g047-sys.c index cd2eb7782cfe..a3acf6dd2867 100644 --- a/drivers/soc/renesas/r9a09g047-sys.c +++ b/drivers/soc/renesas/r9a09g047-sys.c @@ -62,6 +62,16 @@ static const struct rz_sysc_soc_id_init_data rzg3e_sys_s= oc_id_init_data __initco .print_id =3D rzg3e_sys_print_id, }; =20 +static const struct regmap_config rzg3e_sysc_regmap __initconst =3D { + .name =3D "rzg3e_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x170c, +}; + const struct rz_sysc_init_data rzg3e_sys_init_data =3D { .soc_id_init_data =3D &rzg3e_sys_soc_id_init_data, + .regmap_cfg =3D &rzg3e_sysc_regmap, }; diff --git a/drivers/soc/renesas/r9a09g057-sys.c b/drivers/soc/renesas/r9a0= 9g057-sys.c index 4c21cc29edbc..c26821636dce 100644 --- a/drivers/soc/renesas/r9a09g057-sys.c +++ b/drivers/soc/renesas/r9a09g057-sys.c @@ -62,6 +62,16 @@ static const struct rz_sysc_soc_id_init_data rzv2h_sys_s= oc_id_init_data __initco .print_id =3D rzv2h_sys_print_id, }; =20 +static const struct regmap_config rzv2h_sysc_regmap __initconst =3D { + .name =3D "rzv2h_sysc_regs", + .reg_bits =3D 32, + .reg_stride =3D 4, + .val_bits =3D 32, + .fast_io =3D true, + .max_register =3D 0x170c, +}; + const struct rz_sysc_init_data rzv2h_sys_init_data =3D { .soc_id_init_data =3D &rzv2h_sys_soc_id_init_data, + .regmap_cfg =3D &rzv2h_sysc_regmap, }; diff --git a/drivers/soc/renesas/rz-sysc.c b/drivers/soc/renesas/rz-sysc.c index ffa65fb4dade..70556a2f55e6 100644 --- a/drivers/soc/renesas/rz-sysc.c +++ b/drivers/soc/renesas/rz-sysc.c @@ -6,8 +6,10 @@ */ =20 #include +#include #include #include +#include #include =20 #include "rz-sysc.h" @@ -100,14 +102,19 @@ MODULE_DEVICE_TABLE(of, rz_sysc_match); =20 static int rz_sysc_probe(struct platform_device *pdev) { + const struct rz_sysc_init_data *data; const struct of_device_id *match; struct device *dev =3D &pdev->dev; + struct regmap *regmap; struct rz_sysc *sysc; + int ret; =20 match =3D of_match_node(rz_sysc_match, dev->of_node); if (!match) return -ENODEV; =20 + data =3D match->data; + sysc =3D devm_kzalloc(dev, sizeof(*sysc), GFP_KERNEL); if (!sysc) return -ENOMEM; @@ -117,7 +124,15 @@ static int rz_sysc_probe(struct platform_device *pdev) return PTR_ERR(sysc->base); =20 sysc->dev =3D dev; - return rz_sysc_soc_init(sysc, match); + ret =3D rz_sysc_soc_init(sysc, match); + if (ret || !data->regmap_cfg) + return ret; + + regmap =3D devm_regmap_init_mmio(dev, sysc->base, data->regmap_cfg); + if (IS_ERR(regmap)) + return PTR_ERR(regmap); + + return of_syscon_register_regmap(dev->of_node, regmap); } =20 static struct platform_driver rz_sysc_driver =3D { diff --git a/drivers/soc/renesas/rz-sysc.h b/drivers/soc/renesas/rz-sysc.h index 56bc047a1bff..447008140634 100644 --- a/drivers/soc/renesas/rz-sysc.h +++ b/drivers/soc/renesas/rz-sysc.h @@ -9,6 +9,7 @@ #define __SOC_RENESAS_RZ_SYSC_H__ =20 #include +#include #include #include =20 @@ -34,9 +35,11 @@ struct rz_sysc_soc_id_init_data { /** * struct rz_sysc_init_data - RZ SYSC initialization data * @soc_id_init_data: RZ SYSC SoC ID initialization data + * @regmap_cfg: SoC-specific regmap config */ struct rz_sysc_init_data { const struct rz_sysc_soc_id_init_data *soc_id_init_data; + const struct regmap_config *regmap_cfg; }; =20 extern const struct rz_sysc_init_data rzg3e_sys_init_data; --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wr1-f42.google.com (mail-wr1-f42.google.com [209.85.221.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D776122A810 for ; Fri, 30 May 2025 11:19:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603992; cv=none; b=AFT4Otx0O3jDNqwIwcaPNC1b/vy3XgT7fwnmeIVE7yuDDjOfTtCGJuIzGEbzpscTQ6rv3rvJzQDOZ3AyroS5qPhEN827d8J91fqrlxDzOfNdMujrVY7JdZRKg5DZ+jyGDbT8xXwf9bL3jFtRGy2UCwjtKsqZ20eOk8b6QLCliRw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603992; c=relaxed/simple; bh=Ah7Z+DsWBX06w3bVvtMO0K5BDNvk6TjZ7R8qbml2dpM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=tGwBnibUqNXDNoFNEgVHBxLxdbbLRT5G8YTE2WF+kCIrZsBq+AFT4qqm8j9HKR02+X4m7A1DG4bk1wyxRtH2P4rOMfKRLnPngLMxOXCRKK1jQrYH5PSA7Qr38AWY6M7a4h6MNadJ5dJPTpzPzwkA7K53ThTn/ZybcMZuR10pEfY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=DjpVjCES; arc=none smtp.client-ip=209.85.221.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="DjpVjCES" Received: by mail-wr1-f42.google.com with SMTP id ffacd0b85a97d-3a375888297so1140505f8f.1 for ; Fri, 30 May 2025 04:19:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603988; x=1749208788; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=FJ/+G+AC3goiMLAvY8TZZVygk03XZkoKHyxtdwV9Bko=; b=DjpVjCESWVc0Bd1YTeQkSuYLD6nXwsQyhHj0r20Nam4ljGqxhIFc/xaH3O4lnlEgTI eWLS7i+0uGEnmpQFva5kbbmlnGXt+WB4ktVk3s/Xq190MupoyXKkWBQNposG8m6xfId+ ggHGPu1iK1SxLp5KvSCcjHhpLoR6C340WgEsek4oxWJTnUP5lP8IeNQ7EHsfx8w81x2a 3eB+aGjk6rD/zOQzk9Wpse1wu5lxlwyBAfC5NJ1RdQyGp2NK+oyZ7jeEfY6BpGR4CXWb eXgtuYxaAai4JHU0Zn4H2LjHBx55aZelEZF+i1nXotaHW9TvOZb+69UKSWf3OH32JTqQ aJNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603988; x=1749208788; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=FJ/+G+AC3goiMLAvY8TZZVygk03XZkoKHyxtdwV9Bko=; b=ajweg1RQBy83arwZpJF5TyBCCmMKtpAm0LLchvCFxSonJhRvoODDqgqqoCvoMLS2vo UuZ0xr0L0afs6b7mFHfWcV25OGi88hiiPC+Y7hPG1ozj2+JUgfkkC3aEUj3z/LeCfRBa WzcVEbDwQ9Ak7Wb1MxrKG1dVH1EzC1BPWWOvnB/nwPNdBuZm15cU7i8D7arLNEyGF4uY HXZbvXPM2Fu70E0NNDya0Sb31c7qZ5BLbxpj78ktWsnDkUvntt0nkgR6sqjV2CLremZG ekSfdYoveKObqybvHlvAcvP4l1LooOuIPbdL/EkT9uYaDiS8vpeQO1IEkSO6ugDFNvWS M0ag== X-Forwarded-Encrypted: i=1; AJvYcCUvQG9CX4mkcp+/4OzbgUIy6XoEezMNNvw1zpPH1lYWLskkBLUVwijgxMDXT/4cjPlYq3Gt31AXkJBRfGY=@vger.kernel.org X-Gm-Message-State: AOJu0YyLNkac+tBvv16u2n0Y6mRyQlnWDFrY9zBDQbqPhiLJE30xekhE fTvEkAtPJxGgUxgmXQ6hYApFpaO53EU5TUaTAOIFUwlNqmAHKzuMAPjRHF965y9K4zU= X-Gm-Gg: ASbGncsN90XHkUnwU/adJUfFhfrm5m5HWdshI2XYQtABDqKf4zNiIeAANOvh2kUJyz/ vw345c9JG8kM/+VKbZKGB/SKSMVr5nME0+89W7UnEIige3SIsGGBwh9phnRjYB4H9u+VDlSGt5r gHX6o7hxUPJVMt6OYwcFdRsWvzhnphPL7S9oa2eYVjUt1iAx+0S3xnv56n6g1YXbGlOqwJrRQsA KHtSRiOaRnRvo1cDcm2IMTgsqSLRIaqsjxDUrAqF+2HoFPtPuZuoK6kQpmPylMFvgeJFiG37W4Y IYBva4mz8lh6TKMwP0Zt0Li8/8h9TNvh9AxXvjZ2DF8eG7g1JMjKnwt0rv00rD6eBoN1ezRM6P0 s1IOWnA== X-Google-Smtp-Source: AGHT+IHmpme3ASdZjXhpIgvfrfPC8BzS2kR2b9/W6J51HT2LhURSK9ofZ+2PJlI42CY77vECWpRGwg== X-Received: by 2002:a05:6000:4029:b0:3a4:da0e:517a with SMTP id ffacd0b85a97d-3a4eedb8a81mr6645254f8f.23.1748603987781; Fri, 30 May 2025 04:19:47 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:47 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 2/8] clk: renesas: r9a08g045: Add clocks, resets and power domain support for the PCIe Date: Fri, 30 May 2025 14:19:11 +0300 Message-ID: <20250530111917.1495023-3-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Add clocks, resets and power domains for the PCIe IP available on the Renesas RZ/G3S SoC. The clkl1pm clock is required for PCIe link power management (PM) control and should be enabled based on the state of the CLKREQ# pin. Therefore, mark it as a no_pm clock to allow the PCIe driver to manage it during link PM transitions. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - none drivers/clk/renesas/r9a08g045-cpg.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/clk/renesas/r9a08g045-cpg.c b/drivers/clk/renesas/r9a0= 8g045-cpg.c index 4035f3443598..33219164a19a 100644 --- a/drivers/clk/renesas/r9a08g045-cpg.c +++ b/drivers/clk/renesas/r9a08g045-cpg.c @@ -243,6 +243,8 @@ static const struct rzg2l_mod_clk r9a08g045_mod_clks[] = =3D { DEF_MOD("adc_adclk", R9A08G045_ADC_ADCLK, R9A08G045_CLK_TSU, 0x5a8, 0), DEF_MOD("adc_pclk", R9A08G045_ADC_PCLK, R9A08G045_CLK_TSU, 0x5a8, 1), DEF_MOD("tsu_pclk", R9A08G045_TSU_PCLK, R9A08G045_CLK_TSU, 0x5ac, 0), + DEF_MOD("pci_aclk", R9A08G045_PCI_ACLK, R9A08G045_CLK_M0, 0x608, 0), + DEF_MOD("pci_clk1pm", R9A08G045_PCI_CLKL1PM, R9A08G045_CLK_ZT, 0x608, 1), DEF_MOD("vbat_bclk", R9A08G045_VBAT_BCLK, R9A08G045_OSCCLK, 0x614, 0), }; =20 @@ -282,6 +284,13 @@ static const struct rzg2l_reset r9a08g045_resets[] =3D= { DEF_RST(R9A08G045_ADC_PRESETN, 0x8a8, 0), DEF_RST(R9A08G045_ADC_ADRST_N, 0x8a8, 1), DEF_RST(R9A08G045_TSU_PRESETN, 0x8ac, 0), + DEF_RST(R9A08G045_PCI_ARESETN, 0x908, 0), + DEF_RST(R9A08G045_PCI_RST_B, 0x908, 1), + DEF_RST(R9A08G045_PCI_RST_GP_B, 0x908, 2), + DEF_RST(R9A08G045_PCI_RST_PS_B, 0x908, 3), + DEF_RST(R9A08G045_PCI_RST_RSM_B, 0x908, 4), + DEF_RST(R9A08G045_PCI_RST_CFG_B, 0x908, 5), + DEF_RST(R9A08G045_PCI_RST_LOAD_B, 0x908, 6), DEF_RST(R9A08G045_VBAT_BRESETN, 0x914, 0), }; =20 @@ -358,6 +367,8 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a08= g045_pm_domains[] =3D { DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(14)), 0), DEF_PD("tsu", R9A08G045_PD_TSU, DEF_REG_CONF(CPG_BUS_MCPU2_MSTOP, BIT(15)), 0), + DEF_PD("pci", R9A08G045_PD_PCI, + DEF_REG_CONF(CPG_BUS_PERI_COM_MSTOP, BIT(10)), 0), DEF_PD("vbat", R9A08G045_PD_VBAT, DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(8)), GENPD_FLAG_ALWAYS_ON), @@ -365,6 +376,10 @@ static const struct rzg2l_cpg_pm_domain_init_data r9a0= 8g045_pm_domains[] =3D { DEF_REG_CONF(CPG_BUS_MCPU3_MSTOP, BIT(7)), 0), }; =20 +static const unsigned int r9a08g045_no_pm_mod_clks[] =3D { + MOD_CLK_BASE + R9A08G045_PCI_CLKL1PM, +}; + const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { /* Core Clocks */ .core_clks =3D r9a08g045_core_clks, @@ -381,6 +396,10 @@ const struct rzg2l_cpg_info r9a08g045_cpg_info =3D { .num_mod_clks =3D ARRAY_SIZE(r9a08g045_mod_clks), .num_hw_mod_clks =3D R9A08G045_VBAT_BCLK + 1, =20 + /* No PM modules Clocks */ + .no_pm_mod_clks =3D r9a08g045_no_pm_mod_clks, + .num_no_pm_mod_clks =3D ARRAY_SIZE(r9a08g045_no_pm_mod_clks), + /* Resets */ .resets =3D r9a08g045_resets, .num_resets =3D R9A08G045_VBAT_BRESETN + 1, /* Last reset ID + 1 */ --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 767E322B584 for ; Fri, 30 May 2025 11:19:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603993; cv=none; b=FBhWzSGGruQLyIZlmRSDG77jdXJC8FtBAfKBoDuRvld0wa1o8V2wVO6nFSYHgxBcTJTAq5pGeWvgwe/W4gRzNSDs0WfS3AhRR5SH0vYHHoBUA+XXhHzJYNKdlqDD2n1pMMnH4JUWLxyWu2bpmWi5yrUlg/88nHBVi6yFMdx/dNY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603993; c=relaxed/simple; bh=ns2/6HM9DUUKQWgTZTHH3dZVC94HZ2UxMpbY4SNaI0s=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=T6sH6E0suWWVfAGwwq9PjjxjL/89cjvzhvyol754n5zSMXF6xvgVcyqepY18O/jCJj85URWiqa/MzlG0MZLuCFsiBF5nfEZtJCd/XBq60ZXACScvUBbYwiK/f2pwtpJXJhUAnPz+WPmxvbLwz/kAOGy7jPzoks7DtVWdJbxxsL8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=RIjmqaub; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="RIjmqaub" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-442eb5d143eso18354885e9.0 for ; Fri, 30 May 2025 04:19:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603990; x=1749208790; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=NRhFPy/WSaCOJP9APyJMZ4CnadrynNoxtIF0zSIL6mg=; b=RIjmqaubfatb8vLWLsdi2NNjp+byq1n33u8GrI4qKZ7Dvp9M0MsCfcqKkpD+tI6ONY X4ChhIIMFoySXGSDn1UvTT0FpmJlDlMuKHKffWyuzJHf7aYvKORTnA4GfmKqEirveSe6 kKKcmDhRigLFJbj+Dbr1CIyLDXO6ABYPL1zDTt69JVeagD0CQswFvCMSjOps3atTjflf c5An3JzN4pjLRQs/V/TT/ODFcj9K7BHAo59Zss6P04T/1lROhvZtswMeG63NNcoVbvw3 7Xn3iR+l6v3x7ehVu2B3/vE9nYCxsBbJcwQMorUjgRKmnVfU7eL0/0BKVGeVrc7aTcjz 7ZVw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603990; x=1749208790; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=NRhFPy/WSaCOJP9APyJMZ4CnadrynNoxtIF0zSIL6mg=; b=mlrpVY+Uw5qev2j0YFEH8ORxJslzmjrGWG4cg1nm77Sw98Jen4jc6G5BR17y2XNQcY jHVcoF1TJyUjPw8vrGe1Yq95CdPkv1L/2QuaeQaG/PggaNCIRwGyOw00kEzleeA116Tw 1r8r6UPVDvyy7YoNOqPwxK+sNNQOIQ20ki9kF7ZWmSpBXkfbegV2xbvYG27rwdp3XtWZ 1e7T4nne0/ivp4b7B59m7ZwyOEe9hOnYJKl+wn22XE2pS7U7xq0AxhIV2sxP0w3AOKjf w2yOHWekZ5GhMut9/1+wrKPmmRgD5EMVk+CxM0DDAmVPTkzzETsMRfmzrTALVbtQxcWT i7xA== X-Forwarded-Encrypted: i=1; AJvYcCU37rNyFce3Itv9VDqz0DTNWI0OXahR2XA8CnSezVP/uWKTc7BD+0hTo2CxHMwdiVhmQ03vGdXTppiYlcQ=@vger.kernel.org X-Gm-Message-State: AOJu0Yxh/msnapraxL4Mb1NQkv31gGb2zDnJCJee2xA3EZxH3RD+gfJ2 lv8QaCsquDJEb9Am4yg2RnESBQUcA5oBJm5Q6CeggMQbIJGwr9PedFlOgrSzYivbbOc= X-Gm-Gg: ASbGnctFZAM1ijuiwIc9+dWoLWLb4/47DJHHl7Vmr+Zg5ct+2lQesegLWa0Sk+MZXIl 8gG578iNOjQBrebaLBd8WHYX8BCiAsK9kb/dN7ivdpxHJzIrbH8SfNPdL5oKB8SNmz85zRHitK4 ecZf5cFvAJrsf3RXyXl2MWeQdezNfOLV5V9jMUkjO2NcZF9ILsIBB17J7aYhWylLOwfOdPJgNWk sO2He0hJdCAZTmVYbwJSezT8es38TvWQ5kzpgT9ozgE5BqZNv+uZ/uIjWBmV4Iuc4PESXW3pYA6 /lgt7aPE6XO+kEn17MXIA07Jx7PsS0OLf8X7rNfWDhAi4hOatgRn7S+Sg0tbLIeu2+d2aROKQhc K8JXmTQ== X-Google-Smtp-Source: AGHT+IFM8W21a8CSEqnfheEWvs2NWYLaDxAcaJALbnProLcKAOdd/gUtEAjS+UJvMRJJ0qPulokYPA== X-Received: by 2002:a05:600c:1910:b0:441:b698:3431 with SMTP id 5b1f17b1804b1-450d6590912mr23046025e9.28.1748603989725; Fri, 30 May 2025 04:19:49 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:49 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 3/8] dt-bindings: PCI: renesas,r9a08g045s33-pcie: Add documentation for the PCIe IP on Renesas RZ/G3S Date: Fri, 30 May 2025 14:19:12 +0300 Message-ID: <20250530111917.1495023-4-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The PCIe IP available on the Renesas RZ/G3S complies with the PCI Express Base Specification 4.0. It is designed for root complex applications and features a single-lane (x1) implementation. Add documentation for it. Signed-off-by: Claudiu Beznea Reviewed-by: Rob Herring (Arm) Tested-by: Wolfram Sang --- Changes in v2: - update the interrupt names by dropping "int" and "rc" string; due to this the patch description was adjusted - added "interrupt-controller" and made it mandatory - s/clkl1pm/pm/g - dropped the legacy-interrupt-controller node; with this the gic interrupt controller node was dropped as well as it is not needed anymore - updated interrupt-map in example and added interrupt-controller - added clock-names as required property as the pm clock is not handled though PM domains; this will allow the driver to have the option to request the pm clock by its name when implementation will be adjusted to used the pm clock - adjusted the size of dma-ranges to reflect the usage on SMARC module board - moved "renesas,sysc" at the end of the node in example to align with dts coding style .../pci/renesas,r9a08g045s33-pcie.yaml | 202 ++++++++++++++++++ 1 file changed, 202 insertions(+) create mode 100644 Documentation/devicetree/bindings/pci/renesas,r9a08g045= s33-pcie.yaml diff --git a/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pci= e.yaml b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.ya= ml new file mode 100644 index 000000000000..8ba30c084d1b --- /dev/null +++ b/Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml @@ -0,0 +1,202 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pci/renesas,r9a08g045s33-pcie.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Renesas RZ/G3S PCIe host controller + +maintainers: + - Claudiu Beznea + +description: + Renesas RZ/G3S PCIe host controller complies with PCIe Base Specification + 4.0 and supports up to 5 GT/s (Gen2). + +properties: + compatible: + const: renesas,r9a08g045s33-pcie # RZ/G3S + + reg: + maxItems: 1 + + interrupts: + items: + - description: System error interrupt + - description: System error on correctable error interrupt + - description: System error on non-fatal error interrupt + - description: System error on fatal error interrupt + - description: AXI error interrupt + - description: INTA interrupt + - description: INTB interrupt + - description: INTC interrupt + - description: INTD interrupt + - description: MSI interrupt + - description: Link bandwidth interrupt + - description: PME interrupt + - description: DMA interrupt + - description: PCIe event interrupt + - description: Message interrupt + - description: All interrupts + + interrupt-names: + items: + - description: serr + - description: ser_cor + - description: serr_nonfatal + - description: serr_fatal + - description: axi_err + - description: inta + - description: intb + - description: intc + - description: intd + - description: msi + - description: link_bandwidth + - description: pm_pme + - description: dma + - description: pcie_evt + - description: msg + - description: all + + interrupt-controller: true + + clocks: + items: + - description: System clock + - description: PM control clock + + clock-names: + items: + - description: aclk + - description: pm + + resets: + items: + - description: AXI2PCIe Bridge reset + - description: Data link layer/transaction layer reset + - description: Transaction layer (ACLK domain) reset + - description: Transaction layer (PCLK domain) reset + - description: Physical layer reset + - description: Configuration register reset + - description: Configuration register reset + + reset-names: + items: + - description: aresetn + - description: rst_b + - description: rst_gp_b + - description: rst_ps_b + - description: rst_rsm_b + - description: rst_cfg_b + - description: rst_load_b + + power-domains: + maxItems: 1 + + dma-ranges: + description: + A single range for the inbound memory region. + maxItems: 1 + + renesas,sysc: + description: System controller phandle + $ref: /schemas/types.yaml#/definitions/phandle + + vendor-id: + const: 0x1912 + + device-id: + const: 0x0033 + +required: + - compatible + - reg + - clocks + - clock-names + - resets + - reset-names + - interrupts + - interrupt-names + - interrupt-map + - interrupt-map-mask + - interrupt-controller + - power-domains + - "#address-cells" + - "#size-cells" + - "#interrupt-cells" + - renesas,sysc + - vendor-id + - device-id + +allOf: + - $ref: /schemas/pci/pci-host-bridge.yaml# + +unevaluatedProperties: false + +examples: + - | + #include + #include + + bus { + #address-cells =3D <2>; + #size-cells =3D <2>; + + pcie@11e40000 { + compatible =3D "renesas,r9a08g045s33-pcie"; + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>; + dma-ranges =3D <0x42000000 0 0x48000000 0 0x48000000 0 0x38000= 000>; + bus-range =3D <0x0 0xff>; + clocks =3D <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names =3D "aclk", "pm"; + resets =3D <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names =3D "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie 0 0 0 0>, /* INT A */ + <0 0 0 2 &pcie 0 0 0 1>, /* INT B */ + <0 0 0 3 &pcie 0 0 0 2>, /* INT C */ + <0 0 0 4 &pcie 0 0 0 3>; /* INT D */ + device_type =3D "pci"; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + power-domains =3D <&cpg>; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; + renesas,sysc =3D <&sysc>; + }; + }; + +... --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CBEE522CBC0 for ; Fri, 30 May 2025 11:19:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603998; cv=none; b=PnvJ1ikyVa6TCqtKdRFqDfcFrKjgV7Xt4hz53dRxUg9uXf98U1WhCmAP3uT/in307EjU4RZAunw4bHJc6cDUS0lHpVxp87e2FB99obp9sB/AEqZwORO4ZMBqCKikZMkE1kz2jT8kcW4d8vlAMep2kPqQt2FtQEdw/xazPBj9o4U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603998; c=relaxed/simple; bh=dRgX3vvaILA91cxiG0rL/mZk9JQxIfMJKNR+jebWm9g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Ks/YMdp4aRm1Ni4GtVrSaepMSfKbUYRX7ip4qqeCLmBJcmmWsTdxV0hvkKtFiGU4M+4V+wcGRrbCBtVMCKrMRvyilCiTLyeuB42/LZs8qDXz135vQ93htUF8W21sTTy+WiUuB3Zfmv5S2B2D4fMeXs2TLYIUr9VT18HokJJwfWA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=DqHz/13h; arc=none smtp.client-ip=209.85.128.51 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="DqHz/13h" Received: by mail-wm1-f51.google.com with SMTP id 5b1f17b1804b1-43cfba466b2so23097285e9.3 for ; Fri, 30 May 2025 04:19:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603992; x=1749208792; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=3DwcPsgDcC+Gp34UUD6AU1MlyT327vPu9foVQDEPeuU=; b=DqHz/13hPmKUwYByduC5xU5AFbEbvbEqq3MRXqN6rLhgjuKsOv+pNxdhxcN1htU/VK JvRWzyyry/zf0WGbEzTvsTRzOwOn3IW4pcrhI7X1SuhC95jkKWgxGoj9cdV7sigkIhZd T3YHqOAkWopxRnbT4/uL+82rkioy1K3rm6mofKMLYlhtpUfR9LpcvpJ7ItJCGan7oNB+ IDLb7e9KQ2ojNRM2zo0wUiOxu2Yc7lEDQVSgLgs5iC8cYUrw7DssS2BrtnJ29F1KFQgU 9Yd61ehgaVoyaRrFffeiTMAzPYKi5SHYoVXkf1FAsb56BCHaj56U2MxxrkkDetEvJwM4 ulaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603992; x=1749208792; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=3DwcPsgDcC+Gp34UUD6AU1MlyT327vPu9foVQDEPeuU=; b=QD3pqErTgqOy4ZTH3Rv2wRKe2/VS1V3xon3I+FCr5l6ghJAIGa1ZNrJHWkBSL97J/w TED9axMgI09YNQSvABoeWaZ1rERwSXfGb4nd0roP9ZxTGJZLL/5PGxbMidFf8LJYsdNO ZCFzvXKpBDkckeDTiwxVzVdXVMa7qIzMZbh++Uad3V2vFtSaIv2Dh5rnuiDzitRT92ti DFMM+JxY2r/RUhzhatP0dTDiC/1zm6s8puA2Qo6QXUDn9KkGyl9qhc7vZzgbqVceMcLm ssFCpSsXZV3EQiyLDfOAP/B6DPYqxx4zqNBq5I2hThTVj0GWIALayQz+HF7n28FZOSmn 66FQ== X-Forwarded-Encrypted: i=1; AJvYcCU8kOjnaBomK1V8vHOIcW7+tYJ+FehU1Y8POB5E3qRAldQmylJWecxA93uHOPw61lRR8BInD2RRqxlOZsM=@vger.kernel.org X-Gm-Message-State: AOJu0Yzk9QR19Z1G9JFtCcg0xQ3h41MsH8hKFIn2449GlkC9XWpfFGMm jX6zt04iTC/i4VlB1fnNWkL4ZD9eMHBB2OK+L2Lw7RAQXkyAbQu4VO59xl3QfLBs7cY= X-Gm-Gg: ASbGncswH2b7f1gvOlhHgy/WIBfwZDajHkenx8ba+OcTZDRJMNfNtuVlFIaKlh9Xaqx H4ldg2EKJ+oIup+edBO8d8QWohGQ4dHt7Lu/XvHjS19F+k487ErmMjkm2zJhhz2W2MMAIuLNlud udF/RWd3JAjam5SB6bzZjh00AYRn4FFUiUbstHt0Svlk2DHIdmcfA672vQYOwr/21W6zW8uy/H7 GExtopEl2A7p77a94dORbzJLB0dzv+4qj1xTaKf2p/G2KDTvTqVNPTFxvrzcKywsjfhc6eHpKpS wBa+rVnKoU03gMaC2uZtnOy8OxXgJhMS883ppa6uAblvOD/iz+NVVpP4c4AbOaV7VSTeWBw4tQB DIPIV7BSWXHvGt5b3 X-Google-Smtp-Source: AGHT+IEcbfCVPFMD+tBFL71IyuZANe3L+xDouURQO9QqOroiTpxVbKJqAa9JkWBxvaDPezxD0AkbHg== X-Received: by 2002:a05:600c:8206:b0:441:d437:e3b8 with SMTP id 5b1f17b1804b1-450d8867115mr15097355e9.23.1748603991778; Fri, 30 May 2025 04:19:51 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:51 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 4/8] PCI: rzg3s-host: Add Initial PCIe Host Driver for Renesas RZ/G3S SoC Date: Fri, 30 May 2025 14:19:13 +0300 Message-ID: <20250530111917.1495023-5-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The Renesas RZ/G3S features a PCIe IP that complies with the PCI Express Base Specification 4.0 and supports speeds of up to 5 GT/s. It functions only as a root complex, with a single-lane (x1) configuration. The controller includes Type 1 configuration registers, as well as IP specific registers (called AXI registers) required for various adjustments. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - dropped the references to other RZ SoCs from patch description - dropped the dot at the end of single line comments that are not a sentence - as a result of v2 rework removed unused macros and definitions (e.g. RZG3S_PCI_REQISS_TR_TP1_RD, RZG3S_PCI_REQISS_TR_TP1_WR, enum rzg3s_pcie_cfg_access_type) - dropped driver specific defines that are for generic PCI register offsets and used the generic ones - updated the value of RZG3S_PCI_MSI_INT_NR as on RZ/G3S there are no more than 32 MSIs (v1 value was due to mistake in the HW manual) - added timeout macros to be used by read_poll_timeout() specific functions - re-worked the reset handling part by using reset subsystem specific functions only; with this the struct rzg3s_pcie_soc_data was added; reference to PHY initialization function was added to this structure as well - dropped devres_group_id as the issue it tried to address will now be fixed in platform bus code (v2 posted [2]) - use 80 columns alignment - updated function name in the idea of using names similar to what is used in other drivers - added rzg3s_pcie_root_ops and rzg3s_pcie_child_ops and populate bridge->ops, bridge->child_ops with it; from probe: + bridge->ops =3D &rzg3s_pcie_root_ops; + bridge->child_ops =3D &rzg3s_pcie_child_ops; - print a warning for 32 bit accesses (based on the value of bus->unsafe_warn as done in the common code) - dropped dev_dbg() in read/write functions - added HW manual revision identifier in comments that points to the statements from manual - reworked the rzg3s_pcie_intx_setup() as the legacy interrupt DT node is not used anymore - in rzg3s_pcie_config_init() do not hardcode anymore the primary bus, secondary bus, subordinate bus but get this information from device tree and update HW registers accordingly - dropped rzg3s_pcie_remove() and added rzg3s_pcie_host_remove_action() to be used as a devm action or reset function - s/rzg3s_pcie_suspend/rzg3s_pcie_suspend_noirq, s/rzg3s_pcie_resume/rzg3s_pcie_resume_noirq - dropped DEFINE_NOIRQ_DEV_PM_OPS() - updated driver name (rzg3s-pcie-host) to reflect it is for RZ/G3S=20 [2] https://lore.kernel.org/all/20250526122054.65532-2-claudiu.beznea.uj@bp= .renesas.com MAINTAINERS | 8 + drivers/pci/controller/Kconfig | 7 + drivers/pci/controller/Makefile | 1 + drivers/pci/controller/pcie-rzg3s-host.c | 1686 ++++++++++++++++++++++ 4 files changed, 1702 insertions(+) create mode 100644 drivers/pci/controller/pcie-rzg3s-host.c diff --git a/MAINTAINERS b/MAINTAINERS index 0d59a5910e63..3076065955f0 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -19286,6 +19286,14 @@ S: Maintained F: drivers/pci/controller/dwc/pcie-qcom-common.c F: drivers/pci/controller/dwc/pcie-qcom.c =20 +PCIE DRIVER FOR RENESAS RZ/G3S SERIES +M: Claudiu Beznea +L: linux-pci@vger.kernel.org +L: linux-renesas-soc@vger.kernel.org +S: Supported +F: Documentation/devicetree/bindings/pci/renesas,r9a08g045s33-pcie.yaml +F: drivers/pci/controller/pcie-rzg3s-host.c + PCIE DRIVER FOR ROCKCHIP M: Shawn Lin L: linux-pci@vger.kernel.org diff --git a/drivers/pci/controller/Kconfig b/drivers/pci/controller/Kconfig index 886f6f43a895..76fa5f330105 100644 --- a/drivers/pci/controller/Kconfig +++ b/drivers/pci/controller/Kconfig @@ -258,6 +258,13 @@ config PCI_RCAR_GEN2 There are 3 internal PCI controllers available with a single built-in EHCI/OHCI host controller present on each one. =20 +config PCIE_RENESAS_RZG3S_HOST + tristate "Renesas RZ/G3S PCIe host controller" + depends on ARCH_RENESAS || COMPILE_TEST + select MFD_SYSCON + help + Say Y here if you want PCIe host controller support on Renesas RZ/G3S S= oC. + config PCIE_ROCKCHIP bool depends on PCI diff --git a/drivers/pci/controller/Makefile b/drivers/pci/controller/Makef= ile index 038ccbd9e3ba..229929a945c2 100644 --- a/drivers/pci/controller/Makefile +++ b/drivers/pci/controller/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_PCI_TEGRA) +=3D pci-tegra.o obj-$(CONFIG_PCI_RCAR_GEN2) +=3D pci-rcar-gen2.o obj-$(CONFIG_PCIE_RCAR_HOST) +=3D pcie-rcar.o pcie-rcar-host.o obj-$(CONFIG_PCIE_RCAR_EP) +=3D pcie-rcar.o pcie-rcar-ep.o +obj-$(CONFIG_PCIE_RENESAS_RZG3S_HOST) +=3D pcie-rzg3s-host.o obj-$(CONFIG_PCI_HOST_COMMON) +=3D pci-host-common.o obj-$(CONFIG_PCI_HOST_GENERIC) +=3D pci-host-generic.o obj-$(CONFIG_PCI_HOST_THUNDER_ECAM) +=3D pci-thunder-ecam.o diff --git a/drivers/pci/controller/pcie-rzg3s-host.c b/drivers/pci/control= ler/pcie-rzg3s-host.c new file mode 100644 index 000000000000..7649674bf72d --- /dev/null +++ b/drivers/pci/controller/pcie-rzg3s-host.c @@ -0,0 +1,1686 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * PCIe driver for Renesas RZ/G3S SoCs + * + * Copyright (C) 2025 Renesas Electronics Corp. + * + * Based on: + * drivers/pci/controller/pcie-rcar-host.c + * Copyright (C) 2009 - 2011 Paul Mundt + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* AXI registers */ +#define RZG3S_PCI_REQDATA(id) (0x80 + (id) * 0x4) +#define RZG3S_PCI_REQRCVDAT 0x8c +#define RZG3S_PCI_REQADR1 0x90 +#define RZG3S_PCI_REQADR1_BUS GENMASK(31, 24) +#define RZG3S_PCI_REQADR1_DEV GENMASK(23, 19) +#define RZG3S_PCI_REQADR1_FUNC GENMASK(18, 16) +#define RZG3S_PCI_REQADR1_REG GENMASK(11, 0) +#define RZG3S_PCI_REQBE 0x98 +#define RZG3S_PCI_REQBE_BYTE_EN GENMASK(3, 0) +#define RZG3S_PCI_REQISS 0x9c +#define RZG3S_PCI_REQISS_REQ_ISSUE BIT(0) +#define RZG3S_PCI_REQISS_TR_TYPE GENMASK(11, 8) +#define RZG3S_PCI_REQISS_TR_TP0_RD FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0= x4) +#define RZG3S_PCI_REQISS_TR_TP0_WR FIELD_PREP(RZG3S_PCI_REQISS_TR_TYPE, 0= x5) +#define RZG3S_PCI_REQISS_MOR_STATUS GENMASK(18, 16) +#define RZG3S_PCI_MSIRCVWADRL 0x100 +#define RZG3S_PCI_MSIRCVWADRL_ENA BIT(0) +#define RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA BIT(1) +#define RZG3S_PCI_MSIRCVWADRU 0x104 +#define RZG3S_PCI_MSIRCVWMSKL 0x108 +#define RZG3S_PCI_MSIRCVWMSKU 0x10c +#define RZG3S_PCI_PINTRCVIE 0x110 +#define RZG3S_PCI_PINTRCVIE_INTX(i) BIT(i) +#define RZG3S_PCI_PINTRCVIE_MSI BIT(4) +#define RZG3S_PCI_PINTRCVIS 0x114 +#define RZG3S_PCI_PINTRCVIS_INTX(i) BIT(i) +#define RZG3S_PCI_PINTRCVIS_MSI BIT(4) +#define RZG3S_PCI_MSGRCVIE 0x120 +#define RZG3S_PCI_MSGRCVIE_MSG_RCV BIT(24) +#define RZG3S_PCI_MSGRCVIS 0x124 +#define RZG3S_PCI_MSGRCVIS_MRI BIT(24) +#define RZG3S_PCI_PEIE0 0x200 +#define RZG3S_PCI_PEIS0 0x204 +#define RZG3S_PCI_PEIS0_DL_UPDOWN BIT(9) +#define RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER BIT(12) +#define RZG3S_PCI_PEIE1 0x208 +#define RZG3S_PCI_PEIS1 0x20c +#define RZG3S_PCI_AMEIE 0x210 +#define RZG3S_PCI_AMEIS 0x214 +#define RZG3S_PCI_ASEIE1 0x220 +#define RZG3S_PCI_ASEIS1 0x224 +#define RZG3S_PCI_PCSTAT1 0x408 +#define RZG3S_PCI_PCSTAT1_DL_DOWN_STS BIT(0) +#define RZG3S_PCI_PCSTAT1_LTSSM_STATE GENMASK(14, 10) +#define RZG3S_PCI_PCCTRL2 0x410 +#define RZG3S_PCI_PCCTRL2_LS_CHG_REQ BIT(0) +#define RZG3S_PCI_PCCTRL2_LS_CHG GENMASK(9, 8) +#define RZG3S_PCI_PCSTAT2 0x414 +#define RZG3S_PCI_PCSTAT2_STATE_RX_DETECT GENMASK(15, 8) +#define RZG3S_PCI_PCSTAT2_SDRIRE GENMASK(7, 0) +#define RZG3S_PCI_PCSTAT2_LS_CHG_DONE BIT(28) +#define RZG3S_PCI_PERM 0x300 +#define RZG3S_PCI_PERM_PIPE_PHY_REG_EN BIT(1) +#define RZG3S_PCI_PERM_CFG_HWINIT_EN BIT(2) +#define RZG3S_PCI_MSIRE(id) (0x600 + (id) * 0x10) +#define RZG3S_PCI_MSIRE_ENA BIT(0) +#define RZG3S_PCI_MSIRM(id) (0x608 + (id) * 0x10) +#define RZG3S_PCI_MSIRS(id) (0x60c + (id) * 0x10) +#define RZG3S_PCI_AWBASEL(id) (0x1000 + (id) * 0x20) +#define RZG3S_PCI_AWBASEL_WIN_ENA BIT(0) +#define RZG3S_PCI_AWBASEU(id) (0x1004 + (id) * 0x20) +#define RZG3S_PCI_AWMASKL(id) (0x1008 + (id) * 0x20) +#define RZG3S_PCI_AWMASKU(id) (0x100c + (id) * 0x20) +#define RZG3S_PCI_ADESTL(id) (0x1010 + (id) * 0x20) +#define RZG3S_PCI_ADESTU(id) (0x1014 + (id) * 0x20) +#define RZG3S_PCI_PWBASEL(id) (0x1100 + (id) * 0x20) +#define RZG3S_PCI_PWBASEL_ENA BIT(0) +#define RZG3S_PCI_PWBASEU(id) (0x1104 + (id) * 0x20) +#define RZG3S_PCI_PDESTL(id) (0x1110 + (id) * 0x20) +#define RZG3S_PCI_PDESTU(id) (0x1114 + (id) * 0x20) +#define RZG3S_PCI_PWMASKL(id) (0x1108 + (id) * 0x20) +#define RZG3S_PCI_PWMASKU(id) (0x110c + (id) * 0x20) + +/* PHY control registers */ +#define RZG3S_PCI_PHY_XCFGD(id) (0x2000 + (id) * 0x10) +#define RZG3S_PCI_PHY_XCFGD_NUM 39 +#define RZG3S_PCI_PHY_XCFGA_CMN(id) (0x2400 + (id) * 0x10) +#define RZG3S_PCI_PHY_XCFGA_CMN_NUM 16 +#define RZG3S_PCI_PHY_XCFGA_RX(id) (0x2500 + (id) * 0x10) +#define RZG3S_PCI_PHY_XCFGA_RX_NUM 13 +#define RZG3S_PCI_PHY_XCFGA_TX 0x25d0 +#define RZG3S_PCI_PHY_XCFG_CTRL 0x2a20 +#define RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL BIT(0) + +/* PCIe registers */ +#define RZG3S_PCI_CFG_BASE 0x6000 +#define RZG3S_PCI_CFG_BARMSK00L 0xa0 +#define RZG3S_PCI_CFG_BARMSK00U 0xa4 +#define RZG3S_PCI_CFG_LINKCS 0x70 +#define RZG3S_PCI_CFG_LINKCS_CUR_LS GENMASK(19, 16) +#define RZG3S_PCI_CFG_LINCS2 0x90 +#define RZG3S_PCI_CFG_LINCS2_TARGET_LS GENMASK(3, 0) + +/* System controller registers */ +#define RZG3S_SYS_PCIE_RST_RSM_B 0xd74 +#define RZG3S_SYS_PCIE_RST_RSM_B_MASK BIT(0) + +/* Maximum number of windows */ +#define RZG3S_MAX_WINDOWS 8 + +/* Number of MSI interrupts per register */ +#define RZG3S_PCI_MSI_INT_PER_REG 32 +/* The number of MSI interrupts */ +#define RZG3S_PCI_MSI_INT_NR RZG3S_PCI_MSI_INT_PER_REG + +/* Timeouts */ +#define RZG3S_REQ_ISSUE_TIMEOUT_US 2500 +#define RZG3S_LTSSM_STATE_TIMEOUT_US 1000 +#define RZG3S_LS_CHANGE_TIMEOUT_US 1000 +#define RZG3S_LINK_UP_TIMEOUT_US 500000 + +/** + * enum rzg3s_pcie_link_speed - RZ/G3S PCIe available link speeds + * @RZG3S_PCIE_LINK_SPEED_2_5_GTS: 2.5 GT/s + * @RZG3S_PCIE_LINK_SPEED_5_0_GTS: 5.0 GT/s + */ +enum rzg3s_pcie_link_speed { + RZG3S_PCIE_LINK_SPEED_2_5_GTS =3D 1, + RZG3S_PCIE_LINK_SPEED_5_0_GTS +}; + +/** + * struct rzg3s_pcie_msi - RZ/G3S PCIe MSI data structure + * @domain: IRQ domain + * @map: bitmap with the allocated MSIs + * @dma_addr: address of the allocated MSI window + * @window_base: base address of the MSI window + * @pages: allocated pages for MSI window mapping + * @map_lock: lock for bitmap with the allocated MSIs + */ +struct rzg3s_pcie_msi { + struct irq_domain *domain; + DECLARE_BITMAP(map, RZG3S_PCI_MSI_INT_NR); + dma_addr_t dma_addr; + dma_addr_t window_base; + unsigned long pages; + struct mutex map_lock; +}; + +struct rzg3s_pcie_host; + +/** + * struct rzg3s_pcie_soc_data - SoC specific data + * @init_phy: PHY initialization function + * @power_resets: array with the resets that need to be de-asserted after + * power-on + * @cfg_resets: array with the resets that need to be de-asserted after + * configuration + * @num_power_resets: number of power resets + * @num_cfg_resets: number of configuration resets + */ +struct rzg3s_pcie_soc_data { + int (*init_phy)(struct rzg3s_pcie_host *host); + const char * const *power_resets; + const char * const *cfg_resets; + u8 num_power_resets; + u8 num_cfg_resets; +}; + +/** + * struct rzg3s_pcie_host - RZ/G3S PCIe data structure + * @axi: base address for AXI registers + * @pcie: base address for PCIe registers + * @dev: struct device + * @power_resets: reset control signals that should be set after power up + * @cfg_resets: reset control signals that should be set after configurati= on + * @sysc: SYSC regmap + * @intx_domain: INTx IRQ domain + * @data: SoC specific data + * @msi: MSI data structure + * @hw_lock: lock for access to the HW resources + * @intx_irqs: INTx interrupts + * @vendor_id: Vendor ID + * @device_id: Device ID + */ +struct rzg3s_pcie_host { + void __iomem *axi; + void __iomem *pcie; + struct device *dev; + struct reset_control_bulk_data *power_resets; + struct reset_control_bulk_data *cfg_resets; + struct regmap *sysc; + struct irq_domain *intx_domain; + const struct rzg3s_pcie_soc_data *data; + struct rzg3s_pcie_msi msi; + raw_spinlock_t hw_lock; + int intx_irqs[PCI_NUM_INTX]; + u32 vendor_id; + u32 device_id; +}; + +#define rzg3s_msi_to_host(_msi) container_of(_msi, struct rzg3s_pcie_host,= msi) + +static void rzg3s_pcie_update_bits(void __iomem *base, u32 offset, u32 mas= k, + u32 val) +{ + u32 tmp; + + tmp =3D readl(base + offset); + tmp &=3D ~mask; + tmp |=3D val & mask; + writel(tmp, base + offset); +} + +static bool rzg3s_pcie_child_issue_request(struct rzg3s_pcie_host *host) +{ + u32 val; + int ret; + + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_REQISS, + RZG3S_PCI_REQISS_REQ_ISSUE, + RZG3S_PCI_REQISS_REQ_ISSUE); + ret =3D readl_poll_timeout_atomic(host->axi + RZG3S_PCI_REQISS, val, + !(val & RZG3S_PCI_REQISS_REQ_ISSUE), + 5, RZG3S_REQ_ISSUE_TIMEOUT_US); + + return !!ret || (val & RZG3S_PCI_REQISS_MOR_STATUS); +} + +static int rzg3s_pcie_child_read_conf(struct rzg3s_pcie_host *host, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 *data) +{ + int ret; + + bus->ops->map_bus(bus, devfn, where); + + /* Set the type of request */ + writel(RZG3S_PCI_REQISS_TR_TP0_RD, host->axi + RZG3S_PCI_REQISS); + + /* Issue the request and wait to finish */ + ret =3D rzg3s_pcie_child_issue_request(host); + if (ret) + return PCIBIOS_SET_FAILED; + + /* Read the data */ + *data =3D readl(host->axi + RZG3S_PCI_REQRCVDAT); + + return PCIBIOS_SUCCESSFUL; +} + +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ +static int rzg3s_pcie_child_read(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 *val) +{ + struct rzg3s_pcie_host *host =3D bus->sysdata; + int ret; + + ret =3D rzg3s_pcie_child_read_conf(host, bus, devfn, where, val); + if (ret !=3D PCIBIOS_SUCCESSFUL) + return ret; + + if (size <=3D 2) + *val =3D (*val >> (8 * (where & 3))) & ((1 << (size * 8)) - 1); + + return PCIBIOS_SUCCESSFUL; +} + +static int rzg3s_pcie_child_write_conf(struct rzg3s_pcie_host *host, + struct pci_bus *bus, + unsigned int devfn, int where, + u32 data) +{ + int ret; + + bus->ops->map_bus(bus, devfn, where); + + /* Set the write data */ + writel(0, host->axi + RZG3S_PCI_REQDATA(0)); + writel(0, host->axi + RZG3S_PCI_REQDATA(1)); + writel(data, host->axi + RZG3S_PCI_REQDATA(2)); + + /* Set the type of request */ + writel(RZG3S_PCI_REQISS_TR_TP0_WR, host->axi + RZG3S_PCI_REQISS); + + /* Issue the request and wait to finish */ + ret =3D rzg3s_pcie_child_issue_request(host); + if (ret) + return PCIBIOS_SET_FAILED; + + return PCIBIOS_SUCCESSFUL; +} + +/* Serialization is provided by 'pci_lock' in drivers/pci/access.c */ +static int rzg3s_pcie_child_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct rzg3s_pcie_host *host =3D bus->sysdata; + u32 data, shift; + int ret; + + /* + * Controller does 32 bit accesses. To do byte accesses software need + * to do read/modify/write. This may have potential side effects. For + * example, software may perform a 16-bit write. If the hardware only + * supports 32-bit accesses, we must do a 32-bit read, merge in the 16 + * bits we intend to write, followed by a 32-bit write. If the 16 bits + * we *don't* intend to write happen to have any RW1C + * (write-one-to-clear) bits set, we just inadvertently cleared + * something we shouldn't have. + */ + if (!bus->unsafe_warn) { + dev_warn(&bus->dev, "%d-byte config write to %04x:%02x:%02x.%d offset %#= x may corrupt adjacent RW1C bits\n", + size, pci_domain_nr(bus), bus->number, + PCI_SLOT(devfn), PCI_FUNC(devfn), where); + bus->unsafe_warn =3D 1; + } + + ret =3D rzg3s_pcie_child_read_conf(host, bus, devfn, where, &data); + if (ret !=3D PCIBIOS_SUCCESSFUL) + return ret; + + if (size =3D=3D 1) { + shift =3D BITS_PER_BYTE * (where & 3); + data &=3D ~(0xff << shift); + data |=3D ((val & 0xff) << shift); + } else if (size =3D=3D 2) { + shift =3D BITS_PER_BYTE * (where & 2); + data &=3D ~(0xffff << shift); + data |=3D ((val & 0xffff) << shift); + } else { + data =3D val; + } + + return rzg3s_pcie_child_write_conf(host, bus, devfn, where, data); +} + +static void __iomem *rzg3s_pcie_child_map_bus(struct pci_bus *bus, + unsigned int devfn, + int where) +{ + struct rzg3s_pcie_host *host =3D bus->sysdata; + unsigned int dev, func, reg; + + dev =3D PCI_SLOT(devfn); + func =3D PCI_FUNC(devfn); + reg =3D where & ~0x3; + + /* Set the destination */ + writel(FIELD_PREP(RZG3S_PCI_REQADR1_BUS, bus->number) | + FIELD_PREP(RZG3S_PCI_REQADR1_DEV, dev) | + FIELD_PREP(RZG3S_PCI_REQADR1_FUNC, func) | + FIELD_PREP(RZG3S_PCI_REQADR1_REG, reg), + host->axi + RZG3S_PCI_REQADR1); + + /* Set byte enable */ + writel(RZG3S_PCI_REQBE_BYTE_EN, host->axi + RZG3S_PCI_REQBE); + + return host->axi + where; +} + +static struct pci_ops rzg3s_pcie_child_ops =3D { + .read =3D rzg3s_pcie_child_read, + .write =3D rzg3s_pcie_child_write, + .map_bus =3D rzg3s_pcie_child_map_bus, +}; + +static void __iomem *rzg3s_pcie_root_map_bus(struct pci_bus *bus, + unsigned int devfn, + int where) +{ + struct rzg3s_pcie_host *host =3D bus->sysdata; + + if (devfn) + return NULL; + + return host->pcie + where; +} + +static int rzg3s_pcie_root_write(struct pci_bus *bus, unsigned int devfn, + int where, int size, u32 val) +{ + struct rzg3s_pcie_host *host =3D bus->sysdata; + + writel(RZG3S_PCI_PERM_CFG_HWINIT_EN, host->axi + RZG3S_PCI_PERM); + pci_generic_config_write(bus, devfn, where, size, val); + writel(0, host->axi + RZG3S_PCI_PERM); + + return PCIBIOS_SUCCESSFUL; +} + +static struct pci_ops rzg3s_pcie_root_ops =3D { + .read =3D pci_generic_config_read, + .write =3D rzg3s_pcie_root_write, + .map_bus =3D rzg3s_pcie_root_map_bus, +}; + +static void rzg3s_pcie_intx_irq_handler(struct irq_desc *desc) +{ + struct rzg3s_pcie_host *host =3D irq_desc_get_handler_data(desc); + struct irq_chip *chip =3D irq_desc_get_chip(desc); + unsigned int irq =3D irq_desc_get_irq(desc); + u32 intx =3D irq - host->intx_irqs[0]; + + chained_irq_enter(chip, desc); + generic_handle_domain_irq(host->intx_domain, intx); + chained_irq_exit(chip, desc); +} + +static irqreturn_t rzg3s_pcie_msi_irq(int irq, void *data) +{ + u8 regs =3D RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; + DECLARE_BITMAP(bitmap, RZG3S_PCI_MSI_INT_NR); + struct rzg3s_pcie_host *host =3D data; + struct rzg3s_pcie_msi *msi =3D &host->msi; + unsigned long bit; + u32 status; + + status =3D readl(host->axi + RZG3S_PCI_PINTRCVIS); + if (!(status & RZG3S_PCI_PINTRCVIS_MSI)) + return IRQ_NONE; + + /* Clear the MSI */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, + RZG3S_PCI_PINTRCVIS_MSI, + RZG3S_PCI_PINTRCVIS_MSI); + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIS, + RZG3S_PCI_MSGRCVIS_MRI, RZG3S_PCI_MSGRCVIS_MRI); + + for (u8 reg_id =3D 0; reg_id < regs; reg_id++) { + status =3D readl(host->axi + RZG3S_PCI_MSIRS(reg_id)); + bitmap_write(bitmap, status, reg_id * RZG3S_PCI_MSI_INT_PER_REG, + RZG3S_PCI_MSI_INT_PER_REG); + } + + for_each_set_bit(bit, bitmap, RZG3S_PCI_MSI_INT_NR) { + int ret; + + ret =3D generic_handle_domain_irq(msi->domain->parent, bit); + if (ret) { + u8 reg_bit =3D bit % RZG3S_PCI_MSI_INT_PER_REG; + u8 reg_id =3D bit / RZG3S_PCI_MSI_INT_PER_REG; + + /* Unknown MSI, just clear it */ + writel(BIT(reg_bit), + host->axi + RZG3S_PCI_MSIRS(reg_id)); + } + } + + return IRQ_HANDLED; +} + +static void rzg3s_pcie_msi_top_irq_ack(struct irq_data *d) +{ + irq_chip_ack_parent(d); +} + +static void rzg3s_pcie_msi_top_irq_mask(struct irq_data *d) +{ + pci_msi_mask_irq(d); + irq_chip_mask_parent(d); +} + +static void rzg3s_pcie_msi_top_irq_unmask(struct irq_data *d) +{ + pci_msi_unmask_irq(d); + irq_chip_unmask_parent(d); +} + +static struct irq_chip rzg3s_pcie_msi_top_chip =3D { + .name =3D "PCIe MSI", + .irq_ack =3D rzg3s_pcie_msi_top_irq_ack, + .irq_mask =3D rzg3s_pcie_msi_top_irq_mask, + .irq_unmask =3D rzg3s_pcie_msi_top_irq_unmask, +}; + +static void rzg3s_pcie_msi_irq_ack(struct irq_data *d) +{ + struct rzg3s_pcie_msi *msi =3D irq_data_get_irq_chip_data(d); + struct rzg3s_pcie_host *host =3D rzg3s_msi_to_host(msi); + u8 reg_bit =3D d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; + u8 reg_id =3D d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; + + guard(raw_spinlock_irqsave)(&host->hw_lock); + + writel(BIT(reg_bit), host->axi + RZG3S_PCI_MSIRS(reg_id)); +} + +static void rzg3s_pcie_msi_irq_mask(struct irq_data *d) +{ + struct rzg3s_pcie_msi *msi =3D irq_data_get_irq_chip_data(d); + struct rzg3s_pcie_host *host =3D rzg3s_msi_to_host(msi); + u8 reg_bit =3D d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; + u8 reg_id =3D d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; + + guard(raw_spinlock_irqsave)(&host->hw_lock); + + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), + BIT(reg_bit)); +} + +static void rzg3s_pcie_msi_irq_unmask(struct irq_data *d) +{ + struct rzg3s_pcie_msi *msi =3D irq_data_get_irq_chip_data(d); + struct rzg3s_pcie_host *host =3D rzg3s_msi_to_host(msi); + u8 reg_bit =3D d->hwirq % RZG3S_PCI_MSI_INT_PER_REG; + u8 reg_id =3D d->hwirq / RZG3S_PCI_MSI_INT_PER_REG; + + guard(raw_spinlock_irqsave)(&host->hw_lock); + + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSIRM(reg_id), BIT(reg_bit), + 0); +} + +static void rzg3s_pcie_irq_compose_msi_msg(struct irq_data *data, + struct msi_msg *msg) +{ + struct rzg3s_pcie_msi *msi =3D irq_data_get_irq_chip_data(data); + struct rzg3s_pcie_host *host =3D rzg3s_msi_to_host(msi); + u32 drop_mask =3D RZG3S_PCI_MSIRCVWADRL_ENA | + RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA; + u32 lo, hi; + + /* + * Enable and msg data enable bits are part of the address lo. Drop + * them. + */ + lo =3D readl(host->axi + RZG3S_PCI_MSIRCVWADRL) & ~drop_mask; + hi =3D readl(host->axi + RZG3S_PCI_MSIRCVWADRU); + + msg->address_lo =3D lo; + msg->address_hi =3D hi; + msg->data =3D data->hwirq; +} + +static struct irq_chip rzg3s_pcie_msi_bottom_chip =3D { + .name =3D "rzg3s-pcie-msi", + .irq_ack =3D rzg3s_pcie_msi_irq_ack, + .irq_mask =3D rzg3s_pcie_msi_irq_mask, + .irq_unmask =3D rzg3s_pcie_msi_irq_unmask, + .irq_compose_msi_msg =3D rzg3s_pcie_irq_compose_msi_msg, +}; + +static int rzg3s_pcie_msi_domain_alloc(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs, + void *args) +{ + struct rzg3s_pcie_msi *msi =3D domain->host_data; + int hwirq; + + scoped_guard(mutex, &msi->map_lock) { + hwirq =3D bitmap_find_free_region(msi->map, RZG3S_PCI_MSI_INT_NR, + order_base_2(nr_irqs)); + } + + if (hwirq < 0) + return -ENOSPC; + + for (unsigned int i =3D 0; i < nr_irqs; i++) { + irq_domain_set_info(domain, virq + i, hwirq + i, + &rzg3s_pcie_msi_bottom_chip, + domain->host_data, handle_edge_irq, NULL, + NULL); + } + + return 0; +} + +static void rzg3s_pcie_msi_domain_free(struct irq_domain *domain, + unsigned int virq, unsigned int nr_irqs) +{ + struct irq_data *d =3D irq_domain_get_irq_data(domain, virq); + struct rzg3s_pcie_msi *msi =3D domain->host_data; + + guard(mutex)(&msi->map_lock); + + bitmap_release_region(msi->map, d->hwirq, order_base_2(nr_irqs)); +} + +static const struct irq_domain_ops rzg3s_pcie_msi_domain_ops =3D { + .alloc =3D rzg3s_pcie_msi_domain_alloc, + .free =3D rzg3s_pcie_msi_domain_free, +}; + +static struct msi_domain_info rzg3s_pcie_msi_info =3D { + .flags =3D MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | + MSI_FLAG_MULTI_PCI_MSI | MSI_FLAG_NO_AFFINITY, + .chip =3D &rzg3s_pcie_msi_top_chip, +}; + +static int rzg3s_pcie_msi_allocate_domains(struct rzg3s_pcie_msi *msi) +{ + struct rzg3s_pcie_host *host =3D rzg3s_msi_to_host(msi); + struct device *dev =3D host->dev; + struct fwnode_handle *fwnode =3D dev_fwnode(dev); + struct irq_domain *parent; + + parent =3D irq_domain_create_linear(fwnode, RZG3S_PCI_MSI_INT_NR, + &rzg3s_pcie_msi_domain_ops, msi); + if (!parent) + return dev_err_probe(dev, -ENOMEM, + "failed to create IRQ domain\n"); + irq_domain_update_bus_token(parent, DOMAIN_BUS_NEXUS); + + msi->domain =3D pci_msi_create_irq_domain(fwnode, &rzg3s_pcie_msi_info, + parent); + if (!msi->domain) { + irq_domain_remove(parent); + return dev_err_probe(dev, -ENOMEM, + "failed to create MSI domain\n"); + } + + return 0; +} + +static void rzg3s_pcie_msi_free_domains(struct rzg3s_pcie_msi *msi) +{ + struct irq_domain *parent =3D msi->domain->parent; + + irq_domain_remove(msi->domain); + irq_domain_remove(parent); +} + +static int rzg3s_pcie_msi_hw_setup(struct rzg3s_pcie_host *host) +{ + u8 regs =3D RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; + struct rzg3s_pcie_msi *msi =3D &host->msi; + + /* + * Set MSI window size. HW will set the window to + * RZG3S_PCI_MSI_INT_NR * 4 bytes. + */ + writel(RZG3S_PCI_MSI_INT_NR - 1, host->axi + RZG3S_PCI_MSIRCVWMSKL); + + /* Set MSI window address and enable MSI window */ + writel(upper_32_bits(msi->window_base), + host->axi + RZG3S_PCI_MSIRCVWADRU); + writel(lower_32_bits(msi->window_base) | RZG3S_PCI_MSIRCVWADRL_ENA | + RZG3S_PCI_MSIRCVWADRL_MSG_DATA_ENA, + host->axi + RZG3S_PCI_MSIRCVWADRL); + + /* Set MSI receive enable */ + for (u8 reg_id =3D 0; reg_id < regs; reg_id++) { + writel(RZG3S_PCI_MSIRE_ENA, + host->axi + RZG3S_PCI_MSIRE(reg_id)); + } + + /* Enable message receive interrupts */ + writel(RZG3S_PCI_MSGRCVIE_MSG_RCV, host->axi + RZG3S_PCI_MSGRCVIE); + + /* Enable MSI */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, + RZG3S_PCI_PINTRCVIE_MSI, + RZG3S_PCI_PINTRCVIE_MSI); + + return 0; +} + +static int rzg3s_pcie_msi_setup(struct rzg3s_pcie_host *host) +{ + size_t size =3D RZG3S_PCI_MSI_INT_NR * sizeof(u32); + struct rzg3s_pcie_msi *msi =3D &host->msi; + struct device *dev =3D host->dev; + int id, ret; + + msi->pages =3D __get_free_pages(GFP_KERNEL | GFP_DMA, 0); + if (!msi->pages) + return -ENOMEM; + + msi->dma_addr =3D dma_map_single(dev, (void *)msi->pages, size * 2, + DMA_BIDIRECTIONAL); + if (dma_mapping_error(dev, msi->dma_addr)) { + ret =3D -ENOMEM; + goto free_pages; + } + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section 34.4.5.2 Setting + * the MSI Window) the MSI window need to be within any AXI window. Find + * an AXI window to setup the MSI window. + */ + for (id =3D 0; id < RZG3S_MAX_WINDOWS; id++) { + u64 base, basel, baseu; + u64 mask, maskl, masku; + + basel =3D readl(host->axi + RZG3S_PCI_AWBASEL(id)); + /* Skip checking this AXI window if it's not enabled */ + if (!(basel & RZG3S_PCI_AWBASEL_WIN_ENA)) + continue; + + baseu =3D readl(host->axi + RZG3S_PCI_AWBASEU(id)); + base =3D baseu << 32 | basel; + + maskl =3D readl(host->axi + RZG3S_PCI_AWMASKL(id)); + masku =3D readl(host->axi + RZG3S_PCI_AWMASKU(id)); + mask =3D masku << 32 | maskl; + + if (msi->dma_addr < base || msi->dma_addr > base + mask) + continue; + + break; + } + + if (id =3D=3D RZG3S_MAX_WINDOWS) { + ret =3D -EINVAL; + goto dma_unmap; + } + + /* The MSI base address need to be aligned to the MSI size */ + msi->window_base =3D ALIGN(msi->dma_addr, size); + if (msi->window_base < msi->dma_addr) { + ret =3D -EINVAL; + goto dma_unmap; + } + + rzg3s_pcie_msi_hw_setup(host); + + return 0; + +dma_unmap: + dma_unmap_single(dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); +free_pages: + free_pages(msi->pages, 0); + return ret; +} + +static int rzg3s_pcie_msi_enable(struct rzg3s_pcie_host *host) +{ + struct platform_device *pdev =3D to_platform_device(host->dev); + struct rzg3s_pcie_msi *msi =3D &host->msi; + struct device *dev =3D host->dev; + const char *devname; + int irq, ret; + + mutex_init(&msi->map_lock); + + irq =3D platform_get_irq_byname(pdev, "msi"); + if (irq < 0) + return dev_err_probe(dev, irq ? irq : -EINVAL, + "Failed to get MSI IRQ!\n"); + + devname =3D devm_kasprintf(dev, GFP_KERNEL, "%s-msi", dev_name(dev)); + if (!devname) + return -ENOMEM; + + ret =3D rzg3s_pcie_msi_allocate_domains(msi); + if (ret) + return ret; + + ret =3D devm_request_irq(dev, irq, rzg3s_pcie_msi_irq, 0, devname, host); + if (ret) { + dev_err_probe(dev, ret, "Failed to request IRQ: %d\n", ret); + goto free_domains; + } + + ret =3D rzg3s_pcie_msi_setup(host); + if (ret) { + dev_err_probe(dev, ret, "Failed to setup MSI!\n"); + goto free_domains; + } + + return 0; + +free_domains: + rzg3s_pcie_msi_free_domains(msi); + return ret; +} + +static void rzg3s_pcie_msi_teardown(void *data) +{ + u8 regs =3D RZG3S_PCI_MSI_INT_NR / RZG3S_PCI_MSI_INT_PER_REG; + size_t size =3D RZG3S_PCI_MSI_INT_NR * sizeof(u32); + struct rzg3s_pcie_host *host =3D data; + struct rzg3s_pcie_msi *msi =3D &host->msi; + + /* Disable MSI */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, + RZG3S_PCI_PINTRCVIE_MSI, 0); + + /* Disable message receive interrupts */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_MSGRCVIE, + RZG3S_PCI_MSGRCVIE_MSG_RCV, 0); + + /* Disable MSI receive enable */ + for (u8 reg_id =3D 0; reg_id < regs; reg_id++) + writel(0, host->axi + RZG3S_PCI_MSIRE(reg_id)); + + /* Disable MSI window */ + writel(0, host->axi + RZG3S_PCI_MSIRCVWADRL); + + /* Free unused memory */ + dma_unmap_single(host->dev, msi->dma_addr, size * 2, DMA_BIDIRECTIONAL); + free_pages(msi->pages, 0); + + rzg3s_pcie_msi_free_domains(msi); +} + +static void rzg3s_pcie_intx_irq_ack(struct irq_data *d) +{ + struct rzg3s_pcie_host *host =3D irq_data_get_irq_chip_data(d); + + guard(raw_spinlock_irqsave)(&host->hw_lock); + + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIS, + RZG3S_PCI_PINTRCVIS_INTX(d->hwirq), + RZG3S_PCI_PINTRCVIS_INTX(d->hwirq)); +} + +static void rzg3s_pcie_intx_irq_mask(struct irq_data *d) +{ + struct rzg3s_pcie_host *host =3D irq_data_get_irq_chip_data(d); + + guard(raw_spinlock_irqsave)(&host->hw_lock); + + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, + RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), 0); +} + +static void rzg3s_pcie_intx_irq_unmask(struct irq_data *d) +{ + struct rzg3s_pcie_host *host =3D irq_data_get_irq_chip_data(d); + + guard(raw_spinlock_irqsave)(&host->hw_lock); + + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PINTRCVIE, + RZG3S_PCI_PINTRCVIE_INTX(d->hwirq), + RZG3S_PCI_PINTRCVIE_INTX(d->hwirq)); +} + +static struct irq_chip rzg3s_pcie_intx_irq_chip =3D { + .name =3D "PCIe INTx", + .irq_ack =3D rzg3s_pcie_intx_irq_ack, + .irq_mask =3D rzg3s_pcie_intx_irq_mask, + .irq_unmask =3D rzg3s_pcie_intx_irq_unmask, +}; + +static int rzg3s_pcie_intx_map(struct irq_domain *domain, unsigned int irq, + irq_hw_number_t hwirq) +{ + irq_set_chip_and_handler(irq, &rzg3s_pcie_intx_irq_chip, + handle_level_irq); + irq_set_chip_data(irq, domain->host_data); + + return 0; +} + +static const struct irq_domain_ops rzg3s_pcie_intx_domain_ops =3D { + .map =3D rzg3s_pcie_intx_map, + .xlate =3D irq_domain_xlate_onetwocell, +}; + +static int rzg3s_pcie_intx_setup(struct rzg3s_pcie_host *host) +{ + struct device *dev =3D host->dev; + + for (int i =3D 0; i < PCI_NUM_INTX; i++) { + struct platform_device *pdev =3D to_platform_device(dev); + char irq_name[5] =3D {0}; + int irq; + + scnprintf(irq_name, ARRAY_SIZE(irq_name), "int%c", 97 + i); + + irq =3D platform_get_irq_byname(pdev, irq_name); + if (irq < 0) + return dev_err_probe(dev, -EINVAL, + "Failed to parse and map INT%c IRQ\n", + 65 + i); + + host->intx_irqs[i] =3D irq; + irq_set_chained_handler_and_data(irq, + rzg3s_pcie_intx_irq_handler, + host); + } + + host->intx_domain =3D irq_domain_add_linear(dev->of_node, PCI_NUM_INTX, + &rzg3s_pcie_intx_domain_ops, + host); + if (!host->intx_domain) + return dev_err_probe(dev, -EINVAL, + "Failed to add irq domain for INTx IRQs\n"); + irq_domain_update_bus_token(host->intx_domain, DOMAIN_BUS_WIRED); + + return 0; +} + +static void rzg3s_pcie_intx_teardown(void *data) +{ + struct rzg3s_pcie_host *host =3D data; + + irq_domain_remove(host->intx_domain); +} + +static int rzg3s_pcie_set_max_link_speed(struct rzg3s_pcie_host *host) +{ + u32 lcs, cs2, link_speed, remote_supported_link_speeds, tmp; + u8 ltssm_state_l0 =3D 0xc; + int ret; + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution + * when Changing the Speed Spontaneously) link speed change can be done + * only when the link training and status state machine in the PCIe Core + * Link is L0. + */ + ret =3D readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, tmp, + FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp) =3D=3D ltssm_state_l0, + 100, RZG3S_LTSSM_STATE_TIMEOUT_US); + if (ret) { + dev_dbg(host->dev, + "Could not set max link speed! LTSSM not in L0, state=3D%lx\n", + FIELD_GET(RZG3S_PCI_PCSTAT1_LTSSM_STATE, tmp)); + return ret; + } + + lcs =3D readl(host->pcie + RZG3S_PCI_CFG_LINKCS); + cs2 =3D readl(host->axi + RZG3S_PCI_PCSTAT2); + + link_speed =3D FIELD_GET(RZG3S_PCI_CFG_LINKCS_CUR_LS, lcs); + remote_supported_link_speeds =3D FIELD_GET(RZG3S_PCI_PCSTAT2_SDRIRE, cs2); + + /* + * Return if link is @ 5.0 GT/s or the connected device doesn't support + * it. + */ + if (link_speed =3D=3D RZG3S_PCIE_LINK_SPEED_5_0_GTS || + !(remote_supported_link_speeds & BIT(RZG3S_PCIE_LINK_SPEED_5_0_GTS))) + return 0; + + /* Set target Link speed to 5.0 GT/s */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_CFG_LINCS2, + RZG3S_PCI_CFG_LINCS2_TARGET_LS, + FIELD_PREP(RZG3S_PCI_CFG_LINCS2_TARGET_LS, + RZG3S_PCIE_LINK_SPEED_5_0_GTS)); + + /* Request link speed change */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, + RZG3S_PCI_PCCTRL2_LS_CHG_REQ | + RZG3S_PCI_PCCTRL2_LS_CHG, + RZG3S_PCI_PCCTRL2_LS_CHG_REQ | + FIELD_PREP(RZG3S_PCI_PCCTRL2_LS_CHG, + RZG3S_PCIE_LINK_SPEED_5_0_GTS - 1)); + + ret =3D readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT2, cs2, + (cs2 & RZG3S_PCI_PCSTAT2_LS_CHG_DONE), 100, + RZG3S_LS_CHANGE_TIMEOUT_US); + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section 34.6.3 Caution + * when Changing the Speed Spontaneously) the PCI_PCCTRL2_LS_CHG_REQ + * should be de-asserted after checking for PCI_PCSTAT2_LS_CHG_DONE. + */ + rzg3s_pcie_update_bits(host->axi, RZG3S_PCI_PCCTRL2, + RZG3S_PCI_PCCTRL2_LS_CHG_REQ, 0); + + return ret; +} + +static int rzg3s_pcie_config_init(struct rzg3s_pcie_host *host) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(host); + struct resource_entry *ft; + struct resource *bus; + u8 subordinate_bus; + u8 secondary_bus; + u8 primary_bus; + + ft =3D resource_list_first_type(&bridge->windows, IORESOURCE_BUS); + if (!ft) + return -ENODEV; + + bus =3D ft->res; + primary_bus =3D bus->start; + secondary_bus =3D bus->start + 1; + subordinate_bus =3D bus->end; + + /* Enable access control to the CFGU */ + writel(RZG3S_PCI_PERM_CFG_HWINIT_EN, host->axi + RZG3S_PCI_PERM); + + /* Update vendor ID and device ID */ + writew(host->vendor_id, host->pcie + PCI_VENDOR_ID); + writew(host->device_id, host->pcie + PCI_DEVICE_ID); + + /* HW manual recommends to write 0xffffffff on initialization */ + writel(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00L); + writel(0xffffffff, host->pcie + RZG3S_PCI_CFG_BARMSK00U); + + /* Update bus info. */ + writeb(primary_bus, host->pcie + PCI_PRIMARY_BUS); + writeb(secondary_bus, host->pcie + PCI_SECONDARY_BUS); + writeb(subordinate_bus, host->pcie + PCI_SUBORDINATE_BUS); + + /* Disable access control to the CFGU */ + writel(0, host->axi + RZG3S_PCI_PERM); + + return 0; +} + +static void rzg3s_pcie_irq_init(struct rzg3s_pcie_host *host) +{ + /* + * According to the HW manual of the RZ/G3S (Rev.1.10, sections + * corresponding to all registers written with ~0U), the hardware + * ignores value written to unused bits. Writing ~0U to these registers + * should be safe. + */ + + /* Clear the link state and PM transitions */ + writel(RZG3S_PCI_PEIS0_DL_UPDOWN | RZG3S_PCI_PEIS0_RX_DLLP_PM_ENTER, + host->axi + RZG3S_PCI_PEIS0); + + /* Disable all interrupts */ + writel(0, host->axi + RZG3S_PCI_PEIE0); + + /* Clear all parity and ecc error interrupts */ + writel(~0U, host->axi + RZG3S_PCI_PEIS1); + + /* Disable all parity and ecc error interrupts */ + writel(0, host->axi + RZG3S_PCI_PEIE1); + + /* Clear all AXI master error interrupts */ + writel(~0U, host->axi + RZG3S_PCI_AMEIS); + + /* Clear all AXI slave error interrupts */ + writel(~0U, host->axi + RZG3S_PCI_ASEIS1); + + /* Clear all message receive interrupts */ + writel(~0U, host->axi + RZG3S_PCI_MSGRCVIS); +} + +static void rzg3s_pcie_power_resets_action(void *data) +{ + struct rzg3s_pcie_host *host =3D data; + + reset_control_bulk_assert(host->data->num_power_resets, + host->power_resets); +} + +static void rzg3s_pcie_cfg_resets_action(void *data) +{ + struct rzg3s_pcie_host *host =3D data; + + reset_control_bulk_assert(host->data->num_cfg_resets, + host->cfg_resets); +} + +static int rzg3s_pcie_resets_prepare(struct rzg3s_pcie_host *host) +{ + const struct rzg3s_pcie_soc_data *data =3D host->data; + int ret; + + host->power_resets =3D devm_kmalloc_array(host->dev, + data->num_power_resets, + sizeof(*host->power_resets), + GFP_KERNEL); + if (!host->power_resets) + return -ENOMEM; + + for (unsigned int i =3D 0; i < data->num_power_resets; i++) + host->power_resets[i].id =3D data->power_resets[i]; + + host->cfg_resets =3D devm_kmalloc_array(host->dev, + data->num_cfg_resets, + sizeof(*host->cfg_resets), + GFP_KERNEL); + if (!host->cfg_resets) + return -ENOMEM; + + for (unsigned int i =3D 0; i < data->num_cfg_resets; i++) + host->cfg_resets[i].id =3D data->cfg_resets[i]; + + ret =3D devm_reset_control_bulk_get_exclusive(host->dev, + data->num_power_resets, + host->power_resets); + if (ret) + return ret; + + ret =3D devm_reset_control_bulk_get_exclusive(host->dev, + data->num_cfg_resets, + host->cfg_resets); + if (ret) + return ret; + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section + * 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from + * power on to the de-assertion of reset. + */ + usleep_range(5000, 5100); + ret =3D reset_control_bulk_deassert(data->num_power_resets, + host->power_resets); + if (ret) + return ret; + + return devm_add_action_or_reset(host->dev, + rzg3s_pcie_power_resets_action, host); +} + +static int rzg3s_pcie_host_init(struct rzg3s_pcie_host *host, bool probe) +{ + u32 val; + int ret; + + /* Initialize the PCIe related registers */ + ret =3D rzg3s_pcie_config_init(host); + if (ret) + return ret; + + /* Initialize the interrupts */ + rzg3s_pcie_irq_init(host); + + ret =3D reset_control_bulk_deassert(host->data->num_cfg_resets, + host->cfg_resets); + if (ret) + return ret; + + /* Wait for link up */ + ret =3D readl_poll_timeout(host->axi + RZG3S_PCI_PCSTAT1, val, + !(val & RZG3S_PCI_PCSTAT1_DL_DOWN_STS), 5000, + RZG3S_LINK_UP_TIMEOUT_US); + if (ret) { + reset_control_bulk_assert(host->data->num_cfg_resets, + host->cfg_resets); + return ret; + } + + val =3D readl(host->axi + RZG3S_PCI_PCSTAT2); + dev_info(host->dev, "PCIe link status [0x%x]\n", val); + + val =3D FIELD_GET(RZG3S_PCI_PCSTAT2_STATE_RX_DETECT, val); + dev_info(host->dev, "PCIe x%d: link up\n", hweight32(val)); + + if (probe) { + ret =3D devm_add_action_or_reset(host->dev, + rzg3s_pcie_cfg_resets_action, + host); + } + + return ret; +} + +static void rzg3s_pcie_set_inbound_window(struct rzg3s_pcie_host *host, + u64 cpu_addr, u64 pci_addr, u64 size, + int id) +{ + /* Set CPU window base address */ + writel(upper_32_bits(cpu_addr), host->axi + RZG3S_PCI_ADESTU(id)); + writel(lower_32_bits(cpu_addr), host->axi + RZG3S_PCI_ADESTL(id)); + + /* Set window size */ + writel(upper_32_bits(size), host->axi + RZG3S_PCI_AWMASKU(id)); + writel(lower_32_bits(size), host->axi + RZG3S_PCI_AWMASKL(id)); + + /* Set PCIe window base address and enable the window */ + writel(upper_32_bits(pci_addr), host->axi + RZG3S_PCI_AWBASEU(id)); + writel(lower_32_bits(pci_addr) | RZG3S_PCI_AWBASEL_WIN_ENA, + host->axi + RZG3S_PCI_AWBASEL(id)); +} + +static int rzg3s_pcie_set_inbound_windows(struct rzg3s_pcie_host *host, + struct resource_entry *entry, + int *index) +{ + u64 pci_addr =3D entry->res->start - entry->offset; + u64 cpu_addr =3D entry->res->start; + u64 cpu_end =3D entry->res->end; + u64 size_id =3D 0; + int id =3D *index; + u64 size; + + while (cpu_addr < cpu_end) { + if (id >=3D RZG3S_MAX_WINDOWS) + return dev_err_probe(host->dev, -EINVAL, + "Failed to set inbound windows!\n"); + + size =3D resource_size(entry->res) - size_id; + + /* + * According to the RZ/G3S HW manual (Rev.1.10, + * section 34.3.1.71 AXI Window Mask (Lower) Registers) the min + * size is 4K. + */ + size =3D max(size, 4096); + + /* + * According the RZ/G3S HW manual (Rev.1.10, sections: + * - 34.3.1.69 AXI Window Base (Lower) Registers + * - 34.3.1.71 AXI Window Mask (Lower) Registers + * - 34.3.1.73 AXI Destination (Lower) Registers) + * the CPU addr, PCIe addr, size should be 4K alined and be a + * power of 2. + */ + size =3D ALIGN(size, 4096); + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section + * 34.3.1.71 AXI Window Mask (Lower) Registers) HW expects first + * 12 LSB bits to be 0xfff. Extract 1 from size for this. + */ + size =3D roundup_pow_of_two(size) - 1; + + cpu_addr =3D ALIGN(cpu_addr, 4096); + pci_addr =3D ALIGN(pci_addr, 4096); + + rzg3s_pcie_set_inbound_window(host, cpu_addr, pci_addr, size, + id); + + pci_addr +=3D size; + cpu_addr +=3D size; + size_id =3D size; + id++; + } + *index =3D id; + + return 0; +} + +static int rzg3s_pcie_parse_map_dma_ranges(struct rzg3s_pcie_host *host) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(host); + struct resource_entry *entry; + int i =3D 0, ret; + + resource_list_for_each_entry(entry, &bridge->dma_ranges) { + ret =3D rzg3s_pcie_set_inbound_windows(host, entry, &i); + if (ret) + return ret; + } + + return 0; +} + +static void rzg3s_pcie_set_outbound_window(struct rzg3s_pcie_host *host, + struct resource_entry *win, + int id) +{ + struct resource *res =3D win->res; + resource_size_t size =3D resource_size(res); + resource_size_t res_start; + + if (res->flags & IORESOURCE_IO) + res_start =3D pci_pio_to_address(res->start) - win->offset; + else + res_start =3D res->start - win->offset; + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section 34.3.1.75 PCIe + * Window Base (Lower) Registers) the window base address need to be 4K + * aligned. + */ + res_start =3D ALIGN(res_start, 4096); + + size =3D ALIGN(size, 4096); + size =3D roundup_pow_of_two(size) - 1; + + /* Set PCIe destination */ + writel(upper_32_bits(res_start), host->axi + RZG3S_PCI_PDESTU(id)); + writel(lower_32_bits(res_start), host->axi + RZG3S_PCI_PDESTL(id)); + + /* Set PCIe window mask */ + writel(upper_32_bits(size), host->axi + RZG3S_PCI_PWMASKU(id)); + writel(lower_32_bits(size), host->axi + RZG3S_PCI_PWMASKL(id)); + + /* Set PCIe window base and enable the window */ + writel(upper_32_bits(res_start), host->axi + RZG3S_PCI_PWBASEU(id)); + writel(lower_32_bits(res_start) | RZG3S_PCI_PWBASEL_ENA, + host->axi + RZG3S_PCI_PWBASEL(id)); +} + +static int rzg3s_pcie_parse_map_ranges(struct rzg3s_pcie_host *host) +{ + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(host); + struct resource_entry *win; + int i =3D 0; + + resource_list_for_each_entry(win, &bridge->windows) { + struct resource *res =3D win->res; + + if (i >=3D RZG3S_MAX_WINDOWS) + return dev_err_probe(host->dev, -EINVAL, + "Failed to set outbound windows!\n"); + + if (!res->flags) + continue; + + switch (resource_type(res)) { + case IORESOURCE_IO: + case IORESOURCE_MEM: + rzg3s_pcie_set_outbound_window(host, win, i); + i++; + break; + } + } + + return 0; +} + +static int rzg3s_soc_pcie_init_phy(struct rzg3s_pcie_host *host) +{ + static const u32 xcfgd_settings[RZG3S_PCI_PHY_XCFGD_NUM] =3D { + [8] =3D 0xe0006801, 0x007f7e30, 0x183e0000, 0x978ff500, + 0xec000000, 0x009f1400, 0x0000d009, + [17] =3D 0x78000000, + [19] =3D 0x00880000, 0x000005c0, 0x07000000, 0x00780920, + 0xc9400ce2, 0x90000c0c, 0x000c1414, 0x00005034, + 0x00006000, 0x00000001, + }; + static const u32 xcfga_cmn_settings[RZG3S_PCI_PHY_XCFGA_CMN_NUM] =3D { + 0x00000d10, 0x08310100, 0x00c21404, 0x013c0010, 0x01874440, + 0x1a216082, 0x00103440, 0x00000080, 0x00000010, 0x0c1000c1, + 0x1000c100, 0x0222000c, 0x00640019, 0x00a00028, 0x01d11228, + 0x0201001d, + }; + static const u32 xcfga_rx_settings[RZG3S_PCI_PHY_XCFGA_RX_NUM] =3D { + 0x07d55000, 0x030e3f00, 0x00000288, 0x102c5880, 0x0000000b, + 0x04141441, 0x00641641, 0x00d63d63, 0x00641641, 0x01970377, + 0x00190287, 0x00190028, 0x00000028, + }; + + writel(RZG3S_PCI_PERM_PIPE_PHY_REG_EN, host->axi + RZG3S_PCI_PERM); + + for (u8 i =3D 0; i < RZG3S_PCI_PHY_XCFGD_NUM; i++) + writel(xcfgd_settings[i], host->axi + RZG3S_PCI_PHY_XCFGD(i)); + + for (u8 i =3D 0; i < RZG3S_PCI_PHY_XCFGA_CMN_NUM; i++) { + writel(xcfga_cmn_settings[i], + host->axi + RZG3S_PCI_PHY_XCFGA_CMN(i)); + } + + for (u8 i =3D 0; i < RZG3S_PCI_PHY_XCFGA_RX_NUM; i++) { + writel(xcfga_rx_settings[i], + host->axi + RZG3S_PCI_PHY_XCFGA_RX(i)); + } + + writel(0x107, host->axi + RZG3S_PCI_PHY_XCFGA_TX); + + /* Select PHY settings values */ + writel(RZG3S_PCI_PHY_XCFG_CTRL_PHYREG_SEL, + host->axi + RZG3S_PCI_PHY_XCFG_CTRL); + + writel(0, host->axi + RZG3S_PCI_PERM); + + return 0; +} + +static void rzg3s_pcie_pm_runtime_put(void *data) +{ + pm_runtime_put_sync(data); +} + +static void rzg3s_pcie_sysc_signal_action(void *data) +{ + struct regmap *sysc =3D data; + + /* + * SYSC RST_RSM_B signal need to be asserted before turning off the + * power to the PHY. + */ + regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, + RZG3S_SYS_PCIE_RST_RSM_B_MASK, + FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); +} + +static int +rzg3s_pcie_host_setup(struct rzg3s_pcie_host *host, + int (*intx_setup)(struct rzg3s_pcie_host *host), + int (*msi_setup)(struct rzg3s_pcie_host *host), + bool probe) +{ + struct device *dev =3D host->dev; + int ret; + + /* Set inbound windows */ + ret =3D rzg3s_pcie_parse_map_dma_ranges(host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set inbound windows!\n"); + + /* Set outbound windows */ + ret =3D rzg3s_pcie_parse_map_ranges(host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set outbound windows!\n"); + + /* Set the PHY, if any */ + if (host->data->init_phy) { + ret =3D host->data->init_phy(host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to set the PHY!\n"); + } + + if (intx_setup) { + ret =3D intx_setup(host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup INTx\n"); + + if (probe) { + ret =3D devm_add_action_or_reset(dev, + rzg3s_pcie_intx_teardown, + host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to add INTx action\n"); + } + } + + /* Set the MSIs */ + if (IS_ENABLED(CONFIG_PCI_MSI)) { + ret =3D msi_setup(host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to setup MSIs\n"); + + if (probe) { + ret =3D devm_add_action_or_reset(dev, + rzg3s_pcie_msi_teardown, + host); + if (ret) + return dev_err_probe(dev, ret, + "Failed to add MSI action\n"); + } + } + + /* Initialize the host */ + ret =3D rzg3s_pcie_host_init(host, probe); + if (ret) + return dev_err_probe(dev, ret, + "Failed to initialize the HW!\n"); + + /* Try to set maximum supported link speed */ + ret =3D rzg3s_pcie_set_max_link_speed(host); + if (ret) + dev_info(dev, "Failed to set max link speed\n"); + + return 0; +} + +static void rzg3s_pcie_host_remove_action(void *data) +{ + struct rzg3s_pcie_host *host =3D data; + struct pci_host_bridge *bridge =3D pci_host_bridge_from_priv(host); + + pci_lock_rescan_remove(); + pci_stop_root_bus(bridge->bus); + pci_remove_root_bus(bridge->bus); + pci_unlock_rescan_remove(); +} + +static int rzg3s_pcie_probe(struct platform_device *pdev) +{ + struct pci_host_bridge *bridge; + struct device *dev =3D &pdev->dev; + struct device_node *np =3D dev->of_node; + struct device_node *sysc_np __free(device_node) =3D + of_parse_phandle(np, "renesas,sysc", 0); + struct rzg3s_pcie_host *host; + int ret; + + bridge =3D devm_pci_alloc_host_bridge(dev, sizeof(*host)); + if (!bridge) + return -ENOMEM; + + host =3D pci_host_bridge_priv(bridge); + host->dev =3D dev; + host->data =3D device_get_match_data(dev); + platform_set_drvdata(pdev, host); + + host->axi =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(host->axi)) + return PTR_ERR(host->axi); + host->pcie =3D host->axi + RZG3S_PCI_CFG_BASE; + + ret =3D of_property_read_u32(np, "vendor-id", &host->vendor_id); + if (ret) + return ret; + + ret =3D of_property_read_u32(np, "device-id", &host->device_id); + if (ret) + return ret; + + host->sysc =3D syscon_node_to_regmap(sysc_np); + if (IS_ERR(host->sysc)) + return PTR_ERR(host->sysc); + + ret =3D regmap_update_bits(host->sysc, RZG3S_SYS_PCIE_RST_RSM_B, + RZG3S_SYS_PCIE_RST_RSM_B_MASK, + FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, rzg3s_pcie_sysc_signal_action, + host->sysc); + if (ret) + return ret; + + ret =3D rzg3s_pcie_resets_prepare(host); + if (ret) + return ret; + + ret =3D devm_pm_runtime_enable(dev); + if (ret) + return ret; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + return ret; + + ret =3D devm_add_action_or_reset(dev, rzg3s_pcie_pm_runtime_put, dev); + if (ret) + return ret; + + raw_spin_lock_init(&host->hw_lock); + + ret =3D rzg3s_pcie_host_setup(host, rzg3s_pcie_intx_setup, + rzg3s_pcie_msi_enable, true); + if (ret) + return ret; + + bridge->sysdata =3D host; + bridge->ops =3D &rzg3s_pcie_root_ops; + bridge->child_ops =3D &rzg3s_pcie_child_ops; + ret =3D pci_host_probe(bridge); + if (ret) + return ret; + + return devm_add_action_or_reset(dev, rzg3s_pcie_host_remove_action, + host); +} + +static int rzg3s_pcie_suspend_noirq(struct device *dev) +{ + struct rzg3s_pcie_host *host =3D dev_get_drvdata(dev); + const struct rzg3s_pcie_soc_data *data =3D host->data; + struct regmap *sysc =3D host->sysc; + int ret; + + ret =3D pm_runtime_put_sync(dev); + if (ret) + return ret; + + ret =3D reset_control_bulk_assert(data->num_power_resets, + host->power_resets); + if (ret) + goto rpm_restore; + + ret =3D reset_control_bulk_assert(data->num_cfg_resets, + host->cfg_resets); + if (ret) + goto power_resets_restore; + + ret =3D regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, + RZG3S_SYS_PCIE_RST_RSM_B_MASK, + FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); + if (ret) + goto cfg_resets_restore; + + return 0; + + /* Restore the previous state if any error happens */ +cfg_resets_restore: + reset_control_bulk_deassert(data->num_cfg_resets, + host->cfg_resets); +power_resets_restore: + reset_control_bulk_deassert(data->num_power_resets, + host->power_resets); +rpm_restore: + pm_runtime_resume_and_get(dev); + return ret; +} + +static int rzg3s_pcie_resume_noirq(struct device *dev) +{ + struct rzg3s_pcie_host *host =3D dev_get_drvdata(dev); + const struct rzg3s_pcie_soc_data *data =3D host->data; + struct regmap *sysc =3D host->sysc; + int ret; + + ret =3D regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, + RZG3S_SYS_PCIE_RST_RSM_B_MASK, + FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 1)); + if (ret) + return ret; + + /* + * According to the RZ/G3S HW manual (Rev.1.10, section + * 34.5.1.2 De-asserting the Reset) the PCIe IP needs to wait 5ms from + * power on to the de-assertion of reset. + */ + usleep_range(5000, 5100); + ret =3D reset_control_bulk_deassert(data->num_power_resets, + host->power_resets); + if (ret) + goto assert_rst_rsm_b; + + ret =3D pm_runtime_resume_and_get(dev); + if (ret) + goto assert_power_resets; + + ret =3D rzg3s_pcie_host_setup(host, NULL, rzg3s_pcie_msi_hw_setup, false); + if (ret) + goto rpm_put; + + return 0; + + /* + * If any error happens there is no way to recover the IP. Put it in the + * lowest possible power state. + */ +rpm_put: + pm_runtime_put_sync(dev); +assert_power_resets: + reset_control_bulk_assert(data->num_power_resets, + host->power_resets); +assert_rst_rsm_b: + regmap_update_bits(sysc, RZG3S_SYS_PCIE_RST_RSM_B, + RZG3S_SYS_PCIE_RST_RSM_B_MASK, + FIELD_PREP(RZG3S_SYS_PCIE_RST_RSM_B_MASK, 0)); + return ret; +} + +static const struct dev_pm_ops rzg3s_pcie_pm_ops =3D { + NOIRQ_SYSTEM_SLEEP_PM_OPS(rzg3s_pcie_suspend_noirq, + rzg3s_pcie_resume_noirq) +}; + +const char * const rzg3s_soc_power_resets[] =3D { + "aresetn", "rst_cfg_b", "rst_load_b", +}; + +const char * const rzg3s_soc_cfg_resets[] =3D { + "rst_b", "rst_ps_b", "rst_gp_b", "rst_rsm_b", +}; + +static const struct rzg3s_pcie_soc_data rzg3s_soc_data =3D { + .power_resets =3D rzg3s_soc_power_resets, + .num_power_resets =3D ARRAY_SIZE(rzg3s_soc_power_resets), + .cfg_resets =3D rzg3s_soc_cfg_resets, + .num_cfg_resets =3D ARRAY_SIZE(rzg3s_soc_cfg_resets), + .init_phy =3D rzg3s_soc_pcie_init_phy, +}; + +static const struct of_device_id rzg3s_pcie_of_match[] =3D { + { + .compatible =3D "renesas,r9a08g045s33-pcie", + .data =3D &rzg3s_soc_data, + }, + {}, +}; + +static struct platform_driver rzg3s_pcie_driver =3D { + .driver =3D { + .name =3D "rzg3s-pcie-host", + .of_match_table =3D rzg3s_pcie_of_match, + .pm =3D pm_ptr(&rzg3s_pcie_pm_ops), + }, + .probe =3D rzg3s_pcie_probe, +}; +module_platform_driver(rzg3s_pcie_driver); + +MODULE_DESCRIPTION("Renesas RZ/G3S PCIe host driver"); +MODULE_AUTHOR("Claudiu Beznea "); +MODULE_LICENSE("GPL"); --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0C08F22D781 for ; Fri, 30 May 2025 11:19:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603998; cv=none; b=RNdRz/YXx20kMKPY+0id2L7jtudL7PnuN+b34E/rhZWIhWVkguuoXwCsvCYU0fDmMYF2ttEaiE5hnQDa/d6Ruco2O7NKa1w1FF2n/PyGeiceYYS8DmA9wLaQ3BMamTiWOBRTuGllmE/EM2TpRGiA3r/Lw3HJhcGR5vqb7ZVTGAA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748603998; c=relaxed/simple; bh=X7hDuCiTVWY384OgAlrGLr/jCTONBQsk3r94ENDyK3g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=HnzApovzMttijluXVgzVfiIS1qHljgii8pQ5jA8+EnTwE513miBVgSQO52Sdn4B/7+1NQffIdJ8eBC0UqxOFWT2mEOTGNoluhSB8LcyMY4xYN5FumWvBIWfNXk0RV7gnmL2Usk6DOsbH3at9xUIzzbJvGvwgYqrrwjdfLxyyWSI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=mJNmTFZ1; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="mJNmTFZ1" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-4508287895dso16874665e9.1 for ; Fri, 30 May 2025 04:19:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603994; x=1749208794; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=EpG/I/+BWWmS26h5n6JKq19fnTLhLa0YbFAXx8ak2yk=; b=mJNmTFZ1xtp1hPDAQD0Nf/Xqe+nrwHACGsuTYOCBrTmIv2txwv2zwjHZj4UEWyPcSt HnhxL2u6Se9pNKSGM20AmliBhJ9xDEdxge+KLGe4RNPT8VZZXVffEfT9ZYbxJg98guTt QMto7zY8dtX/DWsV0HndOKu3XrZZffkXnI8VzZs9NGvmrX1DsKf8HTfGY/zbRy/dMALQ 77bGvR74ctizJM/KUyye7R6Jf+xG/N7XRfWJ+o9zXxxjfNJu4D6ep3uWR+XcPni2tCGR wa72+mWiTILq4Z8ueHUivA9hxqxOR8VkTB6pV0sbuTWJuOGMS37OVkvrFp4YoWUc8LtT XCfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603994; x=1749208794; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=EpG/I/+BWWmS26h5n6JKq19fnTLhLa0YbFAXx8ak2yk=; b=Uoeuxo0t1ULE7LubkYeStL2vG7zoBm96TP9kseAPmYMYoLVrkvDm4Gi3V2p471c7Pe sOWR2rHhymBNCqTu0vcnMhqWa/EzW4lGO4BqG43Q9UkdtnrD0gG9n94bj9n7nAILtXme 8VcFh0gDTURchl3wSZYvCwMi4LQAKT8O8rYkSvhf3bdEDzXFEvYl5Z4Jek57K+A8qOxW 4Q+KdDjAbXkSA3MbLiyoIk9pQ6yiNQCPn1ZkKtO0JSz4wTqfFeaTkovnU91faP211B6d KNSoCkn14FkrYmQXHHXkasP2s7lvnx3s0PRGZIdYrlxKVMsuYDuGcnNY4OHwvG9KzzjQ Wzkg== X-Forwarded-Encrypted: i=1; AJvYcCUqP09ZQlBDuz/f9bleeu6Zfmsj5aeNCIfHKQ7bbqh2DuQtEiUfjTFykI9soNKJ78cH/njHp+R7emon8GQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzaWpMflOxlo1XKaVEd7ewfO9SIIfj36EzWT9NFS9iUQKh/e05E pCwUg5K94CH5c56STlDVy6yaBF4nxJNMT4Rn5hLKJnBXLJpDDSjeJE7JMltZ2teVdqk= X-Gm-Gg: ASbGncsqBc/s8ZrRHSdfWeHLQRLcBPosdwLfzg6AeFp3pgNLD0NKqQ/6aocRaOocZVk VsyBrrjeBTYBkPytpCGiP0Fx8+ZCgSmOeDS9P5w84AElNUhlgUeEfY4yuJd1IPvlGANF2vl8Ne+ HLB4PHDJqfuHZ6A+ZfmWx8oOlHtGNXOTvzdG5adhlCLBidZRv885OmB35i231a6Fvynb0ceDexz 7laGEcQu/Z3oDwKRueIb8XCcpo0bMQLaJyTza1w88PFZsuNL4tJsCoGcaR5gNsYJjdVT0QXXAFM XfL/Fk6HuQPMnuaFZZBR25FTnFvJw5zqbB46jscZL4MbQPk3mDLeay1qzK3bIhdqmW7JW242sbH TsI4Z3auUVT+GTqqC X-Google-Smtp-Source: AGHT+IGUJg33COSzG5y9e9bhXP7pOmJUOM67MeQYRzNHWMgUFeu2KrzZLuJQfaLbp9n6mkOJwkwhzA== X-Received: by 2002:a05:600c:9a3:b0:441:bbe5:f562 with SMTP id 5b1f17b1804b1-450ce897d17mr44809275e9.16.1748603994306; Fri, 30 May 2025 04:19:54 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:53 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 5/8] arm64: dts: renesas: r9a08g045s33: Add PCIe node Date: Fri, 30 May 2025 14:19:14 +0300 Message-ID: <20250530111917.1495023-6-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ/G3S SoC has a variant (R9A08G045S33) which support PCIe. Add the PCIe node. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - updated the dma-ranges to reflect the SoC capability; added a comment about it. - updated clock-names, interrupt names - dropped legacy-interrupt-controller node - added interrupt-controller property - moved renesas,sysc at the end of the node to comply with DT coding style arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi | 60 +++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi b/arch/arm64/boo= t/dts/renesas/r9a08g045s33.dtsi index 3351f26c7a2a..f1d642c70436 100644 --- a/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi +++ b/arch/arm64/boot/dts/renesas/r9a08g045s33.dtsi @@ -12,3 +12,63 @@ / { compatible =3D "renesas,r9a08g045s33", "renesas,r9a08g045"; }; + +&soc { + pcie: pcie@11e40000 { + compatible =3D "renesas,r9a08g045s33-pcie"; + reg =3D <0 0x11e40000 0 0x10000>; + ranges =3D <0x03000000 0 0x30000000 0 0x30000000 0 0x8000000>; + /* Map all possible DRAM ranges (4 GB). */ + dma-ranges =3D <0x42000000 0 0x40000000 0 0x40000000 0x1 0x0>; + bus-range =3D <0x0 0xff>; + clocks =3D <&cpg CPG_MOD R9A08G045_PCI_ACLK>, + <&cpg CPG_MOD R9A08G045_PCI_CLKL1PM>; + clock-names =3D "aclk", "pm"; + resets =3D <&cpg R9A08G045_PCI_ARESETN>, + <&cpg R9A08G045_PCI_RST_B>, + <&cpg R9A08G045_PCI_RST_GP_B>, + <&cpg R9A08G045_PCI_RST_PS_B>, + <&cpg R9A08G045_PCI_RST_RSM_B>, + <&cpg R9A08G045_PCI_RST_CFG_B>, + <&cpg R9A08G045_PCI_RST_LOAD_B>; + reset-names =3D "aresetn", "rst_b", "rst_gp_b", "rst_ps_b", + "rst_rsm_b", "rst_cfg_b", "rst_load_b"; + interrupts =3D , + , + , + , + , + , + , + , + , + , + , + , + , + , + , + ; + interrupt-names =3D "serr", "serr_cor", "serr_nonfatal", + "serr_fatal", "axi_err", "inta", + "intb", "intc", "intd", "msi", + "link_bandwidth", "pm_pme", "dma", + "pcie_evt", "msg", "all"; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-map-mask =3D <0 0 0 7>; + interrupt-map =3D <0 0 0 1 &pcie 0 0 0 0>, /* INT A */ + <0 0 0 2 &pcie 0 0 0 1>, /* INT B */ + <0 0 0 3 &pcie 0 0 0 2>, /* INT C */ + <0 0 0 4 &pcie 0 0 0 3>; /* INT D */ + device_type =3D "pci"; + num-lanes =3D <1>; + #address-cells =3D <3>; + #size-cells =3D <2>; + power-domains =3D <&cpg>; + vendor-id =3D <0x1912>; + device-id =3D <0x0033>; + renesas,sysc =3D <&sysc>; + status =3D "disabled"; + }; +}; --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 119E622D9F3 for ; Fri, 30 May 2025 11:19:57 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.53 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748604000; cv=none; b=SHzMBOShW20VkH9DMXFR5DDTXayMBKfxj6VBUZvSqAA+TwGorTv1Abe0tL5RMgTLSIxOj5/rbqhR58ERZj5DHr4n44bqgqsg4uu6p9xVYQxQhPkdB8ALdwmTA/OjFNjuKePsqem/pdysRlW9zq/J+l3cdblWYBT7GHZo+/n6RNI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748604000; c=relaxed/simple; bh=JTrdaAZ1ROVl7a1oj4t3COHx+ERflhdGhlJk2YHh1O4=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=CU4M6TMf9GoQP0F0/aRTrchvNkbtpf0VcuoNEeaElYCVFNdzOAXqzIskzSW7aAlObI5BIOBdju05dtsZqRUDo/YFZiMxU694Td93MazcRxZz2KhJO0qxmolWERF+fX0P77cDq1zybeD9Fvjgz9RJBiKXF9Bw98GO1xxmNGy+92Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=BnpTPMmc; arc=none smtp.client-ip=209.85.128.53 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="BnpTPMmc" Received: by mail-wm1-f53.google.com with SMTP id 5b1f17b1804b1-450ce3a2dd5so15890955e9.3 for ; Fri, 30 May 2025 04:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603996; x=1749208796; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HrSNXGfd1043Q08w0S469+QeaCD1uDQKPuIZl5ROhFI=; b=BnpTPMmcuog4O0CSnJ+ayesc1LGoZfog+M5zTi/2AgahLxrysziU5F25UhpD2fcB5h gW7ClGnXI+2yMo7W/zo5idxb2t3Dhwo/Ewm9ZjbpaDHFWem1fVsu6xaT3wazo15N5UAf QOtFchKf1u08qipINvqXT+mp9o/+7SWzSahM5mL9+hrh8efxzK3xVRvshbGKhbICNRm+ TzGcpoz/Yx4jZVIYvggBwlhdtnZcXvf6c/CDKJwhXnNWrC2ZKGpLXkOBiNl5qNYO47+L Fd2m3O7Mt72zcZ00fxG4XSv5ID5UEd0Z7ExR5Fw1jfUYdMYJBtlYsztgHdGAej5RbzbJ RCrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603996; x=1749208796; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HrSNXGfd1043Q08w0S469+QeaCD1uDQKPuIZl5ROhFI=; b=YSulrLUrZeTJnPKrzNjX9U1guGvX8/QmKlx5Y+V4bG6/U6OO+ORkAsnL9OWhL+aABR PO7j7YUUwcNR2T2RybX3vaX97A3ObdBxkWeKHjzfffuvHoUmWvA5OlaZt0nEJoIVJ5Mz 4MeYHIoXfgZ3r2A9ASzN1/zcLU8xGI2paYqu0BsyIW0gTxIguGg6mbavCQwcakc4WHVI L16w+UO5IGmXNJqgmtq+w2rNiFt8pgrPfqfNn05eTxQQFROayzcWwWmDIlEoFW+/ZzZW YZDdWkTUPDaUMZmNWEKIGBEUmrM6wZKVClGuSiCtatRE6UcWM3/rc66lMWBWL1yVsiV9 W+fg== X-Forwarded-Encrypted: i=1; AJvYcCUn2oP5PWvYRkY7QyVaFCXTwdQQdVuPP/HeIXnOFkKtweu68AtFT0Jb6X9SxXd3SZD2Srj5hxLKFZ8nXDI=@vger.kernel.org X-Gm-Message-State: AOJu0YwtdZv1qDe9YFGvbdQZalXvhpL4UnTpL0NitZyoMEh1qD3towMa /zkZKOsZJzofJFk9/vrP6DWQnwd0xQ06taMuAV6s4ObFJjuiEHovJgVnj+XQdtHXhfU= X-Gm-Gg: ASbGnctDb79v1Gg2DCz4uhGKBxT8c81If91Ythh7ZWP4b/QKp1ncwu5+c0mEOlFHr28 DtXURK4cRHaKl30/VOEPUg2SKk98Qp7dj5xnN4hmG3JtW8lGArBTV/9X5KLHBtE1VKxpetbHFAh q73fWvH1JpoejunHWg29R5AO0e8boDX2f2khfEWulAaNLU+M6SkhYq3Rpo/usXJMr3xJUWVlI5B oitZx/oUWiaDQpzdtrcpNbUL5oFWf811g5cleaZDMc+RLxkk9ezBhwtsvTEWr0du1VvJuYZ4YMq f+GLWRmHab7ksnf8dcJVEox1zxBxFHx58qCimMEAD8zDjNyXCf7+VNY1o2VNmdrBYp4jWFPj8lL ultzC4Q== X-Google-Smtp-Source: AGHT+IEOmvfgxDBSjQyjTAsEbb9y2Sc2/DFcebPrTV7oNj2NnWeeNPPvSc2ZCRmRQYNSn7XQ7be7vg== X-Received: by 2002:a05:600c:354b:b0:442:f44f:654 with SMTP id 5b1f17b1804b1-450d656016fmr22662535e9.33.1748603996269; Fri, 30 May 2025 04:19:56 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:55 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 6/8] arm64: dts: renesas: rzg3s-smarc-som: Update dma-ranges for PCIe Date: Fri, 30 May 2025 14:19:15 +0300 Message-ID: <20250530111917.1495023-7-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The first 128MB of memory is reserved on this board for secure area. Update the PCIe dma-ranges property to reflect this. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - none, this patch is new arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi b/arch/arm64/= boot/dts/renesas/rzg3s-smarc-som.dtsi index 39845faec894..1b03820a6f02 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc-som.dtsi @@ -214,6 +214,11 @@ &sdhi2 { }; #endif =20 +&pcie { + /* First 128MB is reserved for secure area. */ + dma-ranges =3D <0x42000000 0 0x48000000 0 0x48000000 0x0 0x38000000>; +}; + &pinctrl { #if SW_CONFIG3 =3D=3D SW_ON eth0-phy-irq-hog { --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C009B22DA02 for ; Fri, 30 May 2025 11:19:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748604001; cv=none; b=LYU5lFwfaXUMMm7P3YaZxmrH90PzQZwGzNpPh7GnUvX+ziYKvmqJAX7FE+sc3FTLsq532C+s6YIJBa6/OnNSkY9ft+iiFjXTHF5z+G76l4i7+eV/qrRaDZXCvaoSoMCclBBaIG8G2Rg/URiHet4WanlGN9RjuHxpMWjV0ZX5Cuo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748604001; c=relaxed/simple; bh=cJm/K+5ybBRW7zIlcZTsIL5CDJmvxF4XRCkMKcNx2xg=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sepR08O+WilemmxNehv/OXdTupAEU/vRHERu3Km+Fp7BSL2WURwNBMsN49QgBE0LePfLKuIP7KGeQCvOlHwv8fl2K1cyBdB5N4PFghIWtlqDFEFH96YNpfhYPrn2t6C7cgQLN1hdwh0mdGKf0kiPUqNQOVG3ZzfPiJwaslWtkGE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=c1qOAHoZ; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="c1qOAHoZ" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-441c99459e9so12417735e9.3 for ; Fri, 30 May 2025 04:19:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748603998; x=1749208798; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=cvGP/3CRa2t4gXiy9Fv9ps8S84kk+BXASAtnC9F87rA=; b=c1qOAHoZOali2+86hu4/HQqGYiUOBvUVfixgoNaMCPswQA1v/JRhBa6S5OcrnWAOnk sReqUrPuC/e/CJg/i7YmqrkSrA5EbILVgatmfypS2pop+Ei2vVrj7Jm5lGqD69V21iVR oBwaMNDMUOa+6aiaW2eJhdNj6X6DMzkeAe/zkJO0FWGu0tWGvK0WMitc+ELducFYHjDw +l73YQwXHH15JKDMbpE99E9XpRAvT83YyjDTByycnt8L02fUrstuvxs+RXuTZnh9OPIJ iEP3MXMgDzwgp95W3waajw9LtPSVUdeShAbuo6K7yetj0E/vwaky40S1Mo5BPtJQVrCw GryA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748603998; x=1749208798; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=cvGP/3CRa2t4gXiy9Fv9ps8S84kk+BXASAtnC9F87rA=; b=Bu3LYYyyMqRaDfiDiIzJPInAOFs4QHdnHku+NjzULp+ZgP1VS4LL3EFC4Fr+JFZZyl yaY91Bpnv1umkL0h8fK41h88jY9icdESFDeuiWx7bh95HQvJ4pc1jXaqEAbDsox8rIl+ vu+Sqs/geO5M8/EX0KllHX5oEgDtKzRqCW3N/LzVqXtXUx5jhscevlxaXLGWUFRLVrcO +NibUynPejaOUxS7Mhj4seB5eloAXdxCBLsXerbNEb+/9ui0gu+uXherIGLFpqnvWIZR g3tWqcZ18izyllpF/hksRNvtwet+GgH/9fx3YIvnm93u7DtJGPZyF1rcBdUZHz8yiuAE agEQ== X-Forwarded-Encrypted: i=1; AJvYcCXiTNI/PTy26H/UQQ4B3MvbKZ0aK36JzuFcqvoOrtoK87S4vltoROF6Wrg0H40Ac8K4lwcgqVHXPAvQlAw=@vger.kernel.org X-Gm-Message-State: AOJu0YwTHPssac/Txj0QPEHX7b/C4YL3AtzQkMrjEHxW6gidf02qYyUH 1Fe317BEaYu9j9Lek0j8kV73DM/mt3rnchj7PggjpjtirxS9mPxMNbCkNiRYXVDvU1Y= X-Gm-Gg: ASbGncvCnkTyJN5yJSQ3Qmb/dKpqKejUbtWvTnipWVNiThF1ZS+mAGTpEFfA0Yr4X1r QK+EkHupwcG7/R/BX74XvjeyJurWhXTKuh0m2Po9I11bLMeBi3ER3f8JvX4du187g9zHqc5tAuR 1Ug11MxIWpUjsJ2uJP+S7NGBBvCTxQ7UCEKzJ3fD02xe0MijsDGr3ufHkJuljPd/P8G95wJ55au lCxguzjMMkWpyAEpDZsNTN6ucZ2/sS4j+cjGt4XnmSGKdf8Rzzw64GRkT8nb74f70y8v1z58H4t I2xLLgOEBlxFqR4thIIzWxm5g/YdARlx1urZDSx3wFZCB22h8aHOEHiVbr41fTLQyQyrP7enOGd vERr3Yw== X-Google-Smtp-Source: AGHT+IGxApXe/sZJcFH1MLc5rJG+X9SmRJKeviScP7B6tRgI49wzs/sJ62PD40lFB7+X06xl6Ik4Pg== X-Received: by 2002:a05:600c:3582:b0:43c:fbba:41ba with SMTP id 5b1f17b1804b1-450d655b02amr21460665e9.28.1748603998156; Fri, 30 May 2025 04:19:58 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:57 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 7/8] arm64: dts: renesas: rzg3s-smarc: Enable PCIe Date: Fri, 30 May 2025 14:19:16 +0300 Message-ID: <20250530111917.1495023-8-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea The RZ Smarc Carrier-II board has PCIe headers mounted on it. Enable PCIe support. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - none arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi b/arch/arm64/boot= /dts/renesas/rzg3s-smarc.dtsi index 5e044a4d0234..6e9e78aca0b0 100644 --- a/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi +++ b/arch/arm64/boot/dts/renesas/rzg3s-smarc.dtsi @@ -132,6 +132,12 @@ power-monitor@44 { }; }; =20 +&pcie { + pinctrl-0 =3D <&pcie_pins>; + pinctrl-names =3D "default"; + status =3D "okay"; +}; + &pinctrl { audio_clock_pins: audio-clock { pins =3D "AUDIO_CLK1", "AUDIO_CLK2"; @@ -159,6 +165,11 @@ key-3-gpio-hog { line-name =3D "key-3-gpio-irq"; }; =20 + pcie_pins: pcie { + pinmux =3D , /* PCIE_RST_OUT_B */ + ; /* PCIE_CLKREQ_B */ + }; + scif0_pins: scif0 { pinmux =3D , /* RXD */ ; /* TXD */ --=20 2.43.0 From nobody Tue Dec 16 22:33:35 2025 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 701ED22DFB6 for ; Fri, 30 May 2025 11:20:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748604004; cv=none; b=gpMnyFG36e2/tM1VRb22HKjExH3t6uNz1RID7NttMlUDMK2S03TRH0EaKNBLjGVaAqU99x35EKO6UPFQUV5OSlKWz0Jpk12CCbNfYGxFz1XLCifvw6Vx0pvVl1rbvdXk8QmVJW6p1EjdPJbXvcOklAiiTapjXdy35a5dfdTdE5U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748604004; c=relaxed/simple; bh=PrFWTreIuoDsO+2dJtLRS+p9byMc23RZOKSzUzdjGdw=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nt6FO8/0xU+PXEJWQWYbIYwLT60wimKZ/GDCzHXJg7DkTRw2ZIBkSUzNTrs8Re5m3JSn+NueB7VIPx3cRzJPYS6RSjABspLVLUVA0hjp7MtTnP+IQtXDvbO3cq1weEk9vj4MBSuaO4LZ01cAKeF5elmMqMxfM82ACqgVz+ob+LI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev; spf=pass smtp.mailfrom=tuxon.dev; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b=GOVGmP3u; arc=none smtp.client-ip=209.85.128.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=tuxon.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=tuxon.dev header.i=@tuxon.dev header.b="GOVGmP3u" Received: by mail-wm1-f50.google.com with SMTP id 5b1f17b1804b1-441c99459e9so12417895e9.3 for ; Fri, 30 May 2025 04:20:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=tuxon.dev; s=google; t=1748604001; x=1749208801; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=gBGOjaATHiERWGlVICubjqS+hAYT10Q+U69oOw2FjwA=; b=GOVGmP3uTCvTkrkGmlk9XlPB7Zcc930lljqJSrcMoFR7ic1xGAqzYavWil06zi2mGv 1+znsfSXNcU7BJdpSyWPzNlI3zsvNGfqfG1egeCbwtHmYcUwu/fIeK31Ua4pX19r0pSt GzYMBTdtRApDw9syaQcsooIxlWBOkrDJbutynG5UPmggQYjozAcfe8SMm70h1BvwLXm8 Mf59w+tm6ZvJ53Uup/gg++/9hs1t9eiq3JbqC6FB2OM8OwSQK4YQKCAgWLVwaeCbNsoV MYvPkFsUMMzBYUFxtkeJvqK1afXhptMDP8zwwSr1WW+9ufSbd+O+EiLGeIx0D7ayGauD 7Gbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748604001; x=1749208801; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=gBGOjaATHiERWGlVICubjqS+hAYT10Q+U69oOw2FjwA=; b=AYuFZ+h2djgfrAGyeLp924asfHZ9fBFWsXHlklo+bYmMmnrcZOnffMoFu6sO4fXgH4 xQMz/rOV3wtqIII1QUg/8urq6zMiSandc1yKQb8Om1GHMPYyg9dzcL+GfcCcWFEtkdaG tJrlhKdzzhZxdWFFtRgCfH8sTqnlYVijkx8Q5g6qMhOZA45qkv9eb1/0AyZG+Ze9uQqO rAid1Ibr30tQwajI3MwH/bvvt0YikjE5yQNUkGq7gbNsocuXJKToDIJ5FU5DHsK3BtV7 YBvQqxYPYc2K49yPrELZXry3swGnk7GPQ/TI7CGeTcdOTFUdGyV+buskrZ0NzY6zfHf6 3aKg== X-Forwarded-Encrypted: i=1; AJvYcCWf6QXFcpzO3Fydtjsoaltx6wqbqbd9sJ/zbYZ/eoPJC6K28Afk43oNQF4u8lwwUG5StEsYowWW7kXq1IM=@vger.kernel.org X-Gm-Message-State: AOJu0YzEA6qU4micXJWfblNjE2pdDpI0MrzQdLdAjJOvOc9hfWmmnmAG umlOFfWZ5GtZfgLtAlENoDjp1ognNs/m3vdx+hH0C3F2iAe+uOVqILdbK6n8k91KHNg= X-Gm-Gg: ASbGncuaj1REyX3Ifj4MNAYHfaICCFUDn9WDnim8VPiDL8fNLbm7lkYNo+l8BYSypUT GdrMRWEfYQLEuDX+9XIdyBVdhf86nGGWoXkb2QFejJN9G30lMWz7MwI2Rrwe001g67cXU1cspo8 UPo1T9RFp0gH+Q5dLgbPQyWFFXsg/K6iSFKe3YBYy3KOgC1uMVIm8PA7zVskrxnQIO9IcFhYmYe 2du4j231h9I5molUsM1GazrFKFKjfjIx1u7D3Ia7pzBQ0OiQMTL8kLiAxrrDa16lF5JsRVm57+X 2r3c1FGFzshr/IpS9L3RfdtBsWjlpkuAFgu0h4ZmVDkUPR0h8VeAXb1yBCxAoOawlUeWGRFQAVU 47dlGSQ== X-Google-Smtp-Source: AGHT+IFOnZeDzHLcJzr2XiB1V8TCQqZ4gnYI0oqjqw7IlK2qZ/Smc3vbO5ZYPTsUQejGYt+DG3ev/Q== X-Received: by 2002:a05:600c:1d99:b0:442:d9fc:7de with SMTP id 5b1f17b1804b1-450d6546354mr24484345e9.22.1748604000826; Fri, 30 May 2025 04:20:00 -0700 (PDT) Received: from claudiu-X670E-Pro-RS.. ([82.78.167.126]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450dc818f27sm3986435e9.18.2025.05.30.04.19.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 30 May 2025 04:19:59 -0700 (PDT) From: Claudiu X-Google-Original-From: Claudiu To: bhelgaas@google.com, lpieralisi@kernel.org, kw@linux.com, manivannan.sadhasivam@linaro.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, geert+renesas@glider.be, magnus.damm@gmail.com, mturquette@baylibre.com, sboyd@kernel.org, p.zabel@pengutronix.de Cc: claudiu.beznea@tuxon.dev, linux-pci@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-clk@vger.kernel.org, john.madieu.xa@bp.renesas.com, Claudiu Beznea Subject: [PATCH v2 8/8] arm64: defconfig: Enable PCIe for the Renesas RZ/G3S SoC Date: Fri, 30 May 2025 14:19:17 +0300 Message-ID: <20250530111917.1495023-9-claudiu.beznea.uj@bp.renesas.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> References: <20250530111917.1495023-1-claudiu.beznea.uj@bp.renesas.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Claudiu Beznea Enable PCIe for the Renesas RZ/G3S SoC. Signed-off-by: Claudiu Beznea Tested-by: Wolfram Sang --- Changes in v2: - none arch/arm64/configs/defconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 897fc686e6a9..3274d14421d4 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -226,6 +226,7 @@ CONFIG_PCIE_MEDIATEK_GEN3=3Dm CONFIG_PCI_TEGRA=3Dy CONFIG_PCIE_RCAR_HOST=3Dy CONFIG_PCIE_RCAR_EP=3Dy +CONFIG_PCIE_RENESAS_RZG3S_HOST=3Dm CONFIG_PCIE_ROCKCHIP_HOST=3Dm CONFIG_PCI_XGENE=3Dy CONFIG_PCI_IMX6_HOST=3Dy --=20 2.43.0