From nobody Thu Dec 18 14:29:03 2025 Received: from szxga04-in.huawei.com (szxga04-in.huawei.com [45.249.212.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 959D72222A0 for ; Fri, 30 May 2025 10:03:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=45.249.212.190 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748599422; cv=none; b=BrUVfba+pCICd+iEnrCkkGdhFIn+FlMvK38XsvWz/6BqfUOwxX1QY9eSlFkuQjZjOxpE+tQKYfLJhfcvTDhjVKEuZ4NN9MGdEIl3ASWf5wgSBRpNtwLPMOrw1+2sQ33eBT23xUC+8j2xCMWsUNzsvNuQKFBxoPLl5FrEaBsWbsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748599422; c=relaxed/simple; bh=8Dds+AW4wKXW0QoNFVJzCxEfXvXy5FdAF5wXO8RoNDg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=sDksy8w6gz7V7rE3pTwiNJGProDReDC68HPCa2UCTvqX86tEywdQyia0ZLyXq2pb2lZ0ikbJyu0YOzhP9pbihVGzeN40y6MwGteR3nuZWvJvuJ7qQlG6V88epwXENKagouqvkeRElJsOcQUKH5BxqAVV70FaCe1ohUfS5VlOr34= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com; spf=pass smtp.mailfrom=huawei.com; arc=none smtp.client-ip=45.249.212.190 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=huawei.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=huawei.com Received: from mail.maildlp.com (unknown [172.19.162.112]) by szxga04-in.huawei.com (SkyGuard) with ESMTP id 4b7zLd5ygzz2TSL4; Fri, 30 May 2025 18:02:33 +0800 (CST) Received: from dggemv705-chm.china.huawei.com (unknown [10.3.19.32]) by mail.maildlp.com (Postfix) with ESMTPS id BFB8E1401E9; Fri, 30 May 2025 18:03:37 +0800 (CST) Received: from kwepemq100007.china.huawei.com (7.202.195.175) by dggemv705-chm.china.huawei.com (10.3.19.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 30 May 2025 18:03:37 +0800 Received: from localhost.huawei.com (10.169.71.169) by kwepemq100007.china.huawei.com (7.202.195.175) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.11; Fri, 30 May 2025 18:03:37 +0800 From: Yongbang Shi To: , , , , , , , CC: , , , , , , , , , Subject: [PATCH drm-dp 05/10] drm/hisilicon/hibmc: fix rare monitors cannot display problem Date: Fri, 30 May 2025 17:54:27 +0800 Message-ID: <20250530095432.1206966-6-shiyongbang@huawei.com> X-Mailer: git-send-email 2.33.0 In-Reply-To: <20250530095432.1206966-1-shiyongbang@huawei.com> References: <20250530095432.1206966-1-shiyongbang@huawei.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: kwepems100002.china.huawei.com (7.221.188.206) To kwepemq100007.china.huawei.com (7.202.195.175) Content-Type: text/plain; charset="utf-8" From: Baihan Li DP Link training successful at 8.1Gbps with some monitors' max link rate are 2.7Gbps. So change the default 8.1Gbps link rate to the rate that reads from devices' capabilities. Fixes: f9698f802e50 ("drm/hisilicon/hibmc: Restructuring the header dp_reg.= h") Signed-off-by: Baihan Li --- drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h | 4 ++- drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c | 6 +--- drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c | 33 +++++++++++++------ .../gpu/drm/hisilicon/hibmc/dp/dp_serdes.c | 12 ------- 4 files changed, 27 insertions(+), 28 deletions(-) diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_comm.h index 4add05c7f161..18a961466ff0 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_comm.h @@ -25,6 +25,9 @@ struct hibmc_link_status { struct hibmc_link_cap { u8 link_rate; u8 lanes; + int rx_dpcd_revision; + bool is_tps3; + bool is_tps4; }; =20 struct hibmc_dp_link { @@ -62,7 +65,6 @@ struct hibmc_dp_dev { =20 void hibmc_dp_aux_init(struct hibmc_dp *dp); int hibmc_dp_link_training(struct hibmc_dp_dev *dp); -int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp); int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp_dev *dp); int hibmc_dp_serdes_set_tx_cfg(struct hibmc_dp_dev *dp, u8 train_set[HIBMC= _DP_LANE_NUM_MAX]); =20 diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c b/drivers/gpu/drm/h= isilicon/hibmc/dp/dp_hw.c index 8f0daec7d174..ee0b543afd7f 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_hw.c @@ -154,7 +154,6 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) { struct drm_device *drm_dev =3D dp->drm_dev; struct hibmc_dp_dev *dp_dev; - int ret; =20 dp_dev =3D devm_kzalloc(drm_dev->dev, sizeof(struct hibmc_dp_dev), GFP_KE= RNEL); if (!dp_dev) @@ -166,13 +165,10 @@ int hibmc_dp_hw_init(struct hibmc_dp *dp) =20 dp_dev->dev =3D drm_dev; dp_dev->base =3D dp->mmio + HIBMC_DP_OFFSET; + dp_dev->serdes_base =3D dp_dev->base + HIBMC_DP_HOST_OFFSET; =20 hibmc_dp_aux_init(dp); =20 - ret =3D hibmc_dp_serdes_init(dp_dev); - if (ret) - return ret; - dp_dev->link.cap.lanes =3D 0x2; dp_dev->link.cap.link_rate =3D DP_LINK_BW_8_1; =20 diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c b/drivers/gpu/drm= /hisilicon/hibmc/dp/dp_link.c index 74f7832ea53e..6c69fa2ae9cf 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_link.c @@ -39,6 +39,14 @@ static int hibmc_dp_link_training_configure(struct hibmc= _dp_dev *dp) /* enhanced frame */ hibmc_dp_reg_write_field(dp, HIBMC_DP_VIDEO_CTRL, HIBMC_DP_CFG_STREAM_FRA= ME_MODE, 0x1); =20 + ret =3D hibmc_dp_get_serdes_rate_cfg(dp); + if (ret < 0) + return ret; + + ret =3D hibmc_dp_serdes_rate_switch(ret, dp); + if (ret) + return ret; + /* set rate and lane count */ buf[0] =3D dp->link.cap.link_rate; buf[1] =3D DP_LANE_COUNT_ENHANCED_FRAME_EN | dp->link.cap.lanes; @@ -325,6 +333,20 @@ static int hibmc_dp_link_downgrade_training_eq(struct = hibmc_dp_dev *dp) return hibmc_dp_link_reduce_rate(dp); } =20 +static void hibmc_dp_update_caps(struct hibmc_dp_dev *dp) +{ + dp->link.cap.rx_dpcd_revision =3D dp->dpcd[DP_DPCD_REV]; + + dp->link.cap.is_tps3 =3D (dp->dpcd[DP_DPCD_REV] >=3D DP_DPCD_REV_13) && + (dp->dpcd[DP_MAX_LANE_COUNT] & DP_TPS3_SUPPORTED); + dp->link.cap.is_tps4 =3D (dp->dpcd[DP_DPCD_REV] >=3D DP_DPCD_REV_14) && + (dp->dpcd[DP_MAX_DOWNSPREAD] & DP_TPS4_SUPPORTED); + dp->link.cap.link_rate =3D dp->dpcd[DP_MAX_LINK_RATE]; + dp->link.cap.lanes =3D dp->dpcd[DP_MAX_LANE_COUNT] & DP_MAX_LANE_COUNT_MA= SK; + if (dp->link.cap.lanes > HIBMC_DP_LANE_NUM_MAX) + dp->link.cap.lanes =3D HIBMC_DP_LANE_NUM_MAX; +} + int hibmc_dp_link_training(struct hibmc_dp_dev *dp) { struct hibmc_dp_link *link =3D &dp->link; @@ -334,16 +356,7 @@ int hibmc_dp_link_training(struct hibmc_dp_dev *dp) if (ret) drm_err(dp->dev, "dp aux read dpcd failed, ret: %d\n", ret); =20 - dp->link.cap.link_rate =3D dp->dpcd[DP_MAX_LINK_RATE]; - dp->link.cap.lanes =3D 0x2; - - ret =3D hibmc_dp_get_serdes_rate_cfg(dp); - if (ret < 0) - return ret; - - ret =3D hibmc_dp_serdes_rate_switch(ret, dp); - if (ret) - return ret; + hibmc_dp_update_caps(dp); =20 while (true) { ret =3D hibmc_dp_link_training_cr_pre(dp); diff --git a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c b/drivers/gpu/d= rm/hisilicon/hibmc/dp/dp_serdes.c index 676059d4c1e6..8191233aa965 100644 --- a/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c +++ b/drivers/gpu/drm/hisilicon/hibmc/dp/dp_serdes.c @@ -57,15 +57,3 @@ int hibmc_dp_serdes_rate_switch(u8 rate, struct hibmc_dp= _dev *dp) =20 return 0; } - -int hibmc_dp_serdes_init(struct hibmc_dp_dev *dp) -{ - dp->serdes_base =3D dp->base + HIBMC_DP_HOST_OFFSET; - - writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0), - dp->serdes_base + HIBMC_DP_PMA_LANE0_OFFSET); - writel(FIELD_PREP(HIBMC_DP_PMA_TXDEEMPH, DP_SERDES_VOL0_PRE0), - dp->serdes_base + HIBMC_DP_PMA_LANE1_OFFSET); - - return hibmc_dp_serdes_rate_switch(DP_SERDES_BW_8_1, dp); -} --=20 2.33.0