From nobody Wed Feb 11 03:41:54 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 9DB551DF72C for ; Fri, 30 May 2025 09:04:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748595879; cv=none; b=pqYZSe1jrTiefpC0Py8dW2pdzPz0lg6pIr1pgvrsdpkUZCsRPUzugtDuDkg9XEaK6mMRb/ZXSno26Ak3VSyNOYBQygStGd9+7J/boOcWVRz+/FGDlTO0cRpOD5nqIPL92MMCLwhfyrUTKEJNyxaOgSwLVf1spcWp9RH9iBP5tR0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748595879; c=relaxed/simple; bh=lisLegOy+6lXxdxDg5/m1b7CL468MwUWemew7FNpzIQ=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=WtQyhlUBkuVXXdn3PINgkbelfkQp5gAKJnAqWN+l/N5oTPCPC7ty/a/eTc6T72Cyj2j1iRNV3qap0TspvxWRD//jUv2MTCjkSC5lAZ/Um6xZI7Du6JFvhjYWv0io07gt/ZspoqUrBHvocUxUszD9AGx9kBJFwS7f3olqIdcfozQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 919E116F8; Fri, 30 May 2025 02:04:20 -0700 (PDT) Received: from MacBook-Pro.blr.arm.com (unknown [10.164.18.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id F3C603F5A1; Fri, 30 May 2025 02:04:31 -0700 (PDT) From: Dev Jain To: akpm@linux-foundation.org, david@redhat.com, catalin.marinas@arm.com, will@kernel.org Cc: lorenzo.stoakes@oracle.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, linux-mm@kvack.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, steven.price@arm.com, gshan@redhat.com, linux-arm-kernel@lists.infradead.org, Dev Jain Subject: [PATCH 1/3] mm: Allow pagewalk without locks Date: Fri, 30 May 2025 14:34:05 +0530 Message-Id: <20250530090407.19237-2-dev.jain@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250530090407.19237-1-dev.jain@arm.com> References: <20250530090407.19237-1-dev.jain@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" It is noted at [1] that KFENCE can manipulate kernel pgtable entries during softirqs. It does this by calling set_memory_valid() -> __change_memory_com= mon(). This being a non-sleepable context, we cannot take the init_mm mmap lock. Therefore, add PGWALK_NOLOCK to enable walk_page_range_novma() usage without locks. [1] https://lore.kernel.org/linux-arm-kernel/89d0ad18-4772-4d8f-ae8a-7c48d2= 6a927e@arm.com/ Signed-off-by: Dev Jain --- include/linux/pagewalk.h | 2 ++ mm/pagewalk.c | 12 ++++++++---- 2 files changed, 10 insertions(+), 4 deletions(-) diff --git a/include/linux/pagewalk.h b/include/linux/pagewalk.h index 9700a29f8afb..9bc8853ed3de 100644 --- a/include/linux/pagewalk.h +++ b/include/linux/pagewalk.h @@ -14,6 +14,8 @@ enum page_walk_lock { PGWALK_WRLOCK =3D 1, /* vma is expected to be already write-locked during the walk */ PGWALK_WRLOCK_VERIFY =3D 2, + /* no lock is needed */ + PGWALK_NOLOCK =3D 3, }; =20 /** diff --git a/mm/pagewalk.c b/mm/pagewalk.c index e478777c86e1..9657cf4664b2 100644 --- a/mm/pagewalk.c +++ b/mm/pagewalk.c @@ -440,6 +440,8 @@ static inline void process_vma_walk_lock(struct vm_area= _struct *vma, case PGWALK_RDLOCK: /* PGWALK_RDLOCK is handled by process_mm_walk_lock */ break; + default: + break; } #endif } @@ -640,10 +642,12 @@ int walk_page_range_novma(struct mm_struct *mm, unsig= ned long start, * specified address range from being freed. The caller should take * other actions to prevent this race. */ - if (mm =3D=3D &init_mm) - mmap_assert_locked(walk.mm); - else - mmap_assert_write_locked(walk.mm); + if (ops->walk_lock !=3D PGWALK_NOLOCK) { + if (mm =3D=3D &init_mm) + mmap_assert_locked(walk.mm); + else + mmap_assert_write_locked(walk.mm); + } =20 return walk_pgd_range(start, end, &walk); } --=20 2.30.2 From nobody Wed Feb 11 03:41:54 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 5C7571EA7C8 for ; Fri, 30 May 2025 09:04:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748595885; cv=none; b=GZsGN48hHRZIk6y6gdnl2KSIWqvK8ieUbpfHINT4gAedHWPj1upibNvyN8hdG4jkBUiqyMiQC/UKMuJKOxs/GfyFVDQmGfPRv0I9S0R3TWvmumuUpjBiVirbWNAfLiGit6pMt1KoEeuFAohT7PQoI0B32x14tCj02tLJs1GlWCU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748595885; c=relaxed/simple; bh=6i4rPvsVO9h/V46TCoPoAC/yg8N1XCm+jf/47OrvZJI=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=fZA6xd7okBsBH76+aznHVjPtSM8EZ2g/WmIJVlxuzeI7F0IL1MEGic2pFCnNVUDS9QpciTeFIwiuBFIKtSVCfLGUQBYyuNLNlgO2AuYKntNf/M0bMcwUL04/5c2g5Xf312XmlEWrkdJxf9n86KTNmKl2/yLKX2YDoDMC0V89170= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3CDAC16F2; Fri, 30 May 2025 02:04:26 -0700 (PDT) Received: from MacBook-Pro.blr.arm.com (unknown [10.164.18.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 9ED583F5A1; Fri, 30 May 2025 02:04:37 -0700 (PDT) From: Dev Jain To: akpm@linux-foundation.org, david@redhat.com, catalin.marinas@arm.com, will@kernel.org Cc: lorenzo.stoakes@oracle.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, linux-mm@kvack.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, steven.price@arm.com, gshan@redhat.com, linux-arm-kernel@lists.infradead.org, Dev Jain Subject: [PATCH 2/3] arm64: pageattr: Use walk_page_range_novma() to change memory permissions Date: Fri, 30 May 2025 14:34:06 +0530 Message-Id: <20250530090407.19237-3-dev.jain@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250530090407.19237-1-dev.jain@arm.com> References: <20250530090407.19237-1-dev.jain@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Move away from apply_to_page_range(), which does not honour leaf mappings, to walk_page_range_novma(). The callbacks emit a warning and return EINVAL if a partial range is detected. Signed-off-by: Dev Jain --- arch/arm64/mm/pageattr.c | 69 +++++++++++++++++++++++++++++++++++++--- 1 file changed, 64 insertions(+), 5 deletions(-) diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index 39fd1f7ff02a..a5c829c64969 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -8,6 +8,7 @@ #include #include #include +#include =20 #include #include @@ -20,6 +21,67 @@ struct page_change_data { pgprot_t clear_mask; }; =20 +static pteval_t set_pageattr_masks(unsigned long val, struct mm_walk *walk) +{ + struct page_change_data *masks =3D walk->private; + unsigned long new_val =3D val; + + new_val &=3D ~(pgprot_val(masks->clear_mask)); + new_val |=3D (pgprot_val(masks->set_mask)); + + return new_val; +} + +static int pageattr_pud_entry(pud_t *pud, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pud_t val =3D pudp_get(pud); + + if (pud_leaf(val)) { + if (WARN_ON_ONCE((next - addr) !=3D PUD_SIZE)) + return -EINVAL; + val =3D __pud(set_pageattr_masks(pud_val(val), walk)); + set_pud(pud, val); + walk->action =3D ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pmd_entry(pmd_t *pmd, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pmd_t val =3D pmdp_get(pmd); + + if (pmd_leaf(val)) { + if (WARN_ON_ONCE((next - addr) !=3D PMD_SIZE)) + return -EINVAL; + val =3D __pmd(set_pageattr_masks(pmd_val(val), walk)); + set_pmd(pmd, val); + walk->action =3D ACTION_CONTINUE; + } + + return 0; +} + +static int pageattr_pte_entry(pte_t *pte, unsigned long addr, + unsigned long next, struct mm_walk *walk) +{ + pte_t val =3D ptep_get(pte); + + val =3D __pte(set_pageattr_masks(pte_val(val), walk)); + set_pte(pte, val); + + return 0; +} + +static const struct mm_walk_ops pageattr_ops =3D { + .pud_entry =3D pageattr_pud_entry, + .pmd_entry =3D pageattr_pmd_entry, + .pte_entry =3D pageattr_pte_entry, + .walk_lock =3D PGWALK_NOLOCK, +}; + bool rodata_full __ro_after_init =3D IS_ENABLED(CONFIG_RODATA_FULL_DEFAULT= _ENABLED); =20 bool can_set_direct_map(void) @@ -49,9 +111,6 @@ static int change_page_range(pte_t *ptep, unsigned long = addr, void *data) return 0; } =20 -/* - * This function assumes that the range is mapped with PAGE_SIZE pages. - */ static int __change_memory_common(unsigned long start, unsigned long size, pgprot_t set_mask, pgprot_t clear_mask) { @@ -61,8 +120,8 @@ static int __change_memory_common(unsigned long start, u= nsigned long size, data.set_mask =3D set_mask; data.clear_mask =3D clear_mask; =20 - ret =3D apply_to_page_range(&init_mm, start, size, change_page_range, - &data); + ret =3D walk_page_range_novma(&init_mm, start, start + size, + &pageattr_ops, NULL, &data); =20 /* * If the memory is being made valid without changing any other bits --=20 2.30.2 From nobody Wed Feb 11 03:41:54 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id F33291EA7C8 for ; Fri, 30 May 2025 09:04:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748595890; 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Fri, 30 May 2025 02:04:31 -0700 (PDT) Received: from MacBook-Pro.blr.arm.com (unknown [10.164.18.49]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 4A0CF3F5A1; Fri, 30 May 2025 02:04:43 -0700 (PDT) From: Dev Jain To: akpm@linux-foundation.org, david@redhat.com, catalin.marinas@arm.com, will@kernel.org Cc: lorenzo.stoakes@oracle.com, Liam.Howlett@oracle.com, vbabka@suse.cz, rppt@kernel.org, surenb@google.com, mhocko@suse.com, linux-mm@kvack.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, steven.price@arm.com, gshan@redhat.com, linux-arm-kernel@lists.infradead.org, Dev Jain Subject: [PATCH 3/3] mm/pagewalk: Add pre/post_pte_table callback for lazy MMU on arm64 Date: Fri, 30 May 2025 14:34:07 +0530 Message-Id: <20250530090407.19237-4-dev.jain@arm.com> X-Mailer: git-send-email 2.39.3 (Apple Git-146) In-Reply-To: <20250530090407.19237-1-dev.jain@arm.com> References: <20250530090407.19237-1-dev.jain@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" arm64 implements lazy_mmu_mode to allow deferral and batching of barriers when updating kernel PTEs, which provides a nice performance boost. arm64 currently uses apply_to_page_range() to modify kernel PTE permissions, which runs inside lazy_mmu_mode. So to prevent a performance regression, let's add hooks to walk_page_range_novma() to allow continued use of lazy_mmu_mode. Signed-off-by: Dev Jain --- Credits to Ryan for the patch description. arch/arm64/mm/pageattr.c | 12 ++++++++++++ include/linux/pagewalk.h | 2 ++ mm/pagewalk.c | 6 ++++++ 3 files changed, 20 insertions(+) diff --git a/arch/arm64/mm/pageattr.c b/arch/arm64/mm/pageattr.c index a5c829c64969..9163324b12a0 100644 --- a/arch/arm64/mm/pageattr.c +++ b/arch/arm64/mm/pageattr.c @@ -75,11 +75,23 @@ static int pageattr_pte_entry(pte_t *pte, unsigned long= addr, return 0; } =20 +static void pte_lazy_mmu_enter(void) +{ + arch_enter_lazy_mmu_mode(); +} + +static void pte_lazy_mmu_leave(void) +{ + arch_leave_lazy_mmu_mode(); +} + static const struct mm_walk_ops pageattr_ops =3D { .pud_entry =3D pageattr_pud_entry, .pmd_entry =3D pageattr_pmd_entry, .pte_entry =3D pageattr_pte_entry, .walk_lock =3D PGWALK_NOLOCK, + .pre_pte_table =3D pte_lazy_mmu_enter, + .post_pte_table =3D pte_lazy_mmu_leave, }; =20 bool rodata_full __ro_after_init =3D IS_ENABLED(CONFIG_RODATA_FULL_DEFAULT= _ENABLED); diff --git a/include/linux/pagewalk.h b/include/linux/pagewalk.h index 9bc8853ed3de..2157d345974c 100644 --- a/include/linux/pagewalk.h +++ b/include/linux/pagewalk.h @@ -88,6 +88,8 @@ struct mm_walk_ops { int (*pre_vma)(unsigned long start, unsigned long end, struct mm_walk *walk); void (*post_vma)(struct mm_walk *walk); + void (*pre_pte_table)(void); + void (*post_pte_table)(void); int (*install_pte)(unsigned long addr, unsigned long next, pte_t *ptep, struct mm_walk *walk); enum page_walk_lock walk_lock; diff --git a/mm/pagewalk.c b/mm/pagewalk.c index 9657cf4664b2..a441f5cbbc45 100644 --- a/mm/pagewalk.c +++ b/mm/pagewalk.c @@ -33,6 +33,9 @@ static int walk_pte_range_inner(pte_t *pte, unsigned long= addr, const struct mm_walk_ops *ops =3D walk->ops; int err =3D 0; =20 + if (walk->ops->pre_pte_table) + walk->ops->pre_pte_table(); + for (;;) { if (ops->install_pte && pte_none(ptep_get(pte))) { pte_t new_pte; @@ -56,6 +59,9 @@ static int walk_pte_range_inner(pte_t *pte, unsigned long= addr, addr +=3D PAGE_SIZE; pte++; } + + if (walk->ops->post_pte_table) + walk->ops->post_pte_table(); return err; } =20 --=20 2.30.2