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Fri, 30 May 2025 13:21:55 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLsZS011716 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:54 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:48 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:54 +0530 Subject: [PATCH v5 09/18] clk: qcom: camcc-sm8450: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-9-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-GUID: s7n72FdsgcjlvmS0cRIcVj5E_BIBBGqn X-Proofpoint-ORIG-GUID: s7n72FdsgcjlvmS0cRIcVj5E_BIBBGqn X-Authority-Analysis: v=2.4 cv=X8pSKHTe c=1 sm=1 tr=0 ts=6839b0f3 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=jl1wNc9uYJxH2fZ-HckA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX4xP9ndfZOF0H uyW4Cy2bBTFR9TG2cH60tb20UkZ0MmwvxMZC3C3AKt+xU5vstc6ioF7xXOQO/5pfjmk2PXxIZo0 xqci4iyqim9PP9a4kgjvlIHyyPWyMTTpuL+Yi6c5Vf5n+sLc8OI7BYsLunh2wyCH8kBvKFDpnqK 9pLcht6aG8bnqy8QTx3V0ts4BH89S/+n0j9IRPcgZResF+wkuMfcPJAnk5DbAdIjk7omqwfn19l A4deE8HTuyR/dALkKJsm92gDOA3Pj2xab5tCl7X4q5mcvQ06enneKRQBi6EfXfGyGkUhMHeSFKo HUd8EjjbGPOteBYwFIbl3/Q2VIGZH9EgGxdEvuq2PDbwpvuiVSKLsQ063es240xyhN+QRM5sQ2F hn90ux9o/hKR1T6389byvv+oB6VnqFV+A50HZuATi8KP4CZ3dFMCUajjBIZqTuBjrCojTMfL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Camera PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enable critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. This change also removes the modelling for cam_cc_gdsc_clk and keeps it always ON from probe since using CLK_IS_CRITICAL will prevent the clock controller associated power domains from collapsing due to clock framework invoking clk_pm_runtime_get() during prepare. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-sm8450.c | 89 ++++++++++++++++++++-----------------= ---- 1 file changed, 44 insertions(+), 45 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8450.c b/drivers/clk/qcom/camcc-sm845= 0.c index 08982737e4901c0703e19f8dd2d302e24748210c..4dd8be8cc9881c890d2e7c3a12f= 12816a9ab47dc 100644 --- a/drivers/clk/qcom/camcc-sm8450.c +++ b/drivers/clk/qcom/camcc-sm8450.c @@ -86,6 +86,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll0_c= onfig =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -191,6 +192,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll1= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -257,6 +259,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll2= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D rivian_evo_vco, .num_vco =3D ARRAY_SIZE(rivian_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -296,6 +299,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll3= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -368,6 +372,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll4= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -440,6 +445,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll5= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -512,6 +518,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll6= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -584,6 +591,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll7= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll7 =3D { .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -656,6 +664,7 @@ static const struct alpha_pll_config sm8475_cam_cc_pll8= _config =3D { =20 static struct clk_alpha_pll cam_cc_pll8 =3D { .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -1476,24 +1485,6 @@ static struct clk_rcg2 cam_cc_xo_clk_src =3D { }, }; =20 -static struct clk_branch cam_cc_gdsc_clk =3D { - .halt_reg =3D 0x1320c, - .halt_check =3D BRANCH_HALT, - .clkr =3D { - .enable_reg =3D 0x1320c, - .enable_mask =3D BIT(0), - .hw.init =3D &(const struct clk_init_data) { - .name =3D "cam_cc_gdsc_clk", - .parent_hws =3D (const struct clk_hw*[]) { - &cam_cc_xo_clk_src.clkr.hw, - }, - .num_parents =3D 1, - .flags =3D CLK_IS_CRITICAL | CLK_SET_RATE_PARENT, - .ops =3D &clk_branch2_ops, - }, - }, -}; - static struct clk_branch cam_cc_bps_ahb_clk =3D { .halt_reg =3D 0x1004c, .halt_check =3D BRANCH_HALT, @@ -2819,7 +2810,6 @@ static struct clk_regmap *cam_cc_sm8450_clocks[] =3D { [CAM_CC_CSIPHY4_CLK] =3D &cam_cc_csiphy4_clk.clkr, [CAM_CC_CSIPHY5_CLK] =3D &cam_cc_csiphy5_clk.clkr, [CAM_CC_FAST_AHB_CLK_SRC] =3D &cam_cc_fast_ahb_clk_src.clkr, - [CAM_CC_GDSC_CLK] =3D &cam_cc_gdsc_clk.clkr, [CAM_CC_ICP_AHB_CLK] =3D &cam_cc_icp_ahb_clk.clkr, [CAM_CC_ICP_CLK] =3D &cam_cc_icp_clk.clkr, [CAM_CC_ICP_CLK_SRC] =3D &cam_cc_icp_clk_src.clkr, @@ -2913,6 +2903,22 @@ static const struct qcom_reset_map cam_cc_sm8450_res= ets[] =3D { [CAM_CC_SFE_1_BCR] =3D { 0x13094 }, }; =20 +static struct clk_alpha_pll *cam_cc_sm8450_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, + &cam_cc_pll8, +}; + +static u32 cam_cc_sm8450_critical_cbcrs[] =3D { + 0x1320c, /* CAM_CC_GDSC_CLK */ +}; + static const struct regmap_config cam_cc_sm8450_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -3021,6 +3027,13 @@ static struct gdsc *cam_cc_sm8450_gdscs[] =3D { [TITAN_TOP_GDSC] =3D &titan_top_gdsc, }; =20 +static struct qcom_cc_driver_data cam_cc_sm8450_driver_data =3D { + .alpha_plls =3D cam_cc_sm8450_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sm8450_plls), + .clk_cbcrs =3D cam_cc_sm8450_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sm8450_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sm8450_desc =3D { .config =3D &cam_cc_sm8450_regmap_config, .clks =3D cam_cc_sm8450_clocks, @@ -3029,6 +3042,8 @@ static const struct qcom_cc_desc cam_cc_sm8450_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sm8450_resets), .gdscs =3D cam_cc_sm8450_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sm8450_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sm8450_driver_data, }; =20 static const struct of_device_id cam_cc_sm8450_match_table[] =3D { @@ -3040,12 +3055,6 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8450_match_table); =20 static int cam_cc_sm8450_probe(struct platform_device *pdev) { - struct regmap *regmap; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sm8450_desc); - if (IS_ERR(regmap)) - return PTR_ERR(regmap); - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-camcc")) { /* Update CAMCC PLL0 */ cam_cc_pll0.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; @@ -3092,28 +3101,18 @@ static int cam_cc_sm8450_probe(struct platform_devi= ce *pdev) cam_cc_pll8_out_even.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCI= D_OLE]; cam_cc_pll8_out_even.clkr.hw.init =3D &sm8475_cam_cc_pll8_out_even_init; =20 - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &sm8475_cam_cc_pll0_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &sm8475_cam_cc_pll1_co= nfig); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &sm8475_cam_cc_pll2_c= onfig); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &sm8475_cam_cc_pll3_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &sm8475_cam_cc_pll4_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &sm8475_cam_cc_pll5_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &sm8475_cam_cc_pll6_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &sm8475_cam_cc_pll7_co= nfig); - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &sm8475_cam_cc_pll8_co= nfig); - } else { - clk_lucid_evo_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_evo_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_evo_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_evo_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_evo_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_lucid_evo_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - clk_lucid_evo_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); - clk_lucid_evo_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); + cam_cc_pll0.config =3D &sm8475_cam_cc_pll0_config; + cam_cc_pll1.config =3D &sm8475_cam_cc_pll1_config; + cam_cc_pll2.config =3D &sm8475_cam_cc_pll2_config; + cam_cc_pll3.config =3D &sm8475_cam_cc_pll3_config; + cam_cc_pll4.config =3D &sm8475_cam_cc_pll4_config; + cam_cc_pll5.config =3D &sm8475_cam_cc_pll5_config; + cam_cc_pll6.config =3D &sm8475_cam_cc_pll6_config; + cam_cc_pll7.config =3D &sm8475_cam_cc_pll7_config; + cam_cc_pll8.config =3D &sm8475_cam_cc_pll8_config; } =20 - return qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8450_desc, regmap); + return qcom_cc_probe(pdev, &cam_cc_sm8450_desc); } =20 static struct platform_driver cam_cc_sm8450_driver =3D { --=20 2.34.1