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Fri, 30 May 2025 13:21:43 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA04.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDLgNJ031517 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:21:42 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:21:36 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:52 +0530 Subject: [PATCH v5 07/18] clk: qcom: videocc-sm8450: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-7-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Dmitry Baryshkov , Konrad Dybcio X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Authority-Analysis: v=2.4 cv=GIgIEvNK c=1 sm=1 tr=0 ts=6839b0e7 cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=NSTayzwvANHeSgS_AzkA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-ORIG-GUID: 2DKNznYdobWalRaP7BtO1k5458HRrwLw X-Proofpoint-GUID: 2DKNznYdobWalRaP7BtO1k5458HRrwLw X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfXzACy2aBDJJFU lG/kH0pZNaAEMCNPZiXWuheXOP7CXI6us5YZvVmtLdtPZyLtriimN9k4NGd70irTZ2EHIK0PWqr SHQPBlDqquTzWGUwx7aKVe6+Qg3z7swTt/8MsoGJPmbrXeLyURBJ4yZfNa73jIZvtvK+dspFZds GSBx9EeWD6yOqKbXmryWFHRFW2jYrRvPe3XRSam/SCBdsumLN4U/d86LqsuG5jkGgqaEb2e+fF0 OxvhrYcLN/fYJr6KLSKHldYcavfD4+KYa1g+ZjWaVKAfbq4InX+0b01XJfbJE7jsHCunz4vs5+I e3VUzKDcIFLRiylqe936EXc6CCbaiBLZLwzAj7yUIBNGgwgnzVwhGNSEq/nBoPP14Y281DzMgNu Pd2HeKuOjHQjXvA8Pk9Tlj3vHOfF+4+JcjCIgnpK6ZmJrBh5HPPEDRs4M8+19JA4iUyXk4LP X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 malwarescore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 adultscore=0 priorityscore=1501 mlxscore=0 phishscore=0 spamscore=0 suspectscore=0 mlxlogscore=999 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Video PLLs on SM8450/SM8475 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enable critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Signed-off-by: Jagadeesh Kona --- drivers/clk/qcom/videocc-sm8450.c | 58 +++++++++++++++++------------------= ---- 1 file changed, 25 insertions(+), 33 deletions(-) diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-s= m8450.c index 2e11dcffb6646d47b298c27ef68635a465dd728e..d53182f001262324d8f54b0c6a5= e73541eb32190 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -63,6 +62,7 @@ static const struct alpha_pll_config sm8475_video_cc_pll0= _config =3D { =20 static struct clk_alpha_pll video_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &video_cc_pll0_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -106,6 +106,7 @@ static const struct alpha_pll_config sm8475_video_cc_pl= l1_config =3D { =20 static struct clk_alpha_pll video_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &video_cc_pll1_config, .vco_table =3D lucid_evo_vco, .num_vco =3D ARRAY_SIZE(lucid_evo_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_EVO], @@ -407,6 +408,17 @@ static const struct qcom_reset_map video_cc_sm8450_res= ets[] =3D { [VIDEO_CC_MVS1C_CLK_ARES] =3D { .reg =3D 0x808c, .bit =3D 2, .udelay =3D = 1000 }, }; =20 +static struct clk_alpha_pll *video_cc_sm8450_plls[] =3D { + &video_cc_pll0, + &video_cc_pll1, +}; + +static u32 video_cc_sm8450_critical_cbcrs[] =3D { + 0x80e4, /* VIDEO_CC_AHB_CLK */ + 0x8114, /* VIDEO_CC_XO_CLK */ + 0x8130, /* VIDEO_CC_SLEEP_CLK */ +}; + static const struct regmap_config video_cc_sm8450_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -415,6 +427,13 @@ static const struct regmap_config video_cc_sm8450_regm= ap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data video_cc_sm8450_driver_data =3D { + .alpha_plls =3D video_cc_sm8450_plls, + .num_alpha_plls =3D ARRAY_SIZE(video_cc_sm8450_plls), + .clk_cbcrs =3D video_cc_sm8450_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(video_cc_sm8450_critical_cbcrs), +}; + static const struct qcom_cc_desc video_cc_sm8450_desc =3D { .config =3D &video_cc_sm8450_regmap_config, .clks =3D video_cc_sm8450_clocks, @@ -423,6 +442,8 @@ static const struct qcom_cc_desc video_cc_sm8450_desc = =3D { .num_resets =3D ARRAY_SIZE(video_cc_sm8450_resets), .gdscs =3D video_cc_sm8450_gdscs, .num_gdscs =3D ARRAY_SIZE(video_cc_sm8450_gdscs), + .use_rpm =3D true, + .driver_data =3D &video_cc_sm8450_driver_data, }; =20 static const struct of_device_id video_cc_sm8450_match_table[] =3D { @@ -434,23 +455,6 @@ MODULE_DEVICE_TABLE(of, video_cc_sm8450_match_table); =20 static int video_cc_sm8450_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &video_cc_sm8450_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8475-videocc")) { /* Update VideoCC PLL0 */ video_cc_pll0.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; @@ -458,23 +462,11 @@ static int video_cc_sm8450_probe(struct platform_devi= ce *pdev) /* Update VideoCC PLL1 */ video_cc_pll1.regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE]; =20 - clk_lucid_ole_pll_configure(&video_cc_pll0, regmap, &sm8475_video_cc_pll= 0_config); - clk_lucid_ole_pll_configure(&video_cc_pll1, regmap, &sm8475_video_cc_pll= 1_config); - } else { - clk_lucid_evo_pll_configure(&video_cc_pll0, regmap, &video_cc_pll0_confi= g); - clk_lucid_evo_pll_configure(&video_cc_pll1, regmap, &video_cc_pll1_confi= g); + video_cc_pll0.config =3D &sm8475_video_cc_pll0_config; + video_cc_pll1.config =3D &sm8475_video_cc_pll1_config; } =20 - /* Keep some clocks always-on */ - qcom_branch_set_clk_en(regmap, 0x80e4); /* VIDEO_CC_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0x8130); /* VIDEO_CC_SLEEP_CLK */ - qcom_branch_set_clk_en(regmap, 0x8114); /* VIDEO_CC_XO_CLK */ - - ret =3D qcom_cc_really_probe(&pdev->dev, &video_cc_sm8450_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; + return qcom_cc_probe(pdev, &video_cc_sm8450_desc); } =20 static struct platform_driver video_cc_sm8450_driver =3D { --=20 2.34.1