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Fri, 30 May 2025 13:22:07 +0000 (GMT) Received: from nalasex01a.na.qualcomm.com (nalasex01a.na.qualcomm.com [10.47.209.196]) by NALASPPMTA02.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UDM60E015866 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 13:22:06 GMT Received: from [10.213.98.28] (10.80.80.8) by nalasex01a.na.qualcomm.com (10.47.209.196) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 06:22:00 -0700 From: Jagadeesh Kona Date: Fri, 30 May 2025 18:50:56 +0530 Subject: [PATCH v5 11/18] clk: qcom: camcc-sm8650: Move PLL & clk configuration to really probe Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-videocc-pll-multi-pd-voting-v5-11-02303b3a582d@quicinc.com> References: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> In-Reply-To: <20250530-videocc-pll-multi-pd-voting-v5-0-02303b3a582d@quicinc.com> To: Bjorn Andersson , Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Konrad Dybcio , "Vladimir Zapolskiy" , Dmitry Baryshkov CC: Ajit Pandey , Imran Shaik , Taniya Das , "Satya Priya Kakitapalli" , , , , , Krzysztof Kozlowski , Jagadeesh Kona , Bryan O'Donoghue , Konrad Dybcio , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-ClientProxiedBy: nasanex01a.na.qualcomm.com (10.52.223.231) To nalasex01a.na.qualcomm.com (10.47.209.196) X-QCInternal: smtphost X-Proofpoint-Virus-Version: vendor=nai engine=6200 definitions=5800 signatures=585085 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTMwMDExNiBTYWx0ZWRfX4BvRZ7KXu2Vz uYwlLf/y1g61sylWWytQJdeyQoA/9bP5rDFCB33Ey3b7+KBI54bdqneY3OP49tWbjoQf3FFTaVb m3IGJRUDsYCAqqjA0JLZ3J8ww0rN/YMblsHCy7gYwGSQGTKSi+qUqtBQ5Tu8le9MeNyaNA5YUxh V4uxxrpuDzHZEK9qA3vcQhA2Rd6dDfFzE3QV8F+v4E/qTBsHpWMkoCWT+j55nVwXWeQ1IahvXC1 +WEmgxqjV5w2O8FDSgqk484ElvIRmXVnZkpIrEvuOl/VULyxq3PsTEQRlJrWZCjq3oNXvZMHoZf 7GK8/s8qcZhz6IQlBYKKsrSQiFMo6WoeM2P/H8tR+5ncsijp6W0e65bf+R8AHSahTXofbz4UjKx wN0FvmifxvlXRGAKGM+QnWmkGOmhDwOWYcfcPrSfDqzz2QGGleClRw2mC718BlSJtivyjHRd X-Authority-Analysis: v=2.4 cv=EfHIQOmC c=1 sm=1 tr=0 ts=6839b0ff cx=c_pps a=ouPCqIW2jiPt+lZRy3xVPw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=GEpy-HfZoHoA:10 a=IkcTkHD0fZMA:10 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=COk6AnOGAAAA:8 a=s2paB303WvPZy8Ug-xUA:9 a=QEXdDO2ut3YA:10 a=TjNXssC_j7lpFel5tvFf:22 X-Proofpoint-GUID: B1InAR2O-SzLFYvP3UvP4Tza0VPVol-0 X-Proofpoint-ORIG-GUID: B1InAR2O-SzLFYvP3UvP4Tza0VPVol-0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-30_05,2025-05-30_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 adultscore=0 spamscore=0 lowpriorityscore=0 suspectscore=0 clxscore=1015 bulkscore=0 mlxlogscore=999 mlxscore=0 malwarescore=0 priorityscore=1501 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505300116 Camera PLLs on SM8650 require both MMCX and MXC rails to be kept ON to configure the PLLs properly. Hence move runtime power management, PLL configuration and enabling critical clocks to qcom_cc_really_probe() which ensures all required power domains are in enabled state before configuring the PLLs or enabling the clocks. Reviewed-by: Konrad Dybcio Reviewed-by: Dmitry Baryshkov Signed-off-by: Jagadeesh Kona Reviewed-by: Bryan O'Donoghue --- drivers/clk/qcom/camcc-sm8650.c | 83 +++++++++++++++++++++----------------= ---- 1 file changed, 42 insertions(+), 41 deletions(-) diff --git a/drivers/clk/qcom/camcc-sm8650.c b/drivers/clk/qcom/camcc-sm865= 0.c index 0ccd6de8ba78a3493f8f853a4330d2676b5743d4..8b388904f56fc3b3f77a43a09f7= 35ace24b9fcf7 100644 --- a/drivers/clk/qcom/camcc-sm8650.c +++ b/drivers/clk/qcom/camcc-sm8650.c @@ -7,7 +7,6 @@ #include #include #include -#include #include =20 #include @@ -72,6 +71,7 @@ static const struct alpha_pll_config cam_cc_pll0_config = =3D { =20 static struct clk_alpha_pll cam_cc_pll0 =3D { .offset =3D 0x0, + .config =3D &cam_cc_pll0_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -149,6 +149,7 @@ static const struct alpha_pll_config cam_cc_pll1_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll1 =3D { .offset =3D 0x1000, + .config =3D &cam_cc_pll1_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -199,6 +200,7 @@ static const struct alpha_pll_config cam_cc_pll2_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll2 =3D { .offset =3D 0x2000, + .config =3D &cam_cc_pll2_config, .vco_table =3D rivian_ole_vco, .num_vco =3D ARRAY_SIZE(rivian_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_RIVIAN_EVO], @@ -230,6 +232,7 @@ static const struct alpha_pll_config cam_cc_pll3_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll3 =3D { .offset =3D 0x3000, + .config =3D &cam_cc_pll3_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -284,6 +287,7 @@ static const struct alpha_pll_config cam_cc_pll4_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll4 =3D { .offset =3D 0x4000, + .config =3D &cam_cc_pll4_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -338,6 +342,7 @@ static const struct alpha_pll_config cam_cc_pll5_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll5 =3D { .offset =3D 0x5000, + .config =3D &cam_cc_pll5_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -392,6 +397,7 @@ static const struct alpha_pll_config cam_cc_pll6_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll6 =3D { .offset =3D 0x6000, + .config =3D &cam_cc_pll6_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -446,6 +452,7 @@ static const struct alpha_pll_config cam_cc_pll7_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll7 =3D { .offset =3D 0x7000, + .config =3D &cam_cc_pll7_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -500,6 +507,7 @@ static const struct alpha_pll_config cam_cc_pll8_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll8 =3D { .offset =3D 0x8000, + .config =3D &cam_cc_pll8_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -554,6 +562,7 @@ static const struct alpha_pll_config cam_cc_pll9_config= =3D { =20 static struct clk_alpha_pll cam_cc_pll9 =3D { .offset =3D 0x9000, + .config =3D &cam_cc_pll9_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -631,6 +640,7 @@ static const struct alpha_pll_config cam_cc_pll10_confi= g =3D { =20 static struct clk_alpha_pll cam_cc_pll10 =3D { .offset =3D 0xa000, + .config =3D &cam_cc_pll10_config, .vco_table =3D lucid_ole_vco, .num_vco =3D ARRAY_SIZE(lucid_ole_vco), .regs =3D clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_LUCID_OLE], @@ -3509,6 +3519,27 @@ static const struct qcom_reset_map cam_cc_sm8650_res= ets[] =3D { [CAM_CC_SFE_2_BCR] =3D { 0x130f4 }, }; =20 +static struct clk_alpha_pll *cam_cc_sm8650_plls[] =3D { + &cam_cc_pll0, + &cam_cc_pll1, + &cam_cc_pll2, + &cam_cc_pll3, + &cam_cc_pll4, + &cam_cc_pll5, + &cam_cc_pll6, + &cam_cc_pll7, + &cam_cc_pll8, + &cam_cc_pll9, + &cam_cc_pll10, +}; + +static u32 cam_cc_sm8650_critical_cbcrs[] =3D { + 0x132ec, /* CAM_CC_GDSC_CLK */ + 0x13308, /* CAM_CC_SLEEP_CLK */ + 0x13314, /* CAM_CC_DRV_XO_CLK */ + 0x13318, /* CAM_CC_DRV_AHB_CLK */ +}; + static const struct regmap_config cam_cc_sm8650_regmap_config =3D { .reg_bits =3D 32, .reg_stride =3D 4, @@ -3517,6 +3548,13 @@ static const struct regmap_config cam_cc_sm8650_regm= ap_config =3D { .fast_io =3D true, }; =20 +static struct qcom_cc_driver_data cam_cc_sm8650_driver_data =3D { + .alpha_plls =3D cam_cc_sm8650_plls, + .num_alpha_plls =3D ARRAY_SIZE(cam_cc_sm8650_plls), + .clk_cbcrs =3D cam_cc_sm8650_critical_cbcrs, + .num_clk_cbcrs =3D ARRAY_SIZE(cam_cc_sm8650_critical_cbcrs), +}; + static const struct qcom_cc_desc cam_cc_sm8650_desc =3D { .config =3D &cam_cc_sm8650_regmap_config, .clks =3D cam_cc_sm8650_clocks, @@ -3525,6 +3563,8 @@ static const struct qcom_cc_desc cam_cc_sm8650_desc = =3D { .num_resets =3D ARRAY_SIZE(cam_cc_sm8650_resets), .gdscs =3D cam_cc_sm8650_gdscs, .num_gdscs =3D ARRAY_SIZE(cam_cc_sm8650_gdscs), + .use_rpm =3D true, + .driver_data =3D &cam_cc_sm8650_driver_data, }; =20 static const struct of_device_id cam_cc_sm8650_match_table[] =3D { @@ -3535,46 +3575,7 @@ MODULE_DEVICE_TABLE(of, cam_cc_sm8650_match_table); =20 static int cam_cc_sm8650_probe(struct platform_device *pdev) { - struct regmap *regmap; - int ret; - - ret =3D devm_pm_runtime_enable(&pdev->dev); - if (ret) - return ret; - - ret =3D pm_runtime_resume_and_get(&pdev->dev); - if (ret) - return ret; - - regmap =3D qcom_cc_map(pdev, &cam_cc_sm8650_desc); - if (IS_ERR(regmap)) { - pm_runtime_put(&pdev->dev); - return PTR_ERR(regmap); - } - - clk_lucid_ole_pll_configure(&cam_cc_pll0, regmap, &cam_cc_pll0_config); - clk_lucid_ole_pll_configure(&cam_cc_pll1, regmap, &cam_cc_pll1_config); - clk_rivian_evo_pll_configure(&cam_cc_pll2, regmap, &cam_cc_pll2_config); - clk_lucid_ole_pll_configure(&cam_cc_pll3, regmap, &cam_cc_pll3_config); - clk_lucid_ole_pll_configure(&cam_cc_pll4, regmap, &cam_cc_pll4_config); - clk_lucid_ole_pll_configure(&cam_cc_pll5, regmap, &cam_cc_pll5_config); - clk_lucid_ole_pll_configure(&cam_cc_pll6, regmap, &cam_cc_pll6_config); - clk_lucid_ole_pll_configure(&cam_cc_pll7, regmap, &cam_cc_pll7_config); - clk_lucid_ole_pll_configure(&cam_cc_pll8, regmap, &cam_cc_pll8_config); - clk_lucid_ole_pll_configure(&cam_cc_pll9, regmap, &cam_cc_pll9_config); - clk_lucid_ole_pll_configure(&cam_cc_pll10, regmap, &cam_cc_pll10_config); - - /* Keep clocks always enabled */ - qcom_branch_set_clk_en(regmap, 0x13318); /* CAM_CC_DRV_AHB_CLK */ - qcom_branch_set_clk_en(regmap, 0x13314); /* CAM_CC_DRV_XO_CLK */ - qcom_branch_set_clk_en(regmap, 0x132ec); /* CAM_CC_GDSC_CLK */ - qcom_branch_set_clk_en(regmap, 0x13308); /* CAM_CC_SLEEP_CLK */ - - ret =3D qcom_cc_really_probe(&pdev->dev, &cam_cc_sm8650_desc, regmap); - - pm_runtime_put(&pdev->dev); - - return ret; + return qcom_cc_probe(pdev, &cam_cc_sm8650_desc); } =20 static struct platform_driver cam_cc_sm8650_driver =3D { --=20 2.34.1