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Fri, 30 May 2025 10:32:43 +0000 (GMT) Received: from nalasex01c.na.qualcomm.com (nalasex01c.na.qualcomm.com [10.47.97.35]) by NALASPPMTA05.qualcomm.com (8.18.1.2/8.18.1.2) with ESMTPS id 54UAWgeb001270 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Fri, 30 May 2025 10:32:42 GMT Received: from hu-renjiang-sha.qualcomm.com (10.80.80.8) by nalasex01c.na.qualcomm.com (10.47.97.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.9; Fri, 30 May 2025 03:32:39 -0700 From: Renjiang Han Date: Fri, 30 May 2025 16:01:59 +0530 Subject: [PATCH v5] clk: qcom: videocc: Use HW_CTRL_TRIGGER flag for video GDSC's Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250530-switch_gdsc_mode-v5-1-657c56313351@quicinc.com> X-B4-Tracking: v=1; b=H4sIAB6JOWgC/23PwWrDMAyA4VcpPs/Fli1n3mnvMUZJZKXRockWd 9lGybvXKZRCk+Mv0Cd0UZlH4azedhc18iRZhr4EvuwUdXV/ZC2ptAIDaNAZnX/lTN3hmDIdTkN iDRhc8JHYVqjK2tfIrfzdyI/P0p3k8zD+3y5MdpkumLcWYI1NVhvtArYmVkxNY96/f4Skpz0NJ 7VwEzwIALdBQCG4QYqhZg4B1oS7E2isxQ3CFSLW4BO0qQJPa8I/CLCvG4QvBPrQBoqANT89Ms/ zFRyVoqB7AQAA X-Change-ID: 20250530-switch_gdsc_mode-2563649ce175 To: Bjorn Andersson , Michael Turquette , Stephen Boyd CC: , , , Taniya Das , "Vikash Garodia" , Bryan O'Donoghue , Renjiang Han , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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Hence use HW_CTRL_TRIGGER flag instead of HW_CTRL for video GDSC's for Qualcomm SoC SC7180, SDM845, SM7150, SM8150 and SM8450. Signed-off-by: Taniya Das Reviewed-by: Dmitry Baryshkov Reviewed-by: Vikash Garodia Reviewed-by: Bryan O'Donoghue Signed-off-by: Renjiang Han --- The Venus driver requires vcodec GDSC to be ON in SW mode for clock operations and move it back to HW mode to gain power benefits. Earlier, as there is no interface to switch the GDSC mode from GenPD framework, the GDSC is moved to HW control mode as part of GDSC enable callback and venus driver is writing to its POWER_CONTROL register to keep the GDSC ON from SW whereever required. But the POWER_CONTROL register addresses are not constant and can vary across the variants. Also as per the HW recommendation, the GDSC mode switching needs to be controlled from respective GDSC register and this is a uniform approach across all the targets. Hence use dev_pm_genpd_set_hwmode() API which controls GDSC mode switching using its respective GDSC register. Make venus driver to use dev_pm_genpd_set_hwmode() to switch GDSC mode on v4. - 1. the venus driver adds compatibility with the new way to switch GDSC mode. - 2. the clock driver uses the HW_CTRL_TRIGGER flag, which means the venus driver needs to use the dev_pm_genpd_set_hwmode() API to switch GDSC mode. Validated this series on QCS615 and SC7180. Note: This series only includes videocc patches and it can be picked independently without having any functional dependency. --- Changes in v5: - 1. Remove venus driver patch from this patch series due to it has been picked. - Link to v4: https://lore.kernel.org/r/20250218-switch_gdsc_mode-v4-0-546f= 6c925ae0@quicinc.com Changes in v4: - 1. Update the order of patches. - 2. Update vcodec_control_v4 to try dev_pm_genpd_set_hwmode first. - 3. Add hwmode_dev to indicate whether to use HW_CTRL_TRIGGER flag. - 4. Update commit message and cover letter message. - 5. Remove the patch that cleaned up dead code and will submit this patch with next patch series. - Link to v3: https://lore.kernel.org/r/20250115-switch_gdsc_mode-v3-0-9a24= d2fd724c@quicinc.com Changes in v3: - 1. Update commit message. - 2. Add a patch to clean up the dead code for the venus driver. - 3. Remove vcodec_control_v4() function. - 4. Directly call dev_pm_genpd_set_hwmode() without vcodec_control_v4(). - Link to v2: https://lore.kernel.org/r/20241223-switch_gdsc_mode-v2-0-eb5c= 96aee662@quicinc.com Changes in v2: - 1. Add the HW_CTRL_TRIGGER flag for the targets SM7150/SM8150 and SM8450 video GDSCs supporting movement between HW and SW mode of the GDSC. (Suggested by Dmitry Baryshkov) - 2. There is a dependency of the clock driver introducing the new flag and the video driver adapting to this new API. Missing either the clock and video driver could potentially break the video driver. - Link to v1: https://lore.kernel.org/r/20241122-switch_gdsc_mode-v1-0-365f= 097ecbb0@quicinc.com --- drivers/clk/qcom/videocc-sc7180.c | 2 +- drivers/clk/qcom/videocc-sdm845.c | 4 ++-- drivers/clk/qcom/videocc-sm7150.c | 4 ++-- drivers/clk/qcom/videocc-sm8150.c | 4 ++-- drivers/clk/qcom/videocc-sm8450.c | 4 ++-- 5 files changed, 9 insertions(+), 9 deletions(-) diff --git a/drivers/clk/qcom/videocc-sc7180.c b/drivers/clk/qcom/videocc-s= c7180.c index d7f84548039699ce6fdd7c0f6675c168d5eaf4c1..dd2441d6aa83bd7cff17deeb42f= 5d011c1e9b134 100644 --- a/drivers/clk/qcom/videocc-sc7180.c +++ b/drivers/clk/qcom/videocc-sc7180.c @@ -166,7 +166,7 @@ static struct gdsc vcodec0_gdsc =3D { .pd =3D { .name =3D "vcodec0_gdsc", }, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL_TRIGGER, .pwrsts =3D PWRSTS_OFF_ON, }; =20 diff --git a/drivers/clk/qcom/videocc-sdm845.c b/drivers/clk/qcom/videocc-s= dm845.c index f77a0777947773dc8902c92098acff71b9b8f10f..6dedc80a8b3e18eca82c08a5bcd= 7e1fdc374d4b5 100644 --- a/drivers/clk/qcom/videocc-sdm845.c +++ b/drivers/clk/qcom/videocc-sdm845.c @@ -260,7 +260,7 @@ static struct gdsc vcodec0_gdsc =3D { }, .cxcs =3D (unsigned int []){ 0x890, 0x930 }, .cxc_count =3D 2, - .flags =3D HW_CTRL | POLL_CFG_GDSCR, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts =3D PWRSTS_OFF_ON, }; =20 @@ -271,7 +271,7 @@ static struct gdsc vcodec1_gdsc =3D { }, .cxcs =3D (unsigned int []){ 0x8d0, 0x950 }, .cxc_count =3D 2, - .flags =3D HW_CTRL | POLL_CFG_GDSCR, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts =3D PWRSTS_OFF_ON, }; =20 diff --git a/drivers/clk/qcom/videocc-sm7150.c b/drivers/clk/qcom/videocc-s= m7150.c index 14ef7f5617537363673662adc3910ddba8ea6a4f..b6912560ef9b7a84e7fd1d9924f= 5aac6967da780 100644 --- a/drivers/clk/qcom/videocc-sm7150.c +++ b/drivers/clk/qcom/videocc-sm7150.c @@ -271,7 +271,7 @@ static struct gdsc vcodec0_gdsc =3D { }, .cxcs =3D (unsigned int []){ 0x890, 0x9ec }, .cxc_count =3D 2, - .flags =3D HW_CTRL | POLL_CFG_GDSCR, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts =3D PWRSTS_OFF_ON, }; =20 @@ -282,7 +282,7 @@ static struct gdsc vcodec1_gdsc =3D { }, .cxcs =3D (unsigned int []){ 0x8d0, 0xa0c }, .cxc_count =3D 2, - .flags =3D HW_CTRL | POLL_CFG_GDSCR, + .flags =3D HW_CTRL_TRIGGER | POLL_CFG_GDSCR, .pwrsts =3D PWRSTS_OFF_ON, }; =20 diff --git a/drivers/clk/qcom/videocc-sm8150.c b/drivers/clk/qcom/videocc-s= m8150.c index daab3237eec19b727d34512d3a2ba1d7bd2743d6..3024f6fc89c8b374f2ef13debc2= 83998cb136f6b 100644 --- a/drivers/clk/qcom/videocc-sm8150.c +++ b/drivers/clk/qcom/videocc-sm8150.c @@ -179,7 +179,7 @@ static struct gdsc vcodec0_gdsc =3D { .pd =3D { .name =3D "vcodec0_gdsc", }, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL_TRIGGER, .pwrsts =3D PWRSTS_OFF_ON, }; =20 @@ -188,7 +188,7 @@ static struct gdsc vcodec1_gdsc =3D { .pd =3D { .name =3D "vcodec1_gdsc", }, - .flags =3D HW_CTRL, + .flags =3D HW_CTRL_TRIGGER, .pwrsts =3D PWRSTS_OFF_ON, }; static struct clk_regmap *video_cc_sm8150_clocks[] =3D { diff --git a/drivers/clk/qcom/videocc-sm8450.c b/drivers/clk/qcom/videocc-s= m8450.c index 2e11dcffb6646d47b298c27ef68635a465dd728e..be68d9bf52a2df9c09828e3d636= 085d7f942a89d 100644 --- a/drivers/clk/qcom/videocc-sm8450.c +++ b/drivers/clk/qcom/videocc-sm8450.c @@ -347,7 +347,7 @@ static struct gdsc video_cc_mvs0_gdsc =3D { }, .pwrsts =3D PWRSTS_OFF_ON, .parent =3D &video_cc_mvs0c_gdsc.pd, - .flags =3D RETAIN_FF_ENABLE | HW_CTRL, + .flags =3D HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; =20 static struct gdsc video_cc_mvs1c_gdsc =3D { @@ -372,7 +372,7 @@ static struct gdsc video_cc_mvs1_gdsc =3D { }, .pwrsts =3D PWRSTS_OFF_ON, .parent =3D &video_cc_mvs1c_gdsc.pd, - .flags =3D RETAIN_FF_ENABLE | HW_CTRL, + .flags =3D HW_CTRL_TRIGGER | RETAIN_FF_ENABLE, }; =20 static struct clk_regmap *video_cc_sm8450_clocks[] =3D { --- base-commit: 3a83b350b5be4b4f6bd895eecf9a92080200ee5d change-id: 20250530-switch_gdsc_mode-2563649ce175 Best regards, --=20 Renjiang Han