From nobody Tue Dec 16 22:31:37 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0648227BB6; Thu, 29 May 2025 13:35:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525722; cv=none; b=NdhtDnc6UbiIyMmbZZUiN1gfe6wdEOTr6ileltLGKgGuBuRsGGDO+8MF8jDOLZdyb4cDANlWvvEizYutcensHGvBaLgZtS+p9iABgAZCaVw/tYDRXi8gNctw3NfJLfFzPnMceu3ET/A7ODncg3d0dQy/mf2vGGfyBcK4fiNge9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525722; c=relaxed/simple; bh=mxYwWd/9uIeUWgMSTogDHl0/0FX0rUSDGM12IDUcVpY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ajQ1XmwH6F/TTr6BFp2cMbGDA2O4hEjbaGnLE6skY8GxmbpgzBG4cveVffBzM20sXcC4lH3bR/EraadxpSvfPq/Wml+rLBrv17qygH/q+PL+mkJnX9TuadW5eYJ1PrZYO6d5NtmyCwsknw/sCkHzYTO2FTak1481y0nbVFvHoOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pCk+iWLS; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pCk+iWLS" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZFNJ3532941; Thu, 29 May 2025 08:35:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525715; bh=yx1V3FDCa2PJZt0KPoKs6lMJ44AVNFuwqQaT8iuG26g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pCk+iWLS+iqz4hJqVRHj1SrTRatMSTwY1H7Ge1gvUsj2Ywwtpxw/wFu8e05wbfAY2 bJnr/ER7zrRY8q/2dUj9blOhnJOYW6aCJRG2o0pJMB56tbcBBhXvcEpP4v2p6rxFbI kUuWnRDaH4ucosclefc9nqPoWsTFs+oINy5NhivA= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZFke064269 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:15 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:15 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:15 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8o1650971; Thu, 29 May 2025 08:35:12 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 08/13] arm64: dts: ti: k3-j7200-common-proc-board: Enable "mcu_cpsw" in board file Date: Thu, 29 May 2025 19:04:38 +0530 Message-ID: <20250529133443.1252293-9-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "mcu_cpsw" device-tree node in the SoC file, namely "k3-j7200-mcu-wakeup.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index f684ce6ad9ad..021cdeb84ad1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -321,6 +321,7 @@ &wkup_gpio0 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; --=20 2.34.1