From nobody Tue Dec 16 22:31:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA77622ACE7; Thu, 29 May 2025 13:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525711; cv=none; b=Yma7+3utjUfABG9a762BCqVBlGjYqTuN86BfzdeCHwqxXrtYXqtpa7uf15/shNwwMdwfslxu4yW7xRRc1LuhooO4Hf+2EgiEpZYQ/UGIgOtFgQOb9ff/lY30O59ueUQLGN+Z1pdMUwusqU+yjf+cXq8W8CFYkwdyhAKRduBWI+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525711; c=relaxed/simple; bh=7UAcyQ8dKsoHD82jua5xfGKBWRpmDXr/0nsbZNJ92Nc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Elt3QTJi3gmSNfxLHNsLUgW4UOW3EuBc/S9fUDYJNDL5uXmnqd9NuqsE5B0QNKGT/U9jZg9kanYU0ZKxZcxy6I1kNGN+9YOUV0hSREJ1H5Yl4fg5aiNi0M6h6Omy2bXdZ+imgNi1dZ1KZAphOijBHMxSLkBRJstpViwU4c7LM2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xKlsblx8; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xKlsblx8" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZ5e12407088; Thu, 29 May 2025 08:35:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525705; bh=5J/dLICwJ5Y1HVV7l8DTPQWsobQVIaWtOsJ6ROsyyiw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xKlsblx8q2eoJ8wO3GLaKYCtj32RHQ6FSkb3i4ofbwQCsgttj+HrND/GBS/KzE9FZ uOt6RLuxqSmDdFmqQKBhh7/v1ro82+9AHO0muVyqz3pIg9EaF+KsKtZoORP3vs8QR7 wtRxn42HuCvdZU+y6/36c6pB+fVWqHla/pEmGwF8= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZ5ff126533 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:05 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:05 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:05 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8l1650971; Thu, 29 May 2025 08:35:02 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 05/13] arm64: dts: ti: k3-am654-base-board: Enable "mcu_cpsw" in board file Date: Thu, 29 May 2025 19:04:35 +0530 Message-ID: <20250529133443.1252293-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "cpsw3g" device-tree node in the SoC file, namely "k3-am65-mcu.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index c30425960398..d2632d1f8eb7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -606,6 +606,7 @@ partition@3fe0000 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>; }; --=20 2.34.1