From nobody Tue Dec 16 22:20:23 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A77E522A4D5; Thu, 29 May 2025 13:35:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525739; cv=none; b=rgpSntePmSHy09+emyZXpU0stZo493uLTELdxTpLW8rsAHK1w+B4zNopQ1Fh44zqV/jvJeVZ4lVaON015ttE6ZJzJ6ETxRBv/MNUN/Py42HzuC1RPhPLt05OBZWSvoijcLkYGlmMphnDu7BSRLytUYk/AfevkokiGOsLdphxzJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525739; c=relaxed/simple; bh=8W4QUpDgcTW+Xah7t96FXbifwuMnXr0fKIWV2VB2/aU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LJ32xv5Bp6zhUdQbIsllUF+3e89rtbapTglxBlUrCmKCoWKyiBZu0J80eOdnR2c6sl5m2aZlJ3k/ClXsQ7xH/PaPLY8Xcp1ePzdsmRr+thnfrFQyRw7GwmHWGg2npTUNsX9Pam9bkafx3GlMqSrBiaYRwuQDQZhEAenSiil52Hs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=TCe6Zrw1; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TCe6Zrw1" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZXvu3591425; Thu, 29 May 2025 08:35:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525733; bh=LB8Z0NdebTCSX3P28O31aPVquD8FAYcpb5/udEKYrn4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TCe6Zrw1eggZ34MGHhi6X/HAmnKCXcHCrDAeQx0wxHCKI4aZP+hm7oIANlArNWPlT lcwaMVp9e/IdaCvX1fjR6wv1C6LjKaxQvk7+AkiElGINDoIqj6vzv5GQrLG6g509YK wCK+HPcfenKUdpXEpkbYS3taxs0C8Oxijs+4ZJCI= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZX7o2202210 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:33 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:33 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:32 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8t1650971; Thu, 29 May 2025 08:35:30 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 13/13] arm64: dts: ti: k3-j721s2-mcu-wakeup: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:43 +0530 Message-ID: <20250529133443.1252293-14-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..b5fd012d9564 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -552,6 +552,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1