From nobody Tue Dec 16 22:31:36 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D35101C3F36; Thu, 29 May 2025 13:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525732; cv=none; b=S4XJneqDs3Mh2WdYtJQX3CvrwlUO2gzco5UBFIGkk8mh6TwTDPwZvDPsVO8fuhT04JnX72wwbbhEy5tEeGP3mKrrGqpH9gwLaq6SkYJf3DvaNPXOIJ7usvy4uK0Liu1Rkn/ug0Ai600rp+ajtXLOs1Yb2G8Y5qfWeIFAhvs3KVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525732; c=relaxed/simple; bh=8QBk7WwTfAz3x55hQUgW8LQ5an8ehM8R8JsYc5PDDNI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CnB+Bz57eXraozLN++EBlkhB1LonZgWDqY8Aoz8s0LO/+T/BNdOk2KYeyhuYtQy53rGtNUXdLBvUMdZjCbvIHllhwDlZHnVItrRSczB/ZWK28Hr4bNAt79DSLMG3jzEs92C1m1WDN+fqX1L7UP2ujA8Hzug1uuv1lRD+G+fZdaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=I+QuMIbF; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="I+QuMIbF" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZQ3n2407099; Thu, 29 May 2025 08:35:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525726; bh=6H7HUuEynzu+SANLoTLLFVnfS6/zJMqCGCZ1MLeRFPk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I+QuMIbFXtIrqhCEH/prQJ5UD13NupJteUXlfVOWBScmgGVlY+FD4rEZDgJCWgb6q qU0OT+gOH6Qb3KX2U5h046e+3dfDXShyYkW0C1VhjGVN01Nk9WcgSkynQUDEM1y6eX tCx0HH8fcRNpE+gEdLFdmjtMyjKqw1e4Jr6U5T/g= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZQH2064384 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:26 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:26 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:26 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8r1650971; Thu, 29 May 2025 08:35:23 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 11/13] arm64: dts: ti: k3-j721e-mcu-wakeup: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:41 +0530 Message-ID: <20250529133443.1252293-12-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b02142b2b460..dd923540ca0a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -551,6 +551,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1