From nobody Tue Dec 16 22:31:39 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFFF922D7B9; Thu, 29 May 2025 13:35:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525725; cv=none; b=Ye22RfIspef8KZ+Tl1a/QGgBo7gO2c1ueEt5+xt7VOb2ggBankGbxWU658lsKAjF6Fm5wu5Pue39A1fzdDKPhEmkgq396sxbz3l4yjiYLya+s5b/RGBXJv0VrKUHPV6P7ZS6haRqT95Ro4JJD3IrxksyhVU8N3zzWmL627ZaOXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525725; c=relaxed/simple; bh=c+L+erR+j3eIiHx7zBeFYR8Apd6DIP/uMkxtJZRK7h8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Db2NP8WzAyqWacCEOKJl5SOKdhr9ylt2mLFfLohqZSU135ddmjjQKwuq0dqf8rGKnK2fqWbukpV7YjtTx7cgRAPAHnPjpsRAQIPEkB9IjTJL/8Ip8PI2K9ErPZ7vm/6xwcdC0ikoqvuEkQn0trZpkGuBxnY+u1+vNgNn6FaHp4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fxdg8e4r; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fxdg8e4r" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZJUC3532957; Thu, 29 May 2025 08:35:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525719; bh=v51QyjN1wMrH5TRcc7+b3a/r/Csd2hSWT/chYr91cIY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fxdg8e4rzlaSiCv6Ml3Z1EkRmwxYk1C0CaTxULcqH50Ot1evM9RCO3JEAUj/ywC9t DgkXRdem0NR4hDlS1LV5he6sl86ndRyz2pwv+qPnj6rwBIs52wNdHn5GUF00shK1Kt ktDbFTOBd4N92JmKi6NXXnJN/EMNQfbBb5jrWx+I= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZJOn126670 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:19 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:18 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:19 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8p1650971; Thu, 29 May 2025 08:35:16 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 09/13] arm64: dts: ti: k3-j7200-mcu-wakeup: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:39 +0530 Message-ID: <20250529133443.1252293-10-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..604295092d06 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -432,6 +432,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1