From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 9C4811C3F36; Thu, 29 May 2025 13:34:58 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525700; cv=none; b=mSfXBg2caYJze8CqAuUrQXNRt8EfroBf6UJo9oqU24XYol6Ue3UItaXxQ/yxEntTypiPZ0NHSj2P3hRTR/1MaOg7jv96tgpYkav+nTcDquwSJclKgXJg49iZU52FO0KGgR7A4f8RK9cO4oH6/hL5wiTmYjH2AFMED2xs7aFpq3M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525700; c=relaxed/simple; bh=vaOZMCvLCmBp6mhm9kcgj12R05vDdhdjK/O0apb5kVI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=B771snGtrGOeYWkSDBB4NgLWNR3A3e6gAxhH5HGMLDDeZFAshdPLcuTaT6MV771BmtMLsWof/h6eQAqL9XrDumefCIK35Tr1a0KgWWNRpiP6qGqgd/td7YnD9r9Bkq/1N3WyCFQy/6fKpflejhaE2xNqtQ17Nw3WObmLWgojYss= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fMK3zD1I; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fMK3zD1I" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDYpYQ2407009; Thu, 29 May 2025 08:34:51 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525691; bh=CMupLjWd2gTIRNUkkhAjmLP4EX857cqSjwQTFVZ2qhI=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fMK3zD1IP7KzaJX1n0elp8xIOHfHYe5nBrUhElxCirsCpcf7ffTUQbG1MmyrfIxyt luD3/B5pD3U6svw3wZiVvCaX+FPNwB/69bnbYOzMUUulP6NIgN3ecMK5eyC4iNgNPn lkUCfC/qDyHsXblCd2KL9yp4dCxXx93IPB7HA2H0= Received: from DFLE113.ent.ti.com (dfle113.ent.ti.com [10.64.6.34]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDYpj7063926 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:34:51 -0500 Received: from DFLE106.ent.ti.com (10.64.6.27) by DFLE113.ent.ti.com (10.64.6.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:34:51 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE106.ent.ti.com (10.64.6.27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:34:51 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8h1650971; Thu, 29 May 2025 08:34:48 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 01/13] arm64: dts: ti: k3-am625-beagleplay: Enable "cpsw3g" in the board file Date: Thu, 29 May 2025 19:04:31 +0530 Message-ID: <20250529133443.1252293-2-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "cpsw3g" device-tree node in the SoC file, namely "k3-am62-main.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts b/arch/arm64/bo= ot/dts/ti/k3-am625-beagleplay.dts index 72b09f9c69d8..999f5baaba1a 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-beagleplay.dts @@ -585,6 +585,7 @@ &usb1 { }; =20 &cpsw3g { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&rgmii1_pins_default>, <&spe_pins_default>, <&gbe_pmx_obsclk>; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46F4F2110; Thu, 29 May 2025 13:34:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525701; cv=none; b=oVZTc+k0O2cqh7xMBc5/gbOb9CQlLo0UCFtNw4nxMqbKFjmjj2dgltmdZhYA09NXKXWWPqQIQ3V3teqQykUWMkQ7HopDNv6vjdHBFNqoy6tyvveXO+0uifiG1i/igcYoXaTzkx2bcFkbURuPLIylisDE/4tZaOIaYNkypqkxJNA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525701; c=relaxed/simple; bh=oLAYltQ5k4BGZSmpZFs+aEaNdsULyCL4N3ciy4MA5q8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=dMNUGvU124FKtt67UREj25i5gNib5LDJ/kcFskjcfQWBoVabCF/IDDX2jq96QqJG3B12BiPxk1KRBx1svVyXec6jhY7jcdZvfIVhB+uEmMwz/+enmxiGDXnHhTmVA2tmH7a1lO16C69c8O0Mu+tI82L7ndsLmq+KX/38O6qwLgk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=Qf1R6XDE; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="Qf1R6XDE" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDYtae2407049; Thu, 29 May 2025 08:34:55 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525695; bh=V8qlacFfGBNxkk5act1sUfB5rBAj+y20pwNN9ewBtqg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=Qf1R6XDE2/1E7jMA5s7kqZlFrubC5LReE2QWofmtHvl80QEH6A0tvmUPD8QFN/nxf xgM+vXHI5vgtCaZUOFmUXKr2IwphODqmqiYPSunvJdHqh14WFo6+3S32gDE1DpnRMT iIQRF+4DfqSiD1Uga16JyuQ7l1zUBEZkruStYxbc= Received: from DLEE112.ent.ti.com (dlee112.ent.ti.com [157.170.170.23]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDYtS9180005 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:34:55 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE112.ent.ti.com (157.170.170.23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:34:54 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:34:54 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8i1650971; Thu, 29 May 2025 08:34:51 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 02/13] arm64: dts: ti: k3-am62-lp-sk: Enable "cpsw3g" in the board file Date: Thu, 29 May 2025 19:04:32 +0530 Message-ID: <20250529133443.1252293-3-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "cpsw3g" device-tree node in the SoC file, namely "k3-am62-main.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts b/arch/arm64/boot/dts= /ti/k3-am62-lp-sk.dts index aafdb90c0eb7..cec77fba24e6 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am62-lp-sk.dts @@ -149,6 +149,10 @@ &sdhci1 { vqmmc-supply =3D <&vddshv_sdio>; }; =20 +&cpsw3g { + status =3D "okay"; +}; + &cpsw_port2 { status =3D "disabled"; }; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 990C7229B16; Thu, 29 May 2025 13:35:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525705; cv=none; b=QIXqQaTKHWAHoFbavTn/SU5MfQgo557IXKVmNnyn3X6lCU7qxfP1MqyFUmrU/SCJ7pgprC+85dRiILnDQVZOch7BpB5NhbziN3eFmgxRY4h/W87kIdHXj8y5+uuji+5EZlQ2M3faxflrCo7CltV1qxsbvrHcHtrZGv54uhpWm8Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525705; c=relaxed/simple; bh=ZjPypbUo/gbj0R/7ow+Akp8KWWfhLRphMWIMRsbT1hs=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=QVsSYiDIstNq55eIkfsQ28DT/w4usm0rZiVRNX+Z33D/96ptCnzobD5T3gcovEkSTwG7ALUFTRPCRq+AuCQCSqnNB5M9coI01JCtw8iHZSidICeN3P7Ud8n6gECUNwDdejq93c6UZ7Pp9hVOHXyvuHSNONoaM1c8fkEbpFEizIw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=EUpmVPhP; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="EUpmVPhP" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDYw9x2407053; Thu, 29 May 2025 08:34:58 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525698; bh=R6Ke6TQMJrIPkLJIi5JmxYTaZtcYoSq6WZNd77NEz9U=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=EUpmVPhPAWYJhpXsg9fRTKgU66ellwSPr/TNmyxzj4LlmWS4BqiEj3UXhhYm896li AmDLE3Kp9mdev2XqANDz5MrioaXTNQAK11HiIXzhJAHZqFsWPUPLoXB1FxsTyz7a+d Nbbltq5ZIlVMGYPA48PtsxUOgVzM7z/+ZnyajPGM= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDYwAm063975 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:34:58 -0500 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:34:58 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:34:58 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8j1650971; Thu, 29 May 2025 08:34:55 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 03/13] arm64: dts: ti: k3-am625-sk: Enable "cpsw3g" in the board file Date: Thu, 29 May 2025 19:04:33 +0530 Message-ID: <20250529133443.1252293-4-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "cpsw3g" device-tree node in the SoC file, namely "k3-am62-main.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am625-sk.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am625-sk.dts b/arch/arm64/boot/dts/t= i/k3-am625-sk.dts index 2fbfa3719345..9c2258dfd08d 100644 --- a/arch/arm64/boot/dts/ti/k3-am625-sk.dts +++ b/arch/arm64/boot/dts/ti/k3-am625-sk.dts @@ -201,6 +201,7 @@ &sdhci1 { }; =20 &cpsw3g { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&main_rgmii1_pins_default>, <&main_rgmii2_pins_default>; }; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7BFE722B598; Thu, 29 May 2025 13:35:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525713; cv=none; b=t0SmmfpK1k8577Cj+Z3mrgO4AuN1F+FFyjgJAyGEV52AskpQk2+CRW8bLkLgR24qKla9YrxmsgDfBwYD1MS/nX2zEta3hYhSTi8MYBp95mdw2RbOQO0si84rFkhiewgYtbN+PNXaZw8Gmrv5Q/2i8JEymgSiWM+Ar1MXsVayfgU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525713; c=relaxed/simple; bh=RRvTbjUwRP6Uuz5fWWBJurVlIdgwZlVYZoshFWTv8hI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=efXXkihQ03gMEIBePV/KlaL+HZmBR7B7Y4GYfNwD6ALmipgibrH0NHcLS9d3ZLmP9uWjhVrjJdDWPgsKhHMG3K5MnnOIP35VklB2vhmb2lAuwxmFwaV5g/taL7SuCVcCzYdKPNxZmH06rMjy5nyJC8pX9rCoq17ajZd662VPhxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=IAwV4dj2; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="IAwV4dj2" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZ23C2378554; Thu, 29 May 2025 08:35:02 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525702; bh=xewEuLCylugOmuqUPUKm8Asgw99ethqNbgBBVd0Mu10=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=IAwV4dj2Y/dW5pc9XgMSP/rGDtPfDbvuPFgr/d1P8YP9d2oBAtpJgnDN4lrn7VDoK iX+Sf0uOkTpJjLnbAhF41z8UCWtE1JK5EzJ3yJVbxRDzmzervafC0BZd5UnFN9+GBn N88yL6awtS6tz71qrxTqrPJp7y9JjdUypMDk6Jjo= Received: from DLEE107.ent.ti.com (dlee107.ent.ti.com [157.170.170.37]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZ2ev064041 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:02 -0500 Received: from DLEE113.ent.ti.com (157.170.170.24) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:01 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:01 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8k1650971; Thu, 29 May 2025 08:34:58 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 04/13] arm64: dts: ti: k3-am62-main: Disable "cpsw3g" in the SoC file Date: Thu, 29 May 2025 19:04:34 +0530 Message-ID: <20250529133443.1252293-5-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "cpsw3g" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am62-main.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi b/arch/arm64/boot/dts= /ti/k3-am62-main.dtsi index 9e0b6eee9ac7..3d8650e7c80b 100644 --- a/arch/arm64/boot/dts/ti/k3-am62-main.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am62-main.dtsi @@ -724,6 +724,8 @@ cpsw3g: ethernet@8000000 { dma-names =3D "tx0", "tx1", "tx2", "tx3", "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EA77622ACE7; Thu, 29 May 2025 13:35:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525711; cv=none; b=Yma7+3utjUfABG9a762BCqVBlGjYqTuN86BfzdeCHwqxXrtYXqtpa7uf15/shNwwMdwfslxu4yW7xRRc1LuhooO4Hf+2EgiEpZYQ/UGIgOtFgQOb9ff/lY30O59ueUQLGN+Z1pdMUwusqU+yjf+cXq8W8CFYkwdyhAKRduBWI+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525711; c=relaxed/simple; bh=7UAcyQ8dKsoHD82jua5xfGKBWRpmDXr/0nsbZNJ92Nc=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Elt3QTJi3gmSNfxLHNsLUgW4UOW3EuBc/S9fUDYJNDL5uXmnqd9NuqsE5B0QNKGT/U9jZg9kanYU0ZKxZcxy6I1kNGN+9YOUV0hSREJ1H5Yl4fg5aiNi0M6h6Omy2bXdZ+imgNi1dZ1KZAphOijBHMxSLkBRJstpViwU4c7LM2c= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=xKlsblx8; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="xKlsblx8" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZ5e12407088; Thu, 29 May 2025 08:35:05 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525705; bh=5J/dLICwJ5Y1HVV7l8DTPQWsobQVIaWtOsJ6ROsyyiw=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=xKlsblx8q2eoJ8wO3GLaKYCtj32RHQ6FSkb3i4ofbwQCsgttj+HrND/GBS/KzE9FZ uOt6RLuxqSmDdFmqQKBhh7/v1ro82+9AHO0muVyqz3pIg9EaF+KsKtZoORP3vs8QR7 wtRxn42HuCvdZU+y6/36c6pB+fVWqHla/pEmGwF8= Received: from DFLE112.ent.ti.com (dfle112.ent.ti.com [10.64.6.33]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZ5ff126533 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:05 -0500 Received: from DFLE110.ent.ti.com (10.64.6.31) by DFLE112.ent.ti.com (10.64.6.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:05 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE110.ent.ti.com (10.64.6.31) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:05 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8l1650971; Thu, 29 May 2025 08:35:02 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 05/13] arm64: dts: ti: k3-am654-base-board: Enable "mcu_cpsw" in board file Date: Thu, 29 May 2025 19:04:35 +0530 Message-ID: <20250529133443.1252293-6-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "cpsw3g" device-tree node in the SoC file, namely "k3-am65-mcu.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am654-base-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts b/arch/arm64/bo= ot/dts/ti/k3-am654-base-board.dts index c30425960398..d2632d1f8eb7 100644 --- a/arch/arm64/boot/dts/ti/k3-am654-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am654-base-board.dts @@ -606,6 +606,7 @@ partition@3fe0000 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>; }; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D8D322D4DB; Thu, 29 May 2025 13:35:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525716; cv=none; b=eJTyKUrgNT9/ykkfCe+zj9Uk6ngdtbZUDg+8zk/6xC51Ooe9c68hKDkWsHgpqaqyeo/kqNO4zUlBcheVd2e1oROhT0YfQhTTUpUBhUbi9S9/lVFTTiHnd3a+q65qC4XxI+/Jbn3KmDPtyW26atMCNvhIrzNcv4wPLJMXaeqOww4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525716; c=relaxed/simple; bh=G1o761x7CvwA9g+7zfleh+xX9V2mAumko5AUVzpjSXE=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=RCMA3m3bydYP5HNT+nUVLEl8Lzqbgu30KPO2MfxFO/DLoM+PRPPfhFwu6cqQ4bwSgs2Q8+EXSOQ7JRH4bYLbf3bsn9Hm9j9a+4gzv1a6ylQ2BlIptUuKqwrDuLFIr/ZjkmdhOpGLB3jXnzpo2Q2CSwSS67bE16r5NqlICR7RPUc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=gGTTK7Od; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="gGTTK7Od" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZ9n72407092; Thu, 29 May 2025 08:35:09 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525709; bh=5k6/noStFDeQw/83+ecH4/M9IJRXnI3sitFb7DXoocs=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=gGTTK7OdAE6ow/SvXTXJYkMCn0WG7S9gy1vmbx7vPDClPr7umK6ETSCKKXuFQaF2G Q3jpvwEsAzNFiqGXl/sXW8dGohokZpe04T33NoQFzNv/NxNYpVEHpw8Ttc+Ex2s8Xl jCteA9AaBLOx8cZ/HxP0Pit4T2R3Yda4+pL3zmWU= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZ9eD126584 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:09 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:08 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:08 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8m1650971; Thu, 29 May 2025 08:35:05 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 06/13] arm64: dts: ti: k3-am65-mcu: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:36 +0530 Message-ID: <20250529133443.1252293-7-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/= ti/k3-am65-mcu.dtsi index 7cf1f646500a..cd0b796c5f8f 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi @@ -354,6 +354,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C9E4422DF9A; Thu, 29 May 2025 13:35:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525729; cv=none; b=q+YOlI1hNndqFbURtVMYrRZC5IXPjyYV2xcJG95sZkTiJpiuxKGp5bHa34NZhZV/rd3L1PE6SPSifRmQEJR6sVhWNUYciB8PsYUj7zrTq0kCZIIvW79N0EMH9JAdC+kr378uVUhOPt1J0p3ximVh35h3xZPPjmpOf8nKFl67LvQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525729; c=relaxed/simple; bh=VRMKEb+gVfJ7YJqldJG5FV1DeSjqSvVupB/Jh+4GKbU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=S+suw9q6jHDN8hlvgmKNgsy9FIJ7qiunUxsZCnwFcvQEddPGxDIpSkA5yO1VqA++sIX/nFW/Eju0cC+xWDHYEWYlPXCOJqKHvduwQ0eSunZvjSHyQON2l1ZYrn6x1KIw4sZEpPsSk44Ai5LWsus34H7v01UZ+mtJ4Bli0ug8Zhs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=hpkAQuZ8; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="hpkAQuZ8" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZCd13591393; Thu, 29 May 2025 08:35:12 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525712; bh=uOC+4F+xI+7Hfd/sfb4gzyY83VeimMV87ws6zdQWNRQ=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=hpkAQuZ8HaRC4VAzlaf4blmdL1lboNzH5kfJEsVvBqt8/o6eBJp0mrLrxayYPM4Dx SZUgzQQrh21sl8nxOBoP2/OGEDP04mK69enGpiKGCyg7b1Cmxk3CJlnVCbggvCL+CB ljCMkjbic9EMIr6wZZirNj/QN0OECDH4DJPuGXbk= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZCEj2202068 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:12 -0500 Received: from DLEE115.ent.ti.com (157.170.170.26) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:12 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE115.ent.ti.com (157.170.170.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:11 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8n1650971; Thu, 29 May 2025 08:35:09 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 07/13] arm64: dts: ti: iot2050-common: Remove redundant "mcu_cpsw" node status Date: Thu, 29 May 2025 19:04:37 +0530 Message-ID: <20250529133443.1252293-8-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Now that the SoC file "k3-am65-mcu.dtsi" disables the "mcu_cpsw" node by default, following the existing convention of disabling nodes in the SoC file, remove the redundant section for disabling the "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi | 4 ---- 1 file changed, 4 deletions(-) diff --git a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi b/arch/arm6= 4/boot/dts/ti/k3-am65-iot2050-common.dtsi index e5136ed94765..48e740eb0088 100644 --- a/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi +++ b/arch/arm64/boot/dts/ti/k3-am65-iot2050-common.dtsi @@ -475,10 +475,6 @@ &main_i2c3 { #size-cells =3D <0>; }; =20 -&mcu_cpsw { - status =3D "disabled"; -}; - &sdhci1 { status =3D "okay"; pinctrl-names =3D "default"; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E0648227BB6; Thu, 29 May 2025 13:35:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525722; cv=none; b=NdhtDnc6UbiIyMmbZZUiN1gfe6wdEOTr6ileltLGKgGuBuRsGGDO+8MF8jDOLZdyb4cDANlWvvEizYutcensHGvBaLgZtS+p9iABgAZCaVw/tYDRXi8gNctw3NfJLfFzPnMceu3ET/A7ODncg3d0dQy/mf2vGGfyBcK4fiNge9U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525722; c=relaxed/simple; bh=mxYwWd/9uIeUWgMSTogDHl0/0FX0rUSDGM12IDUcVpY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=ajQ1XmwH6F/TTr6BFp2cMbGDA2O4hEjbaGnLE6skY8GxmbpgzBG4cveVffBzM20sXcC4lH3bR/EraadxpSvfPq/Wml+rLBrv17qygH/q+PL+mkJnX9TuadW5eYJ1PrZYO6d5NtmyCwsknw/sCkHzYTO2FTak1481y0nbVFvHoOk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pCk+iWLS; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pCk+iWLS" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZFNJ3532941; Thu, 29 May 2025 08:35:15 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525715; bh=yx1V3FDCa2PJZt0KPoKs6lMJ44AVNFuwqQaT8iuG26g=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pCk+iWLS+iqz4hJqVRHj1SrTRatMSTwY1H7Ge1gvUsj2Ywwtpxw/wFu8e05wbfAY2 bJnr/ER7zrRY8q/2dUj9blOhnJOYW6aCJRG2o0pJMB56tbcBBhXvcEpP4v2p6rxFbI kUuWnRDaH4ucosclefc9nqPoWsTFs+oINy5NhivA= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZFke064269 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:15 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:15 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:15 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8o1650971; Thu, 29 May 2025 08:35:12 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 08/13] arm64: dts: ti: k3-j7200-common-proc-board: Enable "mcu_cpsw" in board file Date: Thu, 29 May 2025 19:04:38 +0530 Message-ID: <20250529133443.1252293-9-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "mcu_cpsw" device-tree node in the SoC file, namely "k3-j7200-mcu-wakeup.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j7200-common-proc-board.dts index f684ce6ad9ad..021cdeb84ad1 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j7200-common-proc-board.dts @@ -321,6 +321,7 @@ &wkup_gpio0 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot01.ext.ti.com (lelvem-ot01.ext.ti.com [198.47.23.234]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CFFF922D7B9; Thu, 29 May 2025 13:35:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.234 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525725; cv=none; b=Ye22RfIspef8KZ+Tl1a/QGgBo7gO2c1ueEt5+xt7VOb2ggBankGbxWU658lsKAjF6Fm5wu5Pue39A1fzdDKPhEmkgq396sxbz3l4yjiYLya+s5b/RGBXJv0VrKUHPV6P7ZS6haRqT95Ro4JJD3IrxksyhVU8N3zzWmL627ZaOXY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525725; c=relaxed/simple; bh=c+L+erR+j3eIiHx7zBeFYR8Apd6DIP/uMkxtJZRK7h8=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Db2NP8WzAyqWacCEOKJl5SOKdhr9ylt2mLFfLohqZSU135ddmjjQKwuq0dqf8rGKnK2fqWbukpV7YjtTx7cgRAPAHnPjpsRAQIPEkB9IjTJL/8Ip8PI2K9ErPZ7vm/6xwcdC0ikoqvuEkQn0trZpkGuBxnY+u1+vNgNn6FaHp4I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=fxdg8e4r; arc=none smtp.client-ip=198.47.23.234 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="fxdg8e4r" Received: from fllvem-sh03.itg.ti.com ([10.64.41.86]) by lelvem-ot01.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZJUC3532957; Thu, 29 May 2025 08:35:19 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525719; bh=v51QyjN1wMrH5TRcc7+b3a/r/Csd2hSWT/chYr91cIY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=fxdg8e4rzlaSiCv6Ml3Z1EkRmwxYk1C0CaTxULcqH50Ot1evM9RCO3JEAUj/ywC9t DgkXRdem0NR4hDlS1LV5he6sl86ndRyz2pwv+qPnj6rwBIs52wNdHn5GUF00shK1Kt ktDbFTOBd4N92JmKi6NXXnJN/EMNQfbBb5jrWx+I= Received: from DLEE102.ent.ti.com (dlee102.ent.ti.com [157.170.170.32]) by fllvem-sh03.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZJOn126670 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:19 -0500 Received: from DLEE107.ent.ti.com (157.170.170.37) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:18 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE107.ent.ti.com (157.170.170.37) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:19 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8p1650971; Thu, 29 May 2025 08:35:16 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 09/13] arm64: dts: ti: k3-j7200-mcu-wakeup: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:39 +0530 Message-ID: <20250529133443.1252293-10-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j7200-mcu-wakeup.dtsi index 56ab144fea07..604295092d06 100644 --- a/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j7200-mcu-wakeup.dtsi @@ -432,6 +432,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B455222F155; Thu, 29 May 2025 13:35:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525734; cv=none; b=J1bIRyTorUb4gEr0kHOSxuanl99AQlIN1WiJB48duTCqw983d9kbK8qZfpyv1ozgjmtqCHV2PL5zipt4lisBG4FFJzgoEI51d3GbynznSORWMa4fR55kI9ZADt76cdb2HDnmllVSlXQyBWLDFrBSJCfAed94Pt5UlwtmVFp3Bos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525734; c=relaxed/simple; bh=hiUmzvR9wd21wMIX4TneN1+10ZETZbFZZPtISiaR700=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=al7cPaW9SWRmBNR6M/SMtc0IKU2xMkqhTU9fyE9Q45H0/sqRo5teUudqZ8mWOwivwcZ0fezvbZB8YX/M2syBVWztpLQ+x/9zU5gmC1CBOmNEL/3RX9D3pJnlvlRKz6ZMLmUzgjyc5wXDbB4RxUNPfrAHtkJbgaQn6412nvwEFs0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=GAINMXc0; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="GAINMXc0" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZNgP3591405; Thu, 29 May 2025 08:35:23 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525723; bh=pukPZy5VoqX0TJ034jS2scg1gi0D3AIKIU4vdYHqhGg=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=GAINMXc0q+1mt8MDgvT7FucLD0kEiRwNApx0M8xC//25VS0jUELtoEj7d78tZmnBP oVMsnEXaT+PL2VRjY5y+8DfhGMXZaHOcHnZHYx7otC0RXKHWvkl+k5E47m4Rd5wONV a+nzpy0rAVaTzNUvErbJ3Uy45o0MhJ6mHNwPPwNM= Received: from DFLE100.ent.ti.com (dfle100.ent.ti.com [10.64.6.21]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZNLB2202152 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:23 -0500 Received: from DFLE105.ent.ti.com (10.64.6.26) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:22 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DFLE105.ent.ti.com (10.64.6.26) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:22 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8q1650971; Thu, 29 May 2025 08:35:19 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 10/13] arm64: dts: ti: k3-j721e-common-proc-board: Enable "mcu_cpsw" in board file Date: Thu, 29 May 2025 19:04:40 +0530 Message-ID: <20250529133443.1252293-11-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "mcu_cpsw" device-tree node in the SoC file, namely "k3-j721e-mcu-wakeup.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts b/arch/a= rm64/boot/dts/ti/k3-j721e-common-proc-board.dts index 45311438315f..eda85dafb794 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721e-common-proc-board.dts @@ -767,6 +767,7 @@ exp5: gpio@20 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D35101C3F36; Thu, 29 May 2025 13:35:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525732; cv=none; b=S4XJneqDs3Mh2WdYtJQX3CvrwlUO2gzco5UBFIGkk8mh6TwTDPwZvDPsVO8fuhT04JnX72wwbbhEy5tEeGP3mKrrGqpH9gwLaq6SkYJf3DvaNPXOIJ7usvy4uK0Liu1Rkn/ug0Ai600rp+ajtXLOs1Yb2G8Y5qfWeIFAhvs3KVQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525732; c=relaxed/simple; bh=8QBk7WwTfAz3x55hQUgW8LQ5an8ehM8R8JsYc5PDDNI=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=CnB+Bz57eXraozLN++EBlkhB1LonZgWDqY8Aoz8s0LO/+T/BNdOk2KYeyhuYtQy53rGtNUXdLBvUMdZjCbvIHllhwDlZHnVItrRSczB/ZWK28Hr4bNAt79DSLMG3jzEs92C1m1WDN+fqX1L7UP2ujA8Hzug1uuv1lRD+G+fZdaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=I+QuMIbF; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="I+QuMIbF" Received: from lelvem-sh01.itg.ti.com ([10.180.77.71]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZQ3n2407099; Thu, 29 May 2025 08:35:26 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525726; bh=6H7HUuEynzu+SANLoTLLFVnfS6/zJMqCGCZ1MLeRFPk=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=I+QuMIbFXtIrqhCEH/prQJ5UD13NupJteUXlfVOWBScmgGVlY+FD4rEZDgJCWgb6q qU0OT+gOH6Qb3KX2U5h046e+3dfDXShyYkW0C1VhjGVN01Nk9WcgSkynQUDEM1y6eX tCx0HH8fcRNpE+gEdLFdmjtMyjKqw1e4Jr6U5T/g= Received: from DLEE100.ent.ti.com (dlee100.ent.ti.com [157.170.170.30]) by lelvem-sh01.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZQH2064384 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:26 -0500 Received: from DLEE103.ent.ti.com (157.170.170.33) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:26 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE103.ent.ti.com (157.170.170.33) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:26 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8r1650971; Thu, 29 May 2025 08:35:23 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 11/13] arm64: dts: ti: k3-j721e-mcu-wakeup: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:41 +0530 Message-ID: <20250529133443.1252293-12-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi b/arch/arm64/b= oot/dts/ti/k3-j721e-mcu-wakeup.dtsi index b02142b2b460..dd923540ca0a 100644 --- a/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721e-mcu-wakeup.dtsi @@ -551,6 +551,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A48C22F395; Thu, 29 May 2025 13:35:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525735; cv=none; b=K6XQ1b3ZO1MNiaiv1Ns9e8cgf4f058wKtyzv45eX1DUD1mwQxT1R/iPNVbAvWIRgT4eSyGbXxRs5yfPDUfjBT2svrxxywhLYO2iP4QJHrq2tB78bwjJH1lwMBoOuyi9lQmRO92WZr7OhiPRPFvJD4axpzH/9lrt8IcSO7PRbG80= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525735; c=relaxed/simple; bh=Jl8jKgyvmUwie2oJ+xaaceBpOSdi6hsNCsuZP3TDpVQ=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=DNy64ztD1S62Bsrp5TnXUahVonSgT5sVFUbXFnrVcR68GEpUknEUADTQVEqHZpYRPiIFkECk6xGaPBLnpyxl9OONoAIeHqL5Ivcx+i0gGxYKLp5bjuyqs3P1JoLP7AfB+nxpWJ2flHifDhQy6VNTTIpeG7IvjniwUBQhO15uGtM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=RrlRSEJ+; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="RrlRSEJ+" Received: from fllvem-sh04.itg.ti.com ([10.64.41.54]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZUem3591417; Thu, 29 May 2025 08:35:30 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525730; bh=Hcaf0i1yzSnlXG0VMMe4a71gA+Cd90Mc4SySd7/rJBY=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=RrlRSEJ+s1PlrKUjakvJMGsJ0wRfuBt72A3wyQ/9l7LxSGD4EIqH3YD5Ej44wXzSy TdahktdyAs8Ir8ro1QD1VMxglsvKZCo4BUOTM65zYRy21yoFrpsJ3vOqYsF67zuGJc 4tFtfZBjDkCTD38hRvaYx3QWyKfiVHDqWeuSmLb4= Received: from DLEE113.ent.ti.com (dlee113.ent.ti.com [157.170.170.24]) by fllvem-sh04.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZUnm180349 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:30 -0500 Received: from DLEE109.ent.ti.com (157.170.170.41) by DLEE113.ent.ti.com (157.170.170.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:29 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE109.ent.ti.com (157.170.170.41) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:29 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8s1650971; Thu, 29 May 2025 08:35:26 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 12/13] arm64: dts: ti: k3-j721s2-common-proc-board: Enable "mcu_cpsw" in board file Date: Thu, 29 May 2025 19:04:42 +0530 Message-ID: <20250529133443.1252293-13-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" In preparation for disabling "mcu_cpsw" device-tree node in the SoC file, namely "k3-j721s2-mcu-wakeup.dtsi", enable it in the board file. The motivation for this change is that of following the existing convention of disabling nodes in the SoC file and only enabling the required ones in the board file. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts b/arch/= arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts index e2fc1288ed07..a482b3ad5095 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts +++ b/arch/arm64/boot/dts/ti/k3-j721s2-common-proc-board.dts @@ -409,6 +409,7 @@ &main_sdhci1 { }; =20 &mcu_cpsw { + status =3D "okay"; pinctrl-names =3D "default"; pinctrl-0 =3D <&mcu_cpsw_pins_default>, <&mcu_mdio_pins_default>; }; --=20 2.34.1 From nobody Tue Dec 16 14:39:37 2025 Received: from fllvem-ot03.ext.ti.com (fllvem-ot03.ext.ti.com [198.47.19.245]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A77E522A4D5; Thu, 29 May 2025 13:35:37 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.245 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525739; cv=none; b=rgpSntePmSHy09+emyZXpU0stZo493uLTELdxTpLW8rsAHK1w+B4zNopQ1Fh44zqV/jvJeVZ4lVaON015ttE6ZJzJ6ETxRBv/MNUN/Py42HzuC1RPhPLt05OBZWSvoijcLkYGlmMphnDu7BSRLytUYk/AfevkokiGOsLdphxzJ4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748525739; c=relaxed/simple; bh=8W4QUpDgcTW+Xah7t96FXbifwuMnXr0fKIWV2VB2/aU=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=LJ32xv5Bp6zhUdQbIsllUF+3e89rtbapTglxBlUrCmKCoWKyiBZu0J80eOdnR2c6sl5m2aZlJ3k/ClXsQ7xH/PaPLY8Xcp1ePzdsmRr+thnfrFQyRw7GwmHWGg2npTUNsX9Pam9bkafx3GlMqSrBiaYRwuQDQZhEAenSiil52Hs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=TCe6Zrw1; arc=none smtp.client-ip=198.47.19.245 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="TCe6Zrw1" Received: from lelvem-sh02.itg.ti.com ([10.180.78.226]) by fllvem-ot03.ext.ti.com (8.15.2/8.15.2) with ESMTP id 54TDZXvu3591425; Thu, 29 May 2025 08:35:33 -0500 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1748525733; bh=LB8Z0NdebTCSX3P28O31aPVquD8FAYcpb5/udEKYrn4=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=TCe6Zrw1eggZ34MGHhi6X/HAmnKCXcHCrDAeQx0wxHCKI4aZP+hm7oIANlArNWPlT lcwaMVp9e/IdaCvX1fjR6wv1C6LjKaxQvk7+AkiElGINDoIqj6vzv5GQrLG6g509YK wCK+HPcfenKUdpXEpkbYS3taxs0C8Oxijs+4ZJCI= Received: from DLEE105.ent.ti.com (dlee105.ent.ti.com [157.170.170.35]) by lelvem-sh02.itg.ti.com (8.18.1/8.18.1) with ESMTPS id 54TDZX7o2202210 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-SHA256 bits=128 verify=FAIL); Thu, 29 May 2025 08:35:33 -0500 Received: from DLEE102.ent.ti.com (157.170.170.32) by DLEE105.ent.ti.com (157.170.170.35) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Thu, 29 May 2025 08:35:33 -0500 Received: from lelvem-mr05.itg.ti.com (10.180.75.9) by DLEE102.ent.ti.com (157.170.170.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Thu, 29 May 2025 08:35:32 -0500 Received: from uda0492258.dhcp.ti.com (uda0492258.dhcp.ti.com [172.24.227.169]) by lelvem-mr05.itg.ti.com (8.18.1/8.18.1) with ESMTP id 54TDYi8t1650971; Thu, 29 May 2025 08:35:30 -0500 From: Siddharth Vadapalli To: , , , , , CC: , , , , Subject: [PATCH 13/13] arm64: dts: ti: k3-j721s2-mcu-wakeup: Disable "mcu_cpsw" in the SoC file Date: Thu, 29 May 2025 19:04:43 +0530 Message-ID: <20250529133443.1252293-14-s-vadapalli@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529133443.1252293-1-s-vadapalli@ti.com> References: <20250529133443.1252293-1-s-vadapalli@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Following the existing convention of disabling nodes in the SoC file and enabling only the required ones in the board file, disable "mcu_cpsw" node. Signed-off-by: Siddharth Vadapalli --- arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..b5fd012d9564 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -552,6 +552,8 @@ mcu_cpsw: ethernet@46000000 { "tx4", "tx5", "tx6", "tx7", "rx"; =20 + status =3D "disabled"; + ethernet-ports { #address-cells =3D <1>; #size-cells =3D <0>; --=20 2.34.1