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Thu, 29 May 2025 11:17:15 +0000 (GMT) X-AuditID: b6c32a29-566fe7000000223e-8e-6838423a0ae5 Received: from epsmtip1.samsung.com ( [182.195.34.30]) by epsmgms1p1new.samsung.com (Symantec Messaging Gateway) with SMTP id 23.3F.08766.A3248386; Thu, 29 May 2025 20:17:14 +0900 (KST) Received: from bose.samsungds.net (unknown [107.108.83.9]) by epsmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250529111712epsmtip1c3473e86dd73fe7f2cb4a048b21fa309~D_1cifmF32102821028epsmtip1F; Thu, 29 May 2025 11:17:11 +0000 (GMT) From: Raghav Sharma To: krzk@kernel.org, s.nawrocki@samsung.com, cw00.choi@samsung.com, alim.akhtar@samsung.com, mturquette@baylibre.com, sboyd@kernel.org, robh@kernel.org, conor+dt@kernel.org, richardcochran@gmail.com, sunyeal.hong@samsung.com, shin.son@samsung.com Cc: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, chandan.vn@samsung.com, karthik.sun@samsung.com, dev.tailor@samsung.com, Raghav Sharma Subject: [PATCH v3 3/4] clk: samsung: exynosautov920: add block hsi2 clock support Date: Thu, 29 May 2025 16:56:39 +0530 Message-Id: <20250529112640.1646740-4-raghav.s@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250529112640.1646740-1-raghav.s@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFupjkeLIzCtJLcpLzFFi42LZdlhJTtfKySLDoO2DhcWDedvYLCZ8ibBY s/cck8X1L89ZLe7tWMZuMf/IOVaLxhlvmCzOn9/AbrHp8TVWi48991gtLu+aw2Yx4/w+JouL p1wtji0Qs/i+8g6jxZEzL5gt/u/ZwW5x+E07q8W/axtZLCYfX8tq0bRsPZODqMf7G63sHjtn 3WX32LSqk81j85J6j74tqxg9Pm+SC2CL4rJJSc3JLEst0rdL4Mq4vug8W8F85YqJX1tYGhiP yHYxcnBICJhInG2S7GLk4hAS2M0ocfjMIbYuRk6guITEvv+/GSFsYYmV/56zQxS9ZZTYfKqF BSTBJqAlcWX7OzaQhIhAF5PEuX+vWEAcZoGdTBJtj7exg1QJCwRJ7Js8nxXEZhFQlbj99AQT yGpeAWuJ4wc1IDbIS+w/eJYZxOYUsJG4e/M52AIhoJKP28+AxXkFBCVOznwCFmcGqm/eOpt5 AqPALCSpWUhSCxiZVjFKphYU56bnFhsWGOallusVJ+YWl+al6yXn525iBEeZluYOxu2rPugd YmTiYDzEKMHBrCTC22RvliHEm5JYWZValB9fVJqTWnyIUZqDRUmcV/xFb4qQQHpiSWp2ampB ahFMlomDU6qBSfZSSKLVjfSHqky3WJg0jsXIRkqXSJy4zNbwv+/En/SiGVe3rXh+VO2QVaeq mCfvX6/S5q/ZkvIX2CoeLFok3f+JZc8cCw+TfR9VpnwX6mKZmMes/XPWwpdZN2/ILU8VXB2t LzTdaNE0n6p12v5267d9Ys4sWHzMwejBxaJKrTVCjlp5Jmxn98u2tfhvlhae+sZdfp6weut1 oW3pB3N2R77XlHZ+3u/4SlSUzXdKa2tGwTu2V7FPbBSn/H3Lf8rh2772Jv7YZ9NMuMpmhwp2 HzlW/nGhdXiK0N3Gx4rBdRyH/KMsk9sVc6VWHeCqdZRR7Dr6vSxedKOw1OF6gZIW8wurzppV la3+tsa65LkSS3FGoqEWc1FxIgBs+bx7IQMAAA== X-CMS-MailID: 20250529111715epcas5p19a63894e2556d2c8005845e01f67c783 X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-Sendblock-Type: REQ_APPROVE CMS-TYPE: 105P cpgsPolicy: CPGSC10-543,Y X-CFilter-Loop: Reflected X-CMS-RootMailID: 20250529111715epcas5p19a63894e2556d2c8005845e01f67c783 References: <20250529112640.1646740-1-raghav.s@samsung.com> Register compatible and cmu_info data to support clocks. CMU_HSI2, this provides clocks for HSI2 block Signed-off-by: Raghav Sharma Reviewed-by: Alim Akhtar --- drivers/clk/samsung/clk-exynosautov920.c | 72 ++++++++++++++++++++++++ 1 file changed, 72 insertions(+) diff --git a/drivers/clk/samsung/clk-exynosautov920.c b/drivers/clk/samsung= /clk-exynosautov920.c index da4afe8ac2ab..572b6ace14ac 100644 --- a/drivers/clk/samsung/clk-exynosautov920.c +++ b/drivers/clk/samsung/clk-exynosautov920.c @@ -26,6 +26,7 @@ #define CLKS_NR_MISC (CLK_DOUT_MISC_OSC_DIV2 + 1) #define CLKS_NR_HSI0 (CLK_DOUT_HSI0_PCIE_APB + 1) #define CLKS_NR_HSI1 (CLK_MOUT_HSI1_USBDRD + 1) +#define CLKS_NR_HSI2 (CLK_DOUT_HSI2_ETHERNET_PTP + 1) =20 /* ---- CMU_TOP ----------------------------------------------------------= -- */ =20 @@ -1752,6 +1753,74 @@ static const struct samsung_cmu_info hsi1_cmu_info _= _initconst =3D { .clk_name =3D "noc", }; =20 +/* ---- CMU_HSI2 ---------------------------------------------------------= */ + +/* Register Offset definitions for CMU_HSI2 (0x16b00000) */ +#define PLL_LOCKTIME_PLL_ETH 0x0 +#define PLL_CON3_PLL_ETH 0x10c +#define PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER 0x600 +#define PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER 0x610 +#define PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER 0x630 +#define CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET 0x1000 +#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET 0x1800 +#define CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP 0x1804 + +static const unsigned long hsi2_clk_regs[] __initconst =3D { + PLL_LOCKTIME_PLL_ETH, + PLL_CON3_PLL_ETH, + PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_USER, + PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USER, + PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_USER, + CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, + CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET, + CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP, +}; + +static const struct samsung_pll_clock hsi2_pll_clks[] __initconst =3D { + /* CMU_HSI2_PLL */ + PLL(pll_531x, FOUT_PLL_ETH, "fout_pll_eth", "oscclk", + PLL_LOCKTIME_PLL_ETH, PLL_CON3_PLL_ETH, NULL), +}; + +/* List of parent clocks for Muxes in CMU_HSI2 */ +PNAME(mout_clkcmu_hsi2_noc_ufs_user_p) =3D { "oscclk", "dout_clkcmu_hsi2_n= oc_ufs" }; +PNAME(mout_clkcmu_hsi2_ufs_embd_user_p) =3D { "oscclk", "dout_clkcmu_hsi2_= ufs_embd" }; +PNAME(mout_hsi2_ethernet_p) =3D { "fout_pll_eth", "mout_clkcmu_hsi2_ethern= et_user" }; +PNAME(mout_clkcmu_hsi2_ethernet_user_p) =3D { "oscclk", "dout_clkcmu_hsi2_= ethernet" }; + +static const struct samsung_mux_clock hsi2_mux_clks[] __initconst =3D { + MUX(CLK_MOUT_HSI2_NOC_UFS_USER, "mout_clkcmu_hsi2_noc_ufs_user", + mout_clkcmu_hsi2_noc_ufs_user_p, PLL_CON0_MUX_CLKCMU_HSI2_NOC_UFS_USE= R, 4, 1), + MUX(CLK_MOUT_HSI2_UFS_EMBD_USER, "mout_clkcmu_hsi2_ufs_embd_user", + mout_clkcmu_hsi2_ufs_embd_user_p, PLL_CON0_MUX_CLKCMU_HSI2_UFS_EMBD_U= SER, 4, 1), + MUX(CLK_MOUT_HSI2_ETHERNET, "mout_hsi2_ethernet", + mout_hsi2_ethernet_p, CLK_CON_MUX_MUX_CLK_HSI2_ETHERNET, 0, 1), + MUX(CLK_MOUT_HSI2_ETHERNET_USER, "mout_clkcmu_hsi2_ethernet_user", + mout_clkcmu_hsi2_ethernet_user_p, PLL_CON0_MUX_CLKCMU_HSI2_ETHERNET_U= SER, 4, 1), +}; + +static const struct samsung_div_clock hsi2_div_clks[] __initconst =3D { + DIV(CLK_DOUT_HSI2_ETHERNET, "dout_hsi2_ethernet", + "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET, + 0, 4), + DIV(CLK_DOUT_HSI2_ETHERNET_PTP, "dout_hsi2_ethernet_ptp", + "mout_hsi2_ethernet", CLK_CON_DIV_DIV_CLK_HSI2_ETHERNET_PTP, + 0, 4), +}; + +static const struct samsung_cmu_info hsi2_cmu_info __initconst =3D { + .pll_clks =3D hsi2_pll_clks, + .nr_pll_clks =3D ARRAY_SIZE(hsi2_pll_clks), + .mux_clks =3D hsi2_mux_clks, + .nr_mux_clks =3D ARRAY_SIZE(hsi2_mux_clks), + .div_clks =3D hsi2_div_clks, + .nr_div_clks =3D ARRAY_SIZE(hsi2_div_clks), + .nr_clk_ids =3D CLKS_NR_HSI2, + .clk_regs =3D hsi2_clk_regs, + .nr_clk_regs =3D ARRAY_SIZE(hsi2_clk_regs), + .clk_name =3D "noc", +}; + static int __init exynosautov920_cmu_probe(struct platform_device *pdev) { const struct samsung_cmu_info *info; @@ -1779,6 +1848,9 @@ static const struct of_device_id exynosautov920_cmu_o= f_match[] =3D { }, { .compatible =3D "samsung,exynosautov920-cmu-hsi1", .data =3D &hsi1_cmu_info, + }, { + .compatible =3D "samsung,exynosautov920-cmu-hsi2", + .data =3D &hsi2_cmu_info, }, { } }; --=20 2.34.1