From nobody Tue Dec 16 22:18:30 2025 Received: from mail.loongson.cn (mail.loongson.cn [114.242.206.163]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 718571D61AA; Thu, 29 May 2025 01:11:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=114.242.206.163 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748481077; cv=none; b=HU03JTpCfUKVHpCwIq2ljqSXS00kTK+Q8kfnU9FJ1cTe0U59vDe9QwXzshnFZhmqHz/XQ+pyPVSljf/tQ98ZtCh8gf+IWeVETs8+3OXRNpu5sefR/dZAkLdoeOJx92mUiwknMnPd8pmH6sLJ7FTwEp9uZ616IXEnP80VZk0MtP0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748481077; c=relaxed/simple; bh=hrnGReoCX4OFCk2gE+9Qx1LGtsJg+c/g8AN4jQ9n+v8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=Rw5WzsmxfHtpBMLL1hLGoEWwqtwYzGctTAar0Is+t+zRfbPoYPFAl8LgvHxCib3CQmwhCIaNViZU5jPnAMBOVtByjLZcMDCOqCFSbUN0qkRXeVJQFTlatAqVya+SM5HGkVf9Pt+BJ/LODA6rAPgXaIugGncbGCKKNciCCkf1OPA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn; spf=pass smtp.mailfrom=loongson.cn; arc=none smtp.client-ip=114.242.206.163 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=loongson.cn Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=loongson.cn Received: from loongson.cn (unknown [10.2.5.213]) by gateway (Coremail) with SMTP id _____8AxQK0xtDdouB4BAQ--.3547S3; Thu, 29 May 2025 09:11:13 +0800 (CST) Received: from localhost.localdomain (unknown [10.2.5.213]) by front1 (Coremail) with SMTP id qMiowMCx_cYmtDdoR0P5AA--.57458S5; Thu, 29 May 2025 09:11:12 +0800 (CST) From: Bibo Mao To: Tianrui Zhao , Huacai Chen , Xianglai Li Cc: kvm@vger.kernel.org, loongarch@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH 3/5] LoongArch: KVM: Use standard bitops API with eiointc Date: Thu, 29 May 2025 09:11:00 +0800 Message-Id: <20250529011102.378749-4-maobibo@loongson.cn> X-Mailer: git-send-email 2.39.3 In-Reply-To: <20250529011102.378749-1-maobibo@loongson.cn> References: <20250529011102.378749-1-maobibo@loongson.cn> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: qMiowMCx_cYmtDdoR0P5AA--.57458S5 X-CM-SenderInfo: xpdruxter6z05rqj20fqof0/ X-Coremail-Antispam: 1Uk129KBjDUn29KB7ZKAUJUUUUU529EdanIXcx71UUUUU7KY7 ZEXasCq-sGcSsGvfJ3UbIjqfuFe4nvWSU5nxnvy29KBjDU0xBIdaVrnUUvcSsGvfC2Kfnx nUUI43ZEXa7xR_UUUUUUUUU== Content-Type: text/plain; charset="utf-8" Standard bitops APIs such test_bit() is used here, rather than manually calculate the offset and mask. Also use non-atomic API __set_bit() and __clear_bit() rather than set_bit() and clear_bit(), since global spinlock is held already. Signed-off-by: Bibo Mao --- arch/loongarch/kvm/intc/eiointc.c | 27 +++++++++++---------------- 1 file changed, 11 insertions(+), 16 deletions(-) diff --git a/arch/loongarch/kvm/intc/eiointc.c b/arch/loongarch/kvm/intc/ei= ointc.c index 0b648c56b0c3..b3aa6e305a18 100644 --- a/arch/loongarch/kvm/intc/eiointc.c +++ b/arch/loongarch/kvm/intc/eiointc.c @@ -9,7 +9,7 @@ =20 static void eiointc_set_sw_coreisr(struct loongarch_eiointc *s) { - int ipnum, cpu, irq_index, irq_mask, irq, cpuid; + int ipnum, cpu, irq, cpuid; struct kvm_vcpu *vcpu; =20 for (irq =3D 0; irq < EIOINTC_IRQS; irq++) { @@ -18,8 +18,6 @@ static void eiointc_set_sw_coreisr(struct loongarch_eioin= tc *s) ipnum =3D count_trailing_zeros(ipnum); ipnum =3D (ipnum >=3D 0 && ipnum < 4) ? ipnum : 0; } - irq_index =3D irq / 32; - irq_mask =3D BIT(irq & 0x1f); =20 cpuid =3D s->coremap.reg_u8[irq]; vcpu =3D kvm_get_vcpu_by_cpuid(s->kvm, cpuid); @@ -27,16 +25,16 @@ static void eiointc_set_sw_coreisr(struct loongarch_eio= intc *s) continue; =20 cpu =3D vcpu->vcpu_id; - if (!!(s->coreisr.reg_u32[cpu][irq_index] & irq_mask)) - set_bit(irq, s->sw_coreisr[cpu][ipnum]); + if (test_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu])) + __set_bit(irq, s->sw_coreisr[cpu][ipnum]); else - clear_bit(irq, s->sw_coreisr[cpu][ipnum]); + __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); } } =20 static void eiointc_update_irq(struct loongarch_eiointc *s, int irq, int l= evel) { - int ipnum, cpu, found, irq_index, irq_mask; + int ipnum, cpu, found; struct kvm_vcpu *vcpu; struct kvm_interrupt vcpu_irq; =20 @@ -48,19 +46,16 @@ static void eiointc_update_irq(struct loongarch_eiointc= *s, int irq, int level) =20 cpu =3D s->sw_coremap[irq]; vcpu =3D kvm_get_vcpu(s->kvm, cpu); - irq_index =3D irq / 32; - irq_mask =3D BIT(irq & 0x1f); - if (level) { /* if not enable return false */ - if (((s->enable.reg_u32[irq_index]) & irq_mask) =3D=3D 0) + if (!test_bit(irq, (unsigned long *)s->enable.reg_u32)) return; - s->coreisr.reg_u32[cpu][irq_index] |=3D irq_mask; + __set_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]); found =3D find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS); - set_bit(irq, s->sw_coreisr[cpu][ipnum]); + __set_bit(irq, s->sw_coreisr[cpu][ipnum]); } else { - s->coreisr.reg_u32[cpu][irq_index] &=3D ~irq_mask; - clear_bit(irq, s->sw_coreisr[cpu][ipnum]); + __clear_bit(irq, (unsigned long *)s->coreisr.reg_u32[cpu]); + __clear_bit(irq, s->sw_coreisr[cpu][ipnum]); found =3D find_first_bit(s->sw_coreisr[cpu][ipnum], EIOINTC_IRQS); } =20 @@ -110,8 +105,8 @@ void eiointc_set_irq(struct loongarch_eiointc *s, int i= rq, int level) unsigned long flags; unsigned long *isr =3D (unsigned long *)s->isr.reg_u8; =20 - level ? set_bit(irq, isr) : clear_bit(irq, isr); spin_lock_irqsave(&s->lock, flags); + level ? __set_bit(irq, isr) : __clear_bit(irq, isr); eiointc_update_irq(s, irq, level); spin_unlock_irqrestore(&s->lock, flags); } --=20 2.39.3