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Thu, 29 May 2025 09:53:52 -0700 (PDT) From: David Lechner Date: Thu, 29 May 2025 11:53:18 -0500 Subject: [PATCH v3 1/3] dt-bindings: pwm: adi,axi-pwmgen: update documentation link Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-pwm-axi-pwmgen-add-external-clock-v3-1-5d8809a7da91@baylibre.com> References: <20250529-pwm-axi-pwmgen-add-external-clock-v3-0-5d8809a7da91@baylibre.com> In-Reply-To: <20250529-pwm-axi-pwmgen-add-external-clock-v3-0-5d8809a7da91@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=958; i=dlechner@baylibre.com; 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Signed-off-by: David Lechner --- Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Do= cumentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml index 45e112d0efb4663bc7fbb3a25a12d66aa8b7492d..bc44381692054f647a160a6573d= ae4cff2ee3f31 100644 --- a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml @@ -14,7 +14,7 @@ description: The Analog Devices AXI PWM generator can generate PWM signals with variable pulse width and period. =20 - https://wiki.analog.com/resources/fpga/docs/axi_pwm_gen + https://analogdevicesinc.github.io/hdl/library/axi_pwm_gen/index.html =20 allOf: - $ref: pwm.yaml# --=20 2.43.0 From nobody Fri Dec 19 11:29:18 2025 Received: from mail-ot1-f47.google.com (mail-ot1-f47.google.com [209.85.210.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6C90822D9F4 for ; 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Thu, 29 May 2025 09:53:53 -0700 (PDT) Received: from [127.0.1.1] ([2600:8803:e7e4:1d00:928b:5d5c:6cd9:1a4]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-735af82d2b8sm303265a34.3.2025.05.29.09.53.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 09:53:53 -0700 (PDT) From: David Lechner Date: Thu, 29 May 2025 11:53:19 -0500 Subject: [PATCH v3 2/3] dt-bindings: pwm: adi,axi-pwmgen: fix clocks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-pwm-axi-pwmgen-add-external-clock-v3-2-5d8809a7da91@baylibre.com> References: <20250529-pwm-axi-pwmgen-add-external-clock-v3-0-5d8809a7da91@baylibre.com> In-Reply-To: <20250529-pwm-axi-pwmgen-add-external-clock-v3-0-5d8809a7da91@baylibre.com> To: Michael Hennerich , =?utf-8?q?Nuno_S=C3=A1?= , Trevor Gamblin , =?utf-8?q?Uwe_Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Lechner Cc: linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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The AXI PWMGEN IP block has a compile option ASYNC_CLK_EN that allows the use of an external clock for the PWM output separate from the AXI clock that runs the peripheral. This was missed in the original bindings and so users were writing dts files where the one and only clock specified would be the external clock, if there was one, incorrectly missing the separate AXI clock. The correct bindings are that the AXI clock is always required and the external clock is optional (must be given only when HDL compile option ASYNC_CLK_EN=3D1). Cc: stable@vger.kernel.org Fixes: 1edf2c2a2841 ("dt-bindings: pwm: Add AXI PWM generator") Signed-off-by: David Lechner Reviewed-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml | 13 +++++++++++= -- 1 file changed, 11 insertions(+), 2 deletions(-) diff --git a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml b/Do= cumentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml index bc44381692054f647a160a6573dae4cff2ee3f31..e4c2d5186dedb18701af74bbc95= 7b82a2b0f8737 100644 --- a/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml +++ b/Documentation/devicetree/bindings/pwm/adi,axi-pwmgen.yaml @@ -30,11 +30,19 @@ properties: const: 3 =20 clocks: - maxItems: 1 + minItems: 1 + maxItems: 2 + + clock-names: + minItems: 1 + items: + - const: axi + - const: ext =20 required: - reg - clocks + - clock-names =20 unevaluatedProperties: false =20 @@ -43,6 +51,7 @@ examples: pwm@44b00000 { compatible =3D "adi,axi-pwmgen-2.00.a"; reg =3D <0x44b00000 0x1000>; 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In most cases, the HDL for this IP block is compiled with the default ASYNC_CLK_EN=3D1. With this option, there is a separate external clock that drives the PWM output separate from the peripheral clock. So the driver should be enabling the "axi" clock to power the peripheral and the "ext" clock to drive the PWM output. When ASYNC_CLK_EN=3D0, the "axi" clock is also used to drive the PWM output and there is no "ext" clock. Previously, if there was a separate external clock, users had to specify only the external clock and (incorrectly) omit the AXI clock in order to get the correct operating frequency for the PWM output. The devicetree bindings are updated to fix this shortcoming and this patch changes the driver to match the new bindings. To preserve compatibility with any existing dtbs that specify only one clock, we don't require the clock name on the first clock. Cc: stable@vger.kernel.org Fixes: 41814fe5c782 ("pwm: Add driver for AXI PWM generator") Acked-by: Nuno S=C3=A1 Reviewed-by: Trevor Gamblin Signed-off-by: David Lechner --- drivers/pwm/pwm-axi-pwmgen.c | 23 ++++++++++++++++++++--- 1 file changed, 20 insertions(+), 3 deletions(-) diff --git a/drivers/pwm/pwm-axi-pwmgen.c b/drivers/pwm/pwm-axi-pwmgen.c index 4337c8f5acf055fc87dc134f2a70b99b0cb5ede6..60dcd354237316bced2d951b7f0= b116c8291bb0d 100644 --- a/drivers/pwm/pwm-axi-pwmgen.c +++ b/drivers/pwm/pwm-axi-pwmgen.c @@ -257,7 +257,7 @@ static int axi_pwmgen_probe(struct platform_device *pde= v) struct regmap *regmap; struct pwm_chip *chip; struct axi_pwmgen_ddata *ddata; - struct clk *clk; + struct clk *axi_clk, *clk; void __iomem *io_base; int ret; =20 @@ -280,9 +280,26 @@ static int axi_pwmgen_probe(struct platform_device *pd= ev) ddata =3D pwmchip_get_drvdata(chip); ddata->regmap =3D regmap; =20 - clk =3D devm_clk_get_enabled(dev, NULL); + /* + * Using NULL here instead of "axi" for backwards compatibility. There + * are some dtbs that don't give clock-names and have the "ext" clock + * as the one and only clock (due to mistake in the original bindings). + */ + axi_clk =3D devm_clk_get_enabled(dev, NULL); + if (IS_ERR(axi_clk)) + return dev_err_probe(dev, PTR_ERR(axi_clk), "failed to get axi clock\n"); + + clk =3D devm_clk_get_optional_enabled(dev, "ext"); if (IS_ERR(clk)) - return dev_err_probe(dev, PTR_ERR(clk), "failed to get clock\n"); + return dev_err_probe(dev, PTR_ERR(clk), "failed to get ext clock\n"); + + /* + * If there is no "ext" clock, it means the HDL was compiled with + * ASYNC_CLK_EN=3D0. In this case, the AXI clock is also used for the + * PWM output clock. + */ + if (!clk) + clk =3D axi_clk; =20 ret =3D devm_clk_rate_exclusive_get(dev, clk); if (ret) --=20 2.43.0