From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 72ECF28E612 for ; Thu, 29 May 2025 11:33:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.50 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518394; cv=none; b=EbZdow7FE0jV/TrmPAAQU+gzcLRLqqQCVgdlB7tAvBFJYaQzIhldKxmGLgfw2loIDTo9kdDzKi5qCEwhduA46NCG7P1luStImIs20yIddsbpdIzSZDofJEDJrDcLGt/qsi7rsOw+kSiWwanZrH70oY+5sRttFF9CrPX3S8h8RZg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518394; c=relaxed/simple; bh=0kXgfqs3fyfI9WK4w4EvE8F1GbYyXHS3q4H/r0Lm5Zo=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=J+7LOP7lyH3dgqAuFsr7zHIrljWyygst26BOycgsRKpC/K8I0WqTcFyorURj/XRHHo31cvOyXpSOHAldu97A5lMssV8iWQkICZ5dbX9UZ7CBid9/leH1kxtD0bFdegVHr5wdrM+KnceW1CKI/skDXBzHoc6971/Dj5GeRrRXUmI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=mbFxL+1x; arc=none smtp.client-ip=209.85.221.50 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="mbFxL+1x" Received: by mail-wr1-f50.google.com with SMTP id ffacd0b85a97d-3a3771c0f8cso460871f8f.3 for ; Thu, 29 May 2025 04:33:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518390; x=1749123190; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=9ENKrydK9y6Ncy6QzWlN/lVHecxyLZuFBTl1oby0dHM=; b=mbFxL+1x+Te6aGoo7tX4KZmXIgjnXfULFNTZ17T/fLPeaQqGo5sdpRmZvChr2udf8/ aixxQcHCfCb+8UflpeffXv1RIxWAYARzHllhPnVXptVsF3IB7ktM5MIfefuWo9U8K+ZC sFGMXC1yspkIaCcGsSjSTN73UzlWqfAZejPGOpZm2Vvp3tw6+W0cPHhHKPA8BKnD7Pc3 kIIbMOmpHpywBcHPdmgG1XnfdvHpfN/TgCzy1sPxNJRP4+kiWNh/AD6IcSUjge3dbayA xgUC9ZUKTPZYVS2rlDG6/2eLmVO9Y/6ct/a2BNvAA/3flfYgX21W8Oy0R1BfryUZhLdu TU3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518390; x=1749123190; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9ENKrydK9y6Ncy6QzWlN/lVHecxyLZuFBTl1oby0dHM=; b=Aa+HahLFTlv0fVB6Q49DHl8b2SW75JBYkejMIhulYTIxSLj/TK74Ug9vW6TQUM62af WNMI3H42KujyPEB9M8yQayuENBQX2EY5Tw+3sOmInGUwW4w9ELCcE4TYcJKDcx7tAKJ3 PESQ9D0HWKHBsgyTmGHabN0ERvlWknPz7N37igEDZ7nswaeriRnvvTxUbPoRdzcs5i9D 7qhGPd1Clv6ThtxjKw5TeyaD0iPWKNxFVp9dWKxK9dQvCekqjIk73Wfxc8jmsQFQQ6TS D6uWnxb3P958rTHHH6VRzbSZvLCqft8rLWeQFHZPVg6PbYt2umt6ia6+nS5FTZagQA+g FgCQ== X-Forwarded-Encrypted: i=1; AJvYcCWFHewVAJ7ZIYFYIqBzBgNHMyVTwB4oPq43FQljc35z0cgAZC4KQu7YXrq7AE7IP6XE1ujX8EGyxMFer84=@vger.kernel.org X-Gm-Message-State: AOJu0Yy5ZZk79O0E1trBW2z6l1SphPzDnGYLEadaUzUOTlavPkwQiwxm RGQkKe+l3h4xLHadZqYsJsUDZh0yibvjHsMRFSrcx4LjE7SwTAURy3DbBc30vddTr4w= X-Gm-Gg: ASbGnct6PccltijMPSB4AVl9SAFc119jhUF3jr0VOTRV+mW0mOgMlWSWCErGHU9/QxT e+oYCJio7KPL/0J7nER3hTy2xMXSz8cMuoOzqhPwSEC+NukTbibuyBZI8/67UY37RFMVB3Z/PTP jTSvKFSVvm+2oX8jNpicRQjYY8DGRNqPpvo7hE2xgXKNLtBtnVsNFDBF8IIwPUBa1QyBSaFvMQ7 CQKuymBy/+6SKDqLiXQzblwnT0n6FsqaDMLFSU8AkKGNJsGIaxxbAbRn6cABfau9YlWsbcwtgzU V8k/33Z9QRCfOwTWxTdBz4+vjFWil5PravQde6Z3M9YFBTCJE/5CIJ3EGqpq X-Google-Smtp-Source: AGHT+IGzW6H/JY6okGMYKiGy1G81BD38MaxIg1/bSFnC+yh1zhWoHrWS5IoXHEN57n42Gztkjj9u+w== X-Received: by 2002:a05:6000:2011:b0:3a4:eb92:b5eb with SMTP id ffacd0b85a97d-3a4eb92b7damr3548709f8f.50.1748518389701; Thu, 29 May 2025 04:33:09 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:09 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:22 +0100 Subject: [PATCH v2 01/11] arm64: sysreg: Update PMSIDR_EL1 description Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-1-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev X-Mailer: b4 0.14.0 From: Marc Zyngier Add the missing SME, ALTCLK, FPF, EFT. CRR and FDS fields. Signed-off-by: Marc Zyngier Tested-by: Leo Yan --- arch/arm64/tools/sysreg | 28 ++++++++++++++++++++++++++-- 1 file changed, 26 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index bdf044c5d11b..e7a8423500f7 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2226,7 +2226,28 @@ Field 15:0 MINLAT EndSysreg =20 Sysreg PMSIDR_EL1 3 0 9 9 7 -Res0 63:25 +Res0 63:33 +UnsignedEnum 32 SME + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 31:28 ALTCLK + 0b0000 NI + 0b0001 IMP + 0b1111 IMPDEF +EndEnum +UnsignedEnum 27 FPF + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 26 EFT + 0b0 NI + 0b1 IMP +EndEnum +UnsignedEnum 25 CRR + 0b0 NI + 0b1 IMP +EndEnum Field 24 PBT Field 23:20 FORMAT Enum 19:16 COUNTSIZE @@ -2244,7 +2265,10 @@ Enum 11:8 INTERVAL 0b0111 3072 0b1000 4096 EndEnum -Res0 7 +UnsignedEnum 7 FDS + 0b0 NI + 0b1 IMP +EndEnum Field 6 FnE Field 5 ERND Field 4 LDS --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ED05728EA4E for ; Thu, 29 May 2025 11:33:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.221.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518394; cv=none; b=g1qF49Kq2O5pLtZ7gE/uGloqvOue/vmwQhFHvsyzPLaYX8Q0g16EuRck6NFd9nby4v4URUsDgHwAJs46+t1O54wbpNwUyoEr/u7cEq7zoLEnRFacr9NmO5mwQZe9ZBED1O6WMi50FAcODYCowXisKtowmutdJDwLn6/JBzWDubU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518394; c=relaxed/simple; bh=FgznNT9Brk72b5Sn5qJ9KzEFbrY6vz/wN6krkmPDC2U=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Ipfw1SCa55uYnMRx10PGh9zdW7Ktcai5C2IbLw73yEzppy5+eQmJDAcWJYNWjYq/osCYfz+3o+h3Hhm4Ui5X2kDxpB93K4l19vmr3nP1j6jBueiFn5QwCyLtt+ySz7y7Oqpkb6AC43XrfsaCFPAm22uXyk18KM+pcB1vnvoX8Ps= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=xMKltMEt; arc=none smtp.client-ip=209.85.221.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="xMKltMEt" Received: by mail-wr1-f44.google.com with SMTP id ffacd0b85a97d-3a375888297so500672f8f.1 for ; Thu, 29 May 2025 04:33:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518391; x=1749123191; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=2Ao7OlEh12lpRfhENXnzwKUwXbWabkHGccxknuUI7tI=; b=xMKltMEtu0lSPEIL439ZzVVo4pKDAOv0mcHdUvseqlQJcj9fnf3b/vKoScqHbXPs+X K1T2d94UD+3GGzS0f3L04srJgJkqKtzE6hgEmUbYYwb46pcW2r44PeZdQGqEeBObLkeV TSX1lK3EtbEclFHsrfdJotDAnBNB19mRQLRIgSLkbzQdLZYfg9YJtWRNvKVK1QFRIwA3 4drN9FUCsP+PLbGhx9am1XRi3lT5+jfk+dvgpdylDlfGA9ivvz2vTvOukc7BTfWilKpP jzOz1ferOk6dBmixWk1ZAg+nXD06V5pH9ic9IkBg4znx5cmmeyfGMaRXK1XCbqHgTJBu Y7kQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518391; x=1749123191; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=2Ao7OlEh12lpRfhENXnzwKUwXbWabkHGccxknuUI7tI=; b=gN/Baa5Ti++XHO6hFRkWEtxQ8f/81y81D2zV4tun/n4zC6BitZs3l2np8RkbrHnntp KajpQI576HPo9BlU/oLRfRIEM5WALoxXECtE5C83k1dLJDAeBJd84fnaHayY0F8Zki2p gQQDrfAdMPlok0ho3D8XVvXrZByWNSYOeqNJXuaCDtEo8p2go6W2IORytv70Dn3XNuXj KFRf75m5ThZRLyh7MbXYiWHuHBeX1Iqn7beC8Y2KE9aVl0DXv6qfbk30QkN7dhRuLLme GcvDK/OSHb8+2hVLMtJeZfeyfql+sdy8D4wzrsh+qeXDSzUpeH6vXBAB4lie6Bk3YlVZ iefQ== X-Forwarded-Encrypted: i=1; AJvYcCVDiThs5H0hLFhNW6sDqsD02IquqGrCb/P9A1ZM6TLG0VLrMRbf4MBdNRcxlZvDUqlu5tuTXDoEmZuPKeQ=@vger.kernel.org X-Gm-Message-State: AOJu0YzA8/lqITL29E6w7tt3hqAECn/6eHXmV51cyiS5WYRdCEANa2Ho MawnrpPUNpaBT/G1BOZl6f6Zf6Ga3Z+qvU9MseiYDtk83eePQGnhSdVmmLC7lDUa0PI= X-Gm-Gg: ASbGncsNm/PMzJDetp5hhvVOG2ppEQDZK84IXGS+Q4c7SXuahdDigZefZlZ4rwGvH1t 7QiUyhoKVqei7q3OjfnCOyQdrYw/EArMQEra847xLS+My6edp+lsmrCatA1apVX+3BAaTrfDR4I MUVQQQk4rRk5j/VwByYlQzdHJH+QezECYOkP5ikC9gaROq7BvCsaoi1gdnMhlIqIxlcS2L0AqLP P/xqLbcca7iJQbxa9BBafO9Nf8EJp8g7c6DyBobE0KilKAi4s5SPhQFLH/kdZRCud9yOVXBEPTP gjH4FJeY9zJmzNiXtrkmmGeRjiY6U4+Muxw2T/KKZq2oGu7WQIHrJ/NceXYy X-Google-Smtp-Source: AGHT+IGCVcVUkYf0t9hJfA1IEOCLHRWCcVLSmCqfshXf0Ly5nAMyifnx2BqS+BSK2ezf753KYr0JOA== X-Received: by 2002:a05:6000:2dc5:b0:3a4:db4a:3004 with SMTP id ffacd0b85a97d-3a4eedb8ab6mr2607351f8f.22.1748518391182; Thu, 29 May 2025 04:33:11 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:10 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:23 +0100 Subject: [PATCH v2 02/11] arm64: sysreg: Add new PMSFCR_EL1 fields and PMSDSFR_EL1 register Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-2-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 Add new fields and register that are introduced for the features FEAT_SPE_EFT (extended filtering) and FEAT_SPE_FDS (data source filtering). Signed-off-by: James Clark Tested-by: Leo Yan --- arch/arm64/tools/sysreg | 17 +++++++++++++++-- 1 file changed, 15 insertions(+), 2 deletions(-) diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg index e7a8423500f7..e2cadf224f7e 100644 --- a/arch/arm64/tools/sysreg +++ b/arch/arm64/tools/sysreg @@ -2205,11 +2205,20 @@ Field 0 RND EndSysreg =20 Sysreg PMSFCR_EL1 3 0 9 9 4 -Res0 63:19 +Res0 63:53 +Field 52 SIMDm +Field 51 FPm +Field 50 STm +Field 49 LDm +Field 48 Bm +Res0 47:21 +Field 20 SIMD +Field 19 FP Field 18 ST Field 17 LD Field 16 B -Res0 15:4 +Res0 15:5 +Field 4 FDS Field 3 FnE Field 2 FL Field 1 FT @@ -2311,6 +2320,10 @@ Field 16 COLL Field 15:0 MSS EndSysreg =20 +Sysreg PMSDSFR_EL1 3 0 9 10 4 +Field 63:0 S +EndSysreg + Sysreg PMBIDR_EL1 3 0 9 10 7 Res0 63:12 Enum 11:8 EA --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f48.google.com (mail-wm1-f48.google.com [209.85.128.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58C0028EA52 for ; Thu, 29 May 2025 11:33:14 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518396; cv=none; b=Yf+uHCCerCXYvLdGJzIf4+Uk8EQaVHmSb4KldwEFOxbuCrH0fnnlrUZTjPCJ6iqM5zpnuJktsTWy3GJl3w5piEDd4uk4I50iydMzPT97HWCbPOmF+atBUn09wgmvSW+zfz8+QPeK2/JsOp48esXiZHp1dl9AmE7sZuC3OIDO/zk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518396; c=relaxed/simple; bh=bhT/vBdY445hdiJGnxyUjZuj2JipKZSpecA8eMwMkO0=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=qQ8NUMl4N5NBxlPRUWaAxoNCSvehUNJfve68uQfVyz7uSyH1pOe3vJhKdGa/IXrTGnSPM2pjWxQyErn9HMkstpACIOFhDPZQmeDRJV8zOkKwnPumNCXhgzuok5jzgR1CI92lj/1Db7JdZtZMsMoyIP/43ZCIIHrWbmtU+HY7snM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=qI75gdiQ; arc=none smtp.client-ip=209.85.128.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="qI75gdiQ" Received: by mail-wm1-f48.google.com with SMTP id 5b1f17b1804b1-442f4a3a4d6so5460585e9.0 for ; Thu, 29 May 2025 04:33:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518393; x=1749123193; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YBh51vvyiyhareusQPjv3Jd+V2PWdf2x4DOb/Anfvgk=; b=qI75gdiQU9dZxdDIY2zh4VkOCcPNvyAus9RgqyCsuBIVoYoNNHg2gzMZYmc0dXxqR7 8xFHYDuFwQzBZwBUlYMJQhmqnsZ7rLpMpcO+i8dKHD6S02iYrSMauNn8NKUctPy13GIv lkbHVp51V4CeYYQlWev7h6hrnTPo+EBbzAX4pj0DmZmNBSldW5J6YwseVqNK8buft5xE jSsgXeuNpmDYyKzTomv6Bh+UyHM2Hz83DNL0nRt3pW4/7CIHdtBJpayjHbnzSeq8ZtHs mIoquA6MD0GXC8HQfEGTfDWFZzDjzVPN3mpRdBKkJ8VCfqmDYPaJ7+zXsSR866AoJRZB 0jRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518393; x=1749123193; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBh51vvyiyhareusQPjv3Jd+V2PWdf2x4DOb/Anfvgk=; b=K0al0YfyAuPW0cJt/Obb3S2kZpBkw2zgtOK6Ls30aOHFZZVcKE7s+wvQIhTZmiMC0/ uJiChNri7BWBNheD+pRBV0Cb9qMXjtDlf3HzDjlx2WSS1xOz2joMyYPQJCAqKMGSLDx+ lDwZu/l2Imi661xoTdLZoTee8RzQG2xCz9WV9X1WXvLXLD6IU8VFmZ/doSFt8hg98Zoh 1kmTT8GKaBMN5jbA8sQF4mq26jpOqdUYtAZgE/04tUAU+sVhMAV1s9I7ZuHVDFnXWXLN fF3fd7uv6m8ckAUF+df4Njqq1iROEIaRLHAPB4/Gn3zynoqnQYJK3GbsM35TrrQdByrh HmLg== X-Forwarded-Encrypted: i=1; AJvYcCVyW8EtcaoqvdxPTYDU7sgiyMaSrr2XxEXJPRC1+cJArLkzNirvud9an/OdUiWlfsY/t4SV8FaruRcZiY4=@vger.kernel.org X-Gm-Message-State: AOJu0YwYE5qaGQIQLvkixPLVCMTRGqpq50hC3u7/GFIJ1xV0VBq8CaPU yOENsp30DFhDCkqH5L/XJHu+9anGUMPjsvDvhXJPhemHGmBupFlEpFk5wI/E6IP+Kvc= X-Gm-Gg: ASbGncuDkPFuScYl6qCXnsrmXqpQwSsqfJ0FvyoobtEX4HDejQ+GT74f+grGNo5LC+j RlSHrfDmFGyMZ/D6ObxdvsJY1KD6rZ0nEz43h6FyV3XB5UFeXZBsXa1wlSwZkmrKrPa+dSx5aDr oFeBN9Ar08x7b5ObN8XZfm5lNHawz38D1aYppPGhQQDLgwDNP3SQvyqAKzvFwxjgMu3efCC/k1W BTFh408v0bxK0c73p9mT5x0wN5ldixdPFd+VU1lFHt8FthGbB5Q9GWlS30vbQKsuKJSkZIrC5pC Q+060ZitR9HRoqav0UIjKQ0VP74zE1N80GFY08/W2iUjbr/SeeEdDu1HBgFi X-Google-Smtp-Source: AGHT+IEtrMK0+qCLgw3Q1exhgAhuym8fUYhFgSSn+IhOQ2msA1tWH3EQ6muEHr0G05oi7CZJdKSgdw== X-Received: by 2002:a05:600c:4f0e:b0:442:f861:3536 with SMTP id 5b1f17b1804b1-450ce83c85bmr27386615e9.7.1748518392610; Thu, 29 May 2025 04:33:12 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:12 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:24 +0100 Subject: [PATCH v2 03/11] perf: arm_spe: Support FEAT_SPEv1p4 filters Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-3-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, Leo Yan , James Clark X-Mailer: b4 0.14.0 FEAT_SPEv1p4 (optional from Armv8.8) adds some new filter bits, so remove them from the previous version's RES0 bits using PMSEVFR_EL1_RES0_V1P4_EXCL. It also makes some previously available bits unavailable again, so add those back using PMSEVFR_EL1_RES0_V1P4_INCL. E.g: E[30], bit [30] When FEAT_SPEv1p4 is _not_ implemented ... FEAT_SPE_V1P3 has the same filters as V1P2 so explicitly add it to the switch. Reviewed-by: Leo Yan Signed-off-by: James Clark Tested-by: Leo Yan --- arch/arm64/include/asm/sysreg.h | 7 +++++++ drivers/perf/arm_spe_pmu.c | 5 ++++- 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysre= g.h index 2639d3633073..e24042e914a4 100644 --- a/arch/arm64/include/asm/sysreg.h +++ b/arch/arm64/include/asm/sysreg.h @@ -354,6 +354,13 @@ (PMSEVFR_EL1_RES0_IMP & ~(BIT_ULL(18) | BIT_ULL(17) | BIT_ULL(11))) #define PMSEVFR_EL1_RES0_V1P2 \ (PMSEVFR_EL1_RES0_V1P1 & ~BIT_ULL(6)) +#define PMSEVFR_EL1_RES0_V1P4_EXCL \ + (BIT_ULL(2) | BIT_ULL(4) | GENMASK_ULL(10, 8) | GENMASK_ULL(23, 19)) +#define PMSEVFR_EL1_RES0_V1P4_INCL \ + (GENMASK_ULL(31, 26)) +#define PMSEVFR_EL1_RES0_V1P4 \ + (PMSEVFR_EL1_RES0_V1P4_INCL | \ + (PMSEVFR_EL1_RES0_V1P2 & ~PMSEVFR_EL1_RES0_V1P4_EXCL)) =20 /* Buffer error reporting */ #define PMBSR_EL1_FAULT_FSC_SHIFT PMBSR_EL1_MSS_SHIFT diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 3efed8839a4e..d9f6d229dce8 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -701,9 +701,12 @@ static u64 arm_spe_pmsevfr_res0(u16 pmsver) case ID_AA64DFR0_EL1_PMSVer_V1P1: return PMSEVFR_EL1_RES0_V1P1; case ID_AA64DFR0_EL1_PMSVer_V1P2: + case ID_AA64DFR0_EL1_PMSVer_V1P3: + return PMSEVFR_EL1_RES0_V1P2; + case ID_AA64DFR0_EL1_PMSVer_V1P4: /* Return the highest version we support in default */ default: - return PMSEVFR_EL1_RES0_V1P2; + return PMSEVFR_EL1_RES0_V1P4; } } =20 --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f68.google.com (mail-wm1-f68.google.com [209.85.128.68]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D341028ECE8 for ; Thu, 29 May 2025 11:33:15 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.68 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518399; cv=none; b=ossPw9qYSeWFxI+bmmqooqseZ9POgRC4P73nZEZqSCc5HTKTp3rSggORKw1uWdcjXi+J/vj4rFku+5okKyVpb3nRKYwpuxDCrxc8PzpDWHNojdqYa33lSteliOwI2WfNUlDJnQ7rqz6SRBykWU0Hybb8iWkvth02kYLkRK7Ym38= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518399; c=relaxed/simple; bh=JLw1SbFI9hf2HJHhhd0RjbsrbancA+Y8QFfWRVSOicI=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GRLm7tzEMdlMcqRmVfDZlhGDIwro9PdpW/4gswOKlYeFkyRKIDbqjrkOuNKK3Un6wnk2jv3nB177ZU7DGhEFN1vFaqpVdrYmEKoTfkc91KxNBWcOYkEcWFH25CtyMdEsKdb5KwibJ/5hBMReqteh1I/p08UCyiiG2R/guiNNRXM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=cAFr+eip; arc=none smtp.client-ip=209.85.128.68 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="cAFr+eip" Received: by mail-wm1-f68.google.com with SMTP id 5b1f17b1804b1-442f4a3a4d6so5460735e9.0 for ; Thu, 29 May 2025 04:33:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518394; x=1749123194; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=pfKDbgxKd2ROJeUv6l7PkfuDFl5ROKG8g8tB4U0lR18=; b=cAFr+eipsTpXBTqs8pH94AdsgTqf70849JkPIcr+DFIPbRGcaZ0iZo8Z74hIQQv/l7 ccD53e4q7E8Ur0glBPsvkG6XsdwDz60dlUnbfDTl/F9LAgUB23SRJV/nBMNV3L5u43ZS WzDKoecgZzdZx/d79Ltn2xmIAfNtiL/ZUFCtsTZEHbq2eguLcjceufLzpdhL42DJLAKY 2aN5TqbLvfWJjw9b0nJTgjVNfuJ0MzIAxt+744g+BvwteN0HAXqB0jZMuCMiVZ7mLEHs 06SUUXTRDiZCj7PlOnNlNYYSjOblWd9P3YzVgLdqrawE4X6ANRBUTioRjYhyOIe0MjoX Lc8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518394; x=1749123194; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=pfKDbgxKd2ROJeUv6l7PkfuDFl5ROKG8g8tB4U0lR18=; b=t926eQf4V80QaFiUuPJN84pn3UrwNKEmwSi/vV6R229Pzshe9LTXD4+uS/45op7cot fKPTggiXgsNDWUyhMbtRIt1PO8DNneuukB8amlqCSSOVaR6a2RLlTLkEr+yazWLZ66lN Ypk0aEpfomf2sImhASHHFq1ESc0EXD+hN7tA5Fr5rmlCOLcdmWxrTPo78yrKSielLQy6 g/A2eQNI70UUBdSBbfu7MgGYP0gkujoV0UimwCIgmFaaf1m/jliLiC/tUm3ifeW8+2L7 PUtu9KNAMvw9W9sgD3fMFCJTm3Va3KyCgEAbPq9k7h6UAC9FtxXTF9LGa2x/cXNDQhgE s4nw== X-Forwarded-Encrypted: i=1; AJvYcCV7NCkpwRKYbNvl4wwqlSd5xZpHeW8OeOcaR2+kNKW4ecqRbSlPaanFmfEnm1lBIeMw7Dn1ag2bE816Ac0=@vger.kernel.org X-Gm-Message-State: AOJu0YzhcKLETqjlL2J65OjQDaqtXVlp6aJt/AmhY54EPSTUzC97S+LB 4jvVZtIvrO1T1SAMnackGeBQtTE4pqrZffUbUmykykXnd7wI0OunoSiujqT9OmP31vU= X-Gm-Gg: ASbGnctwf9dq/ubgIgxZe2Kss1AgI0bg65bpYokZ5cDQ7JvdQxK/tP4gFLt+guK4BYA X/We24jryYU+70LPefKoJAwOSoZH0ldj0y9EVbUVMf2NxGopLX5/NQpdrLlFxvgHQjMifuGRa7f nHqLG94y1MWZZyz9BK2HEUbMASaUvzF6uPkQO34Qo3t8NFQt30YrSi1Noz7BYsigLZVLS4jGpmv PcvkH7gjLJnM6O2eLuhIf5rQry/yGbeCZ5L7CMvSfeVT8mU2rezdMHRkC4I381LrD1EmXImsmb4 C0dDbQ6Y96LLjdvapQvK9sxw8b1019MxCbZnaMrUSwa5WIKH7mzigzfqPupG X-Google-Smtp-Source: AGHT+IHSPmk4fOgPDFLIZtWqcVjzQhEo6i8WE5FJ9ZlisuotXu0mllwIX71So8rjCmQxGTK63Cn0Dw== X-Received: by 2002:a05:600c:4649:b0:43c:ec72:3daf with SMTP id 5b1f17b1804b1-450ce88aa5dmr21155125e9.14.1748518394056; Thu, 29 May 2025 04:33:14 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:13 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:25 +0100 Subject: [PATCH v2 04/11] perf: arm_spe: Add support for FEAT_SPE_EFT extended filtering Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-4-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, Leo Yan , James Clark X-Mailer: b4 0.14.0 FEAT_SPE_EFT (optional from Armv9.4) adds mask bits for the existing load, store and branch filters. It also adds two new filter bits for SIMD and floating point with their own associated mask bits. The current filters only allow OR filtering on samples that are load OR store etc, and the new mask bits allow setting part of the filter to an AND, for example filtering samples that are store AND SIMD. With mask bits set to 0, the OR behavior is preserved, so the unless any masks are explicitly set old filters will behave the same. Add them all and make them behave the same way as existing format bits, hidden and return EOPNOTSUPP if set when the feature doesn't exist. Reviewed-by: Leo Yan Signed-off-by: James Clark Tested-by: Leo Yan --- drivers/perf/arm_spe_pmu.c | 64 ++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index d9f6d229dce8..9309b846f642 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -86,6 +86,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_ERND (1UL << 5) #define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DISCARD (1UL << 7) +#define SPE_PMU_FEAT_EFT (1UL << 8) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -197,6 +198,27 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_discard_CFG config /* PMBLIMITR_EL1.FM =3D DISCARD */ #define ATTR_CFG_FLD_discard_LO 35 #define ATTR_CFG_FLD_discard_HI 35 +#define ATTR_CFG_FLD_branch_filter_mask_CFG config /* PMSFCR_EL1.Bm */ +#define ATTR_CFG_FLD_branch_filter_mask_LO 36 +#define ATTR_CFG_FLD_branch_filter_mask_HI 36 +#define ATTR_CFG_FLD_load_filter_mask_CFG config /* PMSFCR_EL1.LDm */ +#define ATTR_CFG_FLD_load_filter_mask_LO 37 +#define ATTR_CFG_FLD_load_filter_mask_HI 37 +#define ATTR_CFG_FLD_store_filter_mask_CFG config /* PMSFCR_EL1.STm */ +#define ATTR_CFG_FLD_store_filter_mask_LO 38 +#define ATTR_CFG_FLD_store_filter_mask_HI 38 +#define ATTR_CFG_FLD_simd_filter_CFG config /* PMSFCR_EL1.SIMD */ +#define ATTR_CFG_FLD_simd_filter_LO 39 +#define ATTR_CFG_FLD_simd_filter_HI 39 +#define ATTR_CFG_FLD_simd_filter_mask_CFG config /* PMSFCR_EL1.SIMDm */ +#define ATTR_CFG_FLD_simd_filter_mask_LO 40 +#define ATTR_CFG_FLD_simd_filter_mask_HI 40 +#define ATTR_CFG_FLD_float_filter_CFG config /* PMSFCR_EL1.FP */ +#define ATTR_CFG_FLD_float_filter_LO 41 +#define ATTR_CFG_FLD_float_filter_HI 41 +#define ATTR_CFG_FLD_float_filter_mask_CFG config /* PMSFCR_EL1.FPm */ +#define ATTR_CFG_FLD_float_filter_mask_LO 42 +#define ATTR_CFG_FLD_float_filter_mask_HI 42 =20 #define ATTR_CFG_FLD_event_filter_CFG config1 /* PMSEVFR_EL1 */ #define ATTR_CFG_FLD_event_filter_LO 0 @@ -215,8 +237,15 @@ GEN_PMU_FORMAT_ATTR(pa_enable); GEN_PMU_FORMAT_ATTR(pct_enable); GEN_PMU_FORMAT_ATTR(jitter); GEN_PMU_FORMAT_ATTR(branch_filter); +GEN_PMU_FORMAT_ATTR(branch_filter_mask); GEN_PMU_FORMAT_ATTR(load_filter); +GEN_PMU_FORMAT_ATTR(load_filter_mask); GEN_PMU_FORMAT_ATTR(store_filter); +GEN_PMU_FORMAT_ATTR(store_filter_mask); +GEN_PMU_FORMAT_ATTR(simd_filter); +GEN_PMU_FORMAT_ATTR(simd_filter_mask); +GEN_PMU_FORMAT_ATTR(float_filter); +GEN_PMU_FORMAT_ATTR(float_filter_mask); GEN_PMU_FORMAT_ATTR(event_filter); GEN_PMU_FORMAT_ATTR(inv_event_filter); GEN_PMU_FORMAT_ATTR(min_latency); @@ -228,8 +257,15 @@ static struct attribute *arm_spe_pmu_formats_attr[] = =3D { &format_attr_pct_enable.attr, &format_attr_jitter.attr, &format_attr_branch_filter.attr, + &format_attr_branch_filter_mask.attr, &format_attr_load_filter.attr, + &format_attr_load_filter_mask.attr, &format_attr_store_filter.attr, + &format_attr_store_filter_mask.attr, + &format_attr_simd_filter.attr, + &format_attr_simd_filter_mask.attr, + &format_attr_float_filter.attr, + &format_attr_float_filter_mask.attr, &format_attr_event_filter.attr, &format_attr_inv_event_filter.attr, &format_attr_min_latency.attr, @@ -250,6 +286,16 @@ static umode_t arm_spe_pmu_format_attr_is_visible(stru= ct kobject *kobj, if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) return 0; =20 + if ((attr =3D=3D &format_attr_branch_filter_mask.attr || + attr =3D=3D &format_attr_load_filter_mask.attr || + attr =3D=3D &format_attr_store_filter_mask.attr || + attr =3D=3D &format_attr_simd_filter.attr || + attr =3D=3D &format_attr_simd_filter_mask.attr || + attr =3D=3D &format_attr_float_filter.attr || + attr =3D=3D &format_attr_float_filter_mask.attr) && + !(spe_pmu->features & SPE_PMU_FEAT_EFT)) + return 0; + return attr->mode; } =20 @@ -341,8 +387,15 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *= event) u64 reg =3D 0; =20 reg |=3D FIELD_PREP(PMSFCR_EL1_LD, ATTR_CFG_GET_FLD(attr, load_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_LDm, ATTR_CFG_GET_FLD(attr, load_filter_ma= sk)); reg |=3D FIELD_PREP(PMSFCR_EL1_ST, ATTR_CFG_GET_FLD(attr, store_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_STm, ATTR_CFG_GET_FLD(attr, store_filter_m= ask)); reg |=3D FIELD_PREP(PMSFCR_EL1_B, ATTR_CFG_GET_FLD(attr, branch_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_Bm, ATTR_CFG_GET_FLD(attr, branch_filter_m= ask)); + reg |=3D FIELD_PREP(PMSFCR_EL1_SIMD, ATTR_CFG_GET_FLD(attr, simd_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_SIMDm, ATTR_CFG_GET_FLD(attr, simd_filter_= mask)); + reg |=3D FIELD_PREP(PMSFCR_EL1_FP, ATTR_CFG_GET_FLD(attr, float_filter)); + reg |=3D FIELD_PREP(PMSFCR_EL1_FPm, ATTR_CFG_GET_FLD(attr, float_filter_m= ask)); =20 if (reg) reg |=3D PMSFCR_EL1_FT; @@ -716,6 +769,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) u64 reg; struct perf_event_attr *attr =3D &event->attr; struct arm_spe_pmu *spe_pmu =3D to_spe_pmu(event->pmu); + const u64 feat_spe_eft_bits =3D PMSFCR_EL1_LDm | PMSFCR_EL1_STm | + PMSFCR_EL1_Bm | PMSFCR_EL1_SIMD | + PMSFCR_EL1_SIMDm | PMSFCR_EL1_FP | + PMSFCR_EL1_FPm; =20 /* This is, of course, deeply driver-specific */ if (attr->type !=3D event->pmu->type) @@ -761,6 +818,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) !(spe_pmu->features & SPE_PMU_FEAT_FILT_LAT)) return -EOPNOTSUPP; =20 + if ((reg & feat_spe_eft_bits) && + !(spe_pmu->features & SPE_PMU_FEAT_EFT)) + return -EOPNOTSUPP; + if (ATTR_CFG_GET_FLD(&event->attr, discard) && !(spe_pmu->features & SPE_PMU_FEAT_DISCARD)) return -EOPNOTSUPP; @@ -1052,6 +1113,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (spe_pmu->pmsver >=3D ID_AA64DFR0_EL1_PMSVer_V1P2) spe_pmu->features |=3D SPE_PMU_FEAT_DISCARD; =20 + if (FIELD_GET(PMSIDR_EL1_EFT, reg)) + spe_pmu->features |=3D SPE_PMU_FEAT_EFT; + /* This field has a spaced out encoding, so just use a look-up */ fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 546A528F537 for ; Thu, 29 May 2025 11:33:17 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518399; cv=none; b=blNmbEbn7k1yqaTb2XuzCGJZseH0SRTaKKZQjsFO8ORlegP0M3Idjk8FBw0Gkk/SuuWOmpAwH85Msn+PQatyIIh6lkjjOMQjrShmvtVsRs7jVZ3IbVLaoovNakLSV3JS0fcrvXrKabfwTjOu4x85AE1Ml7rJad7pO1NNiaV4uHo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518399; c=relaxed/simple; bh=41eja3GEP0F1NgK0VkDUcr/lsnX2RYh7poVYaCc8trk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=a/rPCjZoVW6UHDwhPy1itEHS38OUJUklmmk7bGtLQihfCMawkt/BPXK43r25+iqC+0ad91lthmQ6gfb2iURryHkn1pjVZThNOVHNgHr0ikpaZRclFRdAuF7DibPkKYfx4y0qR9Y6jfsLr3yapXhRSWaOC7kftRCH7nO7279vp60= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=tveF6x0L; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="tveF6x0L" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-450cd6b511cso5007725e9.2 for ; Thu, 29 May 2025 04:33:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518395; x=1749123195; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=YBZfytqoLfoLLkCHGYVhQ8mByrfQ3MODercYrOljLZA=; b=tveF6x0LTIphKP0aCxdlfKc6YExlp970rewGPdO21OJbNl2+9FGI3ATNw1+E1PWQzK piOir6s5Zg7F923RnCnR+lolV/VDHDGz2kL0a2SDJnpmdeQPOFr9MYqrjWZuzViUGMkk iiOACc1+kD/SAiO0EvAkwYWN8rg4K+54IrCrxAD0Xv4g/+UokivZJiq2Cs9cd8EDqvUw i1T3cJ2XNU//3WyGHgPEXE0FTtUTRMUoFhP71AdThszN18Cv28QWn79uC2KFsg806wT8 XT5X262iL2LUat2vREw/3jzw7Rd1UjSHApYXAdlJY1rxA1Xm4RNNUPS+M0IrmQRbQOoK 6I1A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518395; x=1749123195; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=YBZfytqoLfoLLkCHGYVhQ8mByrfQ3MODercYrOljLZA=; b=oVNGTGmSZonN/pOaQJSTyZ+vyi2OyG83vGew93JH/zibvZNxE0SrtI4ZKX1oqjX0xn RBhabQluLPtAE98h6ZKcQVyv6wvfrVaep+8xGg8lD0sJnbql/Aan4uyptABywH3oPYBV 8eftxNdWkh1CdxqoUf3UN/hldl3YI3S31OZzZk8PT+KvrL+ZbwOo/SkaGkG2r+fGLlQX aB9Cqv67tL4WX6YhAUBPSHrQhuEDxYMPOqcm/9dfvk4s6LyKDi5JTS2mLCKAVYhJbrXD LTOGxsaTS45ZBdpG1yBw94R9NTUVWt96dUdeoQqsr7Rj1AFvPSFQQsdnREtJ2ywTnZzn sHbA== X-Forwarded-Encrypted: i=1; AJvYcCWY286H0TeTOo5+TY42O3fV/mjAPuwp1270ieCwguQuAemZT4aAmh+1FIMjPDuUa3ANAAiG/nHFgRudDME=@vger.kernel.org X-Gm-Message-State: AOJu0YwLgXDVK959sPNwkbZTKUKGJOocV5w9+icKDN3QUzpZFPqwt+WM xZzVVaroH/Y0dmn0kLtjyzIf1zJydL0vOlTNjXZJBo8YbdzgZ3Bh64XRmrT4RkYCwOo= X-Gm-Gg: ASbGncvxZIgOA+gonF19QZdkxMbGA6IcRYC/r3s0nOTWJZpN6AU4aG69g0iOrqAXluc YMfoM61yv3ZmY0K6MWH2PZaB9dIqDiDBP4YMfqh3IQV9/pLhaxcbRfWYyP4D5vyGlguZMj0wc9i KR5SFaRPCXs9ixIxDj699H2nkaUL9yirBmx+gRkFwoIRC7Fgh2ATCUWzkwPx6oNtm9xAfaOyg3p It3bg/C1mCPiJLjz36zzo03zJh20YBekkIYVD8EsysxpwT/NAA09BJKC0dQBrZZ7jmC4pvfinqK 0IeqM8YcBusbKFu4lR9LWv96p5jIaisoKgcOmjSaW/3I6wpvAzc0xdZOMBmZ X-Google-Smtp-Source: AGHT+IHMMfVW7IE9nbkSMy9wDfF0tmM1c9IXy+rbxej/RhTBlE7UtH3OLrCFPOGZOGsnCFRe6FkZLQ== X-Received: by 2002:a05:600c:4394:b0:450:cc79:676 with SMTP id 5b1f17b1804b1-450cc79077fmr23266695e9.20.1748518395511; Thu, 29 May 2025 04:33:15 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:15 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:26 +0100 Subject: [PATCH v2 05/11] arm64/boot: Enable EL2 requirements for SPE_FEAT_FDS Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-5-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 SPE data source filtering (optional from Armv8.8) requires that traps to the filter register PMSDSFR be disabled. Document the requirements and disable the traps if the feature is present. Signed-off-by: James Clark Tested-by: Leo Yan --- Documentation/arch/arm64/booting.rst | 11 +++++++++++ arch/arm64/include/asm/el2_setup.h | 14 ++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/Documentation/arch/arm64/booting.rst b/Documentation/arch/arm6= 4/booting.rst index dee7b6de864f..abd75085a239 100644 --- a/Documentation/arch/arm64/booting.rst +++ b/Documentation/arch/arm64/booting.rst @@ -404,6 +404,17 @@ Before jumping into the kernel, the following conditio= ns must be met: - HDFGWTR2_EL2.nPMICFILTR_EL0 (bit 3) must be initialised to 0b1. - HDFGWTR2_EL2.nPMUACR_EL1 (bit 4) must be initialised to 0b1. =20 + For CPUs with SPE data source filtering (FEAT_SPE_FDS): + + - If EL3 is present: + + - MDCR_EL3.EnPMS3 (bit 42) must be initialised to 0b1. + + - If the kernel is entered at EL1 and EL2 is present: + + - HDFGRTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. + - HDFGWTR2_EL2.nPMSDSFR_EL1 (bit 19) must be initialised to 0b1. + For CPUs with Memory Copy and Memory Set instructions (FEAT_MOPS): =20 - If the kernel is entered at EL1 and EL2 is present: diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el= 2_setup.h index f6d72ca03133..6d0d8c25e912 100644 --- a/arch/arm64/include/asm/el2_setup.h +++ b/arch/arm64/include/asm/el2_setup.h @@ -279,6 +279,20 @@ orr x0, x0, #HDFGRTR2_EL2_nPMICFILTR_EL0 orr x0, x0, #HDFGRTR2_EL2_nPMUACR_EL1 .Lskip_pmuv3p9_\@: + mrs x1, id_aa64dfr0_el1 + ubfx x1, x1, #ID_AA64DFR0_EL1_PMSVer_SHIFT, #4 + /* If SPE is implemented, */ + cmp x1, #ID_AA64DFR0_EL1_PMSVer_IMP + b.lt .Lskip_spefds_\@ + /* we can read PMSIDR and */ + mrs_s x1, SYS_PMSIDR_EL1 + and x1, x1, #(1 << PMSIDR_EL1_FDS_SHIFT) + /* if FEAT_SPE_FDS is implemented, */ + cbz x1, .Lskip_spefds_\@ + /* disable traps to PMSDSFR. */ + orr x0, x0, #HDFGRTR2_EL2_nPMSDSFR_EL1 + +.Lskip_spefds_\@: msr_s SYS_HDFGRTR2_EL2, x0 msr_s SYS_HDFGWTR2_EL2, x0 msr_s SYS_HFGRTR2_EL2, xzr --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f41.google.com (mail-wm1-f41.google.com [209.85.128.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A565C28F94F for ; Thu, 29 May 2025 11:33:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.41 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518401; cv=none; b=VSwsO57NUpi/TXzxRK9FDChucsXE4IzUZrp3era7Az8DZzomjQXSj5Bio68fGMLfPStWPQfCY7KM0+XQIY4f/MeljXPqNbVc+avBwQVVW7lFz8F2QzP+RGTAmDaibVY0JbK+ym6OZacHzyGOGEdFQrF1pLqhOh+jkTyXb3dR38o= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518401; c=relaxed/simple; bh=3Nke7IrlZt1dIQrrtJZ35wZYJcBpZtgeyy0gHEfYDMk=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SjYbMcYH1vTkBhAcQwb6jz9GpoyWlkzQhLeT6b0j5GJ0L+ctLw3PRYiPHbqPgytNdRs0Rqr6Voj68N3SZZEDeftU0BKEgtkbF+p6uoRjyxgwwFlYwBoGlYT7Tc1IEq8PXYLLiOEOA3Win0awyO53tM0qATpdpNjN8XSc3LACNyY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=KnaaY6Tj; arc=none smtp.client-ip=209.85.128.41 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="KnaaY6Tj" Received: by mail-wm1-f41.google.com with SMTP id 5b1f17b1804b1-43ce71582e9so6608215e9.1 for ; Thu, 29 May 2025 04:33:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518397; x=1749123197; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=+Nc8ucW60XE4Jn3cBqaPeV8SZm/My/nwOffHN5F4rVM=; b=KnaaY6TjR4AICoV2JJrqWG1W0pSC7v+0G8uQtLOhKzoHGidv8xYyDbaIE3NV6ecKIJ PIShn1HZ3xXuN5wcngBBy1IqHnBfgyh5iLEpHgz7s/rt5l2Ee3un8kdFSWP7B8R94b8G 6bkChmSgAgI2Bjzc2/vIOLFvuVcezzx4q4ROlhLkPoWMdxABPA3cMi8f//BXKidjVbmS 6ciRDuKwzqGkzpDfYKaAGpS0FggZw0jZKAEsE83h/fyyJSrsY+P9xFTC0DRBZgRjIth+ CfLrKQeyGFHjf45N+X0BkbjHFuvxIZSD6vEBo8XyQ24CGgdUk4ciBpUbWmf+Qv+62Id4 /69A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518397; x=1749123197; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=+Nc8ucW60XE4Jn3cBqaPeV8SZm/My/nwOffHN5F4rVM=; b=Tuy43dhXy5HLC3jDxKz5DdEUYYe0VCNDSRbzSR+M5AfT8uENUZzt6XpoY7rV6YgOeG kYQimTLr835MLDA0/bOCCXfWdxmPp2WrANDyyfYCXfjDWyE2hBTqaJe2QApp4K6lv5V+ NNRKq5LWJcj0x8/1Ra1HEKf7EFverZ7RIHmDzSoYt0sUM8nlk0S8v/S5MeTBGM8avKwJ LwkSt4VN+XXPQLZ9DB1AMT0n8o7QagHj/o4/OEGr7fdaGF5YxddhLSj3RB9zIkp/R87W Bnbcz1KswYxKMFLggrKIwnyksA+MQYE37k934FG+Txldw1UaB9C7DZxJhwgV9zePCEni fk5A== X-Forwarded-Encrypted: i=1; AJvYcCVGG9VhdBNg3kcp0zggobKV/GYkdjBnelAGTXi5obLzJNRMuUkcBY8bkWD+iD0zx/8lkQmKIiq4sbWTDdc=@vger.kernel.org X-Gm-Message-State: AOJu0YwM8jXis4glN+MOtLa9vOg9baxkFrrKLDJ9TaZ1NABX0p6eJO78 ieYPFAHBL4phUrJ2ZBOb7OfAUoUlS2BqLeYaX9OQvDnCYJsjOsDhdGpAX475UoKq7JA= X-Gm-Gg: ASbGnct02xXVTGjTJYhNOfxfY9ItDgbl1amqVsI2RD5GSQ46yNnw4nUyoDu+lR9KJ1t u0xxtgl5GBqmTKd4eZKzrmnSSga8w2aXb9akM/uxJ+PsWe2HnQx1jXEmtERGluOJxBIKpeYllTK aLHgfdUFjO7sBBcE8semiGdzkAxPZFfzqX5LhrhItwZw6ChDpZ3hZ3qiq16v+VNCpvgkYCp/NCa wq9WFPnIJV5Jgm/lDurfEAkJs6Zvlwx1Ywd454mXhXuIuv9748ExTyHL2adh4j9T/4oq5px0hGg C04YKkqBknU6M8amvb3a2aJGjdfmQycwIACZ7Nnmq0z9Mks6yf2LVhOuV7Hf X-Google-Smtp-Source: AGHT+IEKUlq+VjysuU7OFlzmN9WWwVOAQRlwZk1C8MZ05ufCqPWjkB/S4hXmEcNWVtw0X6JufGjbcw== X-Received: by 2002:a05:600c:621b:b0:43c:fffc:786c with SMTP id 5b1f17b1804b1-44fafbf883dmr95464645e9.19.1748518396915; Thu, 29 May 2025 04:33:16 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:16 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:27 +0100 Subject: [PATCH v2 06/11] KVM: arm64: Add trap configs for PMSDSFR_EL1 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-6-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 SPE data source filtering (SPE_FEAT_FDS) adds a new register PMSDSFR_EL1, add the trap configs for it. Signed-off-by: James Clark Tested-by: Leo Yan --- arch/arm64/kvm/emulate-nested.c | 1 + arch/arm64/kvm/sys_regs.c | 1 + 2 files changed, 2 insertions(+) diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-neste= d.c index 0fcfcc0478f9..05d3e6b93ae9 100644 --- a/arch/arm64/kvm/emulate-nested.c +++ b/arch/arm64/kvm/emulate-nested.c @@ -1169,6 +1169,7 @@ static const struct encoding_to_trap_config encoding_= to_cgt[] __initconst =3D { SR_TRAP(SYS_PMSIRR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSLATFR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_PMSNEVFR_EL1, CGT_MDCR_TPMS), + SR_TRAP(SYS_PMSDSFR_EL1, CGT_MDCR_TPMS), SR_TRAP(SYS_TRFCR_EL1, CGT_MDCR_TTRF), SR_TRAP(SYS_TRBBASER_EL1, CGT_MDCR_E2TB), SR_TRAP(SYS_TRBLIMITR_EL1, CGT_MDCR_E2TB), diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 5dde9285afc8..9f544ac7b5a6 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -2956,6 +2956,7 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access }, { SYS_DESC(SYS_PMBPTR_EL1), undef_access }, { SYS_DESC(SYS_PMBSR_EL1), undef_access }, + { SYS_DESC(SYS_PMSDSFR_EL1), undef_access }, /* PMBIDR_EL1 is not trapped */ =20 { PMU_SYS_REG(PMINTENSET_EL1), --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f45.google.com (mail-wm1-f45.google.com [209.85.128.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4984C28FA9C for ; Thu, 29 May 2025 11:33:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518402; cv=none; b=mDCgr+4f1JRRxXYEk7VaRY2DwvQgoElHxZu3HPHLB8O4ysyNkMUKDg5p3Jw6Myzkgw9jbGX9tuwOaS5er7ewMjmdBtcdewn2goXlW1t+i4PFQ68Xk2yeKTYFe5wSTAUCm2es+KOPmdTjdSDDWrX0+310O4H4dhKQKZFKuWbaVAg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518402; c=relaxed/simple; bh=zvP1e+1MWcLi6dFHbap1BiJEf/Gwy+p9o8HThmnNJIg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fACNnXH3/JMiUWh8xAw6R8b40kBNMLWrdXo50dO82b6U9wk5SZJa3REZ1bR54fzy/J7Pp/jPZIztj357EwSw89yQ+s/5qa1OcVmiqB+8W/eVq1HzSFFGuxc/BtpfBOvErdwQy6BCMcJGPyJLIFBA/u0SGbMHgQ5OO+Xt/VJNEk0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=wvVgcuA+; arc=none smtp.client-ip=209.85.128.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="wvVgcuA+" Received: by mail-wm1-f45.google.com with SMTP id 5b1f17b1804b1-43cfe574976so6794935e9.1 for ; Thu, 29 May 2025 04:33:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518398; x=1749123198; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=/Q5mn8xtPi9u9sDm1H7ybxkZxNw4efqIccO1SNVExHM=; b=wvVgcuA+BdOAbJAq1FcDO4QE/WkBblcRUu7/mKb7FXqpc+zkCbUIoIAJEuRInY7FNc W5yI80pnk5kNbqos8HgaA/+U8wX4bEfDK8ttvmvABPINcOxOgOsedQuZkxxjNKUWuLmA AIDn3Ogi1YBNIN1I8YIYp2FaBPYwQeSFqamM2dG31ExILT2upE7hY9nKlz3yep8T8I2m Zp45j1wJ8ZfgvVeTP8nA9UfRPx0NHEe7r5N0dvh5aSOi5iDybU1QKbPBom08WGfZicV3 Raw2RF5x5w6NSJbM1ynY2NI00V0A1wJzx3XQm0suw18zdW/x38F8z7CvRdfU4HcIMcu1 BCMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518398; x=1749123198; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=/Q5mn8xtPi9u9sDm1H7ybxkZxNw4efqIccO1SNVExHM=; b=Zgq/ciXD1cbQV/DkTDWd6sojm3+xn1iEsIAONZYfukoo25a1f1yCnFdW0l1IkWF4/p 2XlgJQREGFoMN3jwCIUsk8XTDNNslDeYLswdIDD5OUpM0Ub5YotsoMiMkAb9kJTUjMhl 7yPVzGX5OwBl5AmKgaKwrbzvfja0mWSXHjiMpkWBM5z6HchqQLiv44S3RZ3DecDmz9vM nQO31mYSaGf20wpG1UB/DlelVFSgOa2BkM1wRMmvdpmlZK2b0b6r8pWmhNTPwA/NgH/v WN5CrzNHZf6W+jyG7EPQHA9uapducVak7SGtYWJzlu9x8ZavyiG+UpggBOkSEuwpFTe+ aPgw== X-Forwarded-Encrypted: i=1; AJvYcCWFPbPyPlHO2RRXxuASn49/v/nG0nNsq/1+nxEwkNagvnyMs6X/fuREQDELy1OQclXZJ3NqLM4F3v9wQy0=@vger.kernel.org X-Gm-Message-State: AOJu0Yy6zFb8LbJFA2Y1LosOsmZPuBVhzRSxGO/MPpvSn78xUpkF2eBH iF+Qq2BlFzW54TNSAMfDla7StoZYe008SUk6fz3nL4CIxvM9tL3nV2OT68Ti07J3dI8= X-Gm-Gg: ASbGnct4Ie1MHSvT+8zzOZa+//sffq99dyOSk7dvUFZmC9sbfhWbp7+cA2Gi/zXXnUa FnWkrUEJx1u1Wjz46sWllHkEi1iPd3I0FTAh9VbGuTXkMjnXByIapVVGb1x/ZPpvTDX34Ww0DZD gMQTAvYPGjzDAo3nvRjxC083Dr5lvxrVhmHo0hv/gkytHrKYO2x4FUbXHZ8RBtYJvMzQkuzKKJc vYuada3OvC/zfFubqtc/3djpm2plJYQ9NJRYIphfGZAhXxd+Gp6Bv/NGhPbxuwVFuDpqDeY1oMS VYYE4lEK6XfHGUhTXZXUT/l6cefUEpV6DSW/StmJ+tM8wLyX2sSXrj8aHRNhh+TWBGJH50g= X-Google-Smtp-Source: AGHT+IFacLMgy8Sgufz8crND9drSgOY6qRlCAWckmK5shHNZ9zSnAptuNxdT/H2WMCBvDy1/kfCobg== X-Received: by 2002:a05:600c:1d8c:b0:43c:e478:889 with SMTP id 5b1f17b1804b1-4506b541d07mr59510265e9.0.1748518398270; Thu, 29 May 2025 04:33:18 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:17 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:28 +0100 Subject: [PATCH v2 07/11] perf: Add perf_event_attr::config4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-7-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, Leo Yan , James Clark X-Mailer: b4 0.14.0 Arm FEAT_SPE_FDS adds the ability to filter on the data source of a packet using another 64-bits of event filtering control. As the existing perf_event_attr::configN fields are all used up for SPE PMU, an additional field is needed. Add a new 'config4' field. Reviewed-by: Leo Yan Signed-off-by: James Clark Tested-by: Leo Yan --- include/uapi/linux/perf_event.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/uapi/linux/perf_event.h b/include/uapi/linux/perf_even= t.h index 78a362b80027..0d0ed85ad8cb 100644 --- a/include/uapi/linux/perf_event.h +++ b/include/uapi/linux/perf_event.h @@ -382,6 +382,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ +#define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ =20 /* * 'struct perf_event_attr' contains various attributes that define @@ -543,6 +544,7 @@ struct perf_event_attr { __u64 sig_data; =20 __u64 config3; /* extension of config2 */ + __u64 config4; /* extension of config3 */ }; =20 /* --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f42.google.com (mail-wm1-f42.google.com [209.85.128.42]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5887528FABB for ; Thu, 29 May 2025 11:33:21 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.42 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518403; cv=none; b=cU7krh6amGFVQroxVIJvjklQObccYfr3RWn/RnrpzBrmTwbvEzlFINiXGRI/NG8CZmMkmkjnpgy9A7OR97F20DrSYFQ9SqgldELxpNIpbcuq3uwGkdLzOmn3j36Di780/g48FSdhh5qXW+JTjysmn/CYN94VPbAAXk73x2l6MxA= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518403; c=relaxed/simple; bh=HnsvEDgYCsBo5G8yWPXIzHJBnobLrqsoKSo90S0gH00=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s4bSFymekEvxni1ULBD8X1/aejgMcGApN1VBu7YO8Q3SWoO1As4bTJ51fNbjxU2tduCTNuQAWYJCDTNYvyNVbtN9JXTRRhG4UcfDz2IAgtmjdgVoGvHHER3rxqWxWfjJ3gQQE9KcL+pDQsYdYK+oVOCZk8LtuaOIH/C+zElKFO4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=Rdp28b7H; arc=none smtp.client-ip=209.85.128.42 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="Rdp28b7H" Received: by mail-wm1-f42.google.com with SMTP id 5b1f17b1804b1-43cfe574976so6795155e9.1 for ; Thu, 29 May 2025 04:33:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518400; x=1749123200; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=hFtizqLb9AdbPIP2xG9Ud/C06SCBb70bCrr/xyknRBQ=; b=Rdp28b7HcAkvssTGXgXyzf2eVf1cL9h7/Wmq32rf10JmrnUd2ZaD5Sue3+jLYhTIA/ FNbWUUrmlZ+OYVqVZbuiHK/5Wmcn+iefL5iJT8mbFkIRvkQn2cgIRYceYTkHRPpyLR9l MUrbpPtv4Spkfxv5uGyoC6x9qsilvpDMwstogmfTehKI62Eyqovr8JAnYbRDxk/SSuQT hBwcqNdNkCQkolxjekFjutKn34jZ2PHcWROZBNN+K+TEl+fVFYBwTex7ZlsrM/h5Nm1F Ya/ulLIaHWfEiZqpepY7U6MeBWuWuZRWGbOQMG8eyYPRujwJNcP8We+8G+s+hcqMIqnU 83YA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518400; x=1749123200; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=hFtizqLb9AdbPIP2xG9Ud/C06SCBb70bCrr/xyknRBQ=; b=eGy5ov0chixFG9AQKd7KlnOPR8FY3kD9Uq2WgY2jMgOiU8VjM4eGTr3A/qV4SLGBKj DYbiw/+dmdIou8I/Hb4kvT9/8ULvd/tSG1BRXGGtmcDISqkC2cnYu7dxCC+AWCcuopz1 M+/XDDZWOGrXIotcjL3SFZiGepsd/9QoJcD5VgUBcQAy89Spu7CmSpakE0t3JtFpHXSk 7S42GUzhVBczCfIDgPMgngxssYVSGuW+AQWE9anc8i9lT+NIvcJVdBuHTonFW3hLBQmk qMKS7BgYY9SURg52uqjTi3wHLIX1htfuD7wO5Zf1VPfY6gZiskSHRA6eRnbK63KqC7Kb T+ow== X-Forwarded-Encrypted: i=1; AJvYcCUSiivydNs0AJ/81u/nDk373Tb+qBsk3S/l43c1DEkLzmr8OOUo4XRjbNMA4D0AYF5XCcYBp6GrUNLvQ30=@vger.kernel.org X-Gm-Message-State: AOJu0YwZrh7MsKsc9b//IeM3TPNqQugfsHmPNaXqf7+A7XAzrxnRqqz8 YuCvkjcxtpUfWAunA/MM0TqT/BgB4UY6f2lwQt1xO4FwCLqqiBuNum89PAobrl29xMM= X-Gm-Gg: ASbGnctxEWE9YvD9/IP57Xi3sNiATEN2pgopGuwfe8vr5CmVXIlgYR1EDkFz+1odQiu jtKHFjaiIFdQ+Hz+xaiM5h9cxNaiDVZsOf90VZ4j+dpR8sShs9eVuHq7BNwAnHgwieHbT/MjcyI P8KjkuVY8wP4Xcgvi1c9g0jWzX+pGg3f5AEWBEqc5GOWGh+K4x4/i6J2tY5Ls4ZT6DbFq3Qu5dh ClFC4ejbRTqZcXOm4nAUGFKcpq4R+F4A3qdUj3f8q/ZMCF8QP3iIRTolj0q4NC4rv6s4AxKTmZF KrfRMXxvm4tUIL3mFIUcSkWdL7k17VKKKY5pq6M6/x7g+m5EtilMtT4aoU1E X-Google-Smtp-Source: AGHT+IGimy6ZJ9K4F4atDZc7N5EcbAuC+37QDbioDnIXH/PmwoUz6QxTIrXaAGlqmLwxYEe63f5+gQ== X-Received: by 2002:a05:600c:810e:b0:445:1984:2479 with SMTP id 5b1f17b1804b1-45072545a3emr53537625e9.5.1748518399707; Thu, 29 May 2025 04:33:19 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:19 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:29 +0100 Subject: [PATCH v2 08/11] perf: arm_spe: Add support for filtering on data source Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-8-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, Leo Yan , James Clark X-Mailer: b4 0.14.0 SPE_FEAT_FDS adds the ability to filter on the data source of packets. Like the other existing filters, enable filtering with PMSFCR_EL1.FDS when any of the filter bits are set. Each bit maps to data sources 0-63 described by bits[0:5] in the data source packet (although the full range of data source is 16 bits so higher value data sources can't be filtered on). The filter is an OR of all the bits, so for example setting bits 0 and 3 filters packets from data sources 0 OR 3. Reviewed-by: Leo Yan Signed-off-by: James Clark Tested-by: Leo Yan --- drivers/perf/arm_spe_pmu.c | 31 +++++++++++++++++++++++++++++++ 1 file changed, 31 insertions(+) diff --git a/drivers/perf/arm_spe_pmu.c b/drivers/perf/arm_spe_pmu.c index 9309b846f642..d04318411f77 100644 --- a/drivers/perf/arm_spe_pmu.c +++ b/drivers/perf/arm_spe_pmu.c @@ -87,6 +87,7 @@ struct arm_spe_pmu { #define SPE_PMU_FEAT_INV_FILT_EVT (1UL << 6) #define SPE_PMU_FEAT_DISCARD (1UL << 7) #define SPE_PMU_FEAT_EFT (1UL << 8) +#define SPE_PMU_FEAT_FDS (1UL << 9) #define SPE_PMU_FEAT_DEV_PROBED (1UL << 63) u64 features; =20 @@ -232,6 +233,10 @@ static const struct attribute_group arm_spe_pmu_cap_gr= oup =3D { #define ATTR_CFG_FLD_inv_event_filter_LO 0 #define ATTR_CFG_FLD_inv_event_filter_HI 63 =20 +#define ATTR_CFG_FLD_data_src_filter_CFG config4 /* PMSDSFR_EL1 */ +#define ATTR_CFG_FLD_data_src_filter_LO 0 +#define ATTR_CFG_FLD_data_src_filter_HI 63 + GEN_PMU_FORMAT_ATTR(ts_enable); GEN_PMU_FORMAT_ATTR(pa_enable); GEN_PMU_FORMAT_ATTR(pct_enable); @@ -248,6 +253,7 @@ GEN_PMU_FORMAT_ATTR(float_filter); GEN_PMU_FORMAT_ATTR(float_filter_mask); GEN_PMU_FORMAT_ATTR(event_filter); GEN_PMU_FORMAT_ATTR(inv_event_filter); +GEN_PMU_FORMAT_ATTR(data_src_filter); GEN_PMU_FORMAT_ATTR(min_latency); GEN_PMU_FORMAT_ATTR(discard); =20 @@ -268,6 +274,7 @@ static struct attribute *arm_spe_pmu_formats_attr[] =3D= { &format_attr_float_filter_mask.attr, &format_attr_event_filter.attr, &format_attr_inv_event_filter.attr, + &format_attr_data_src_filter.attr, &format_attr_min_latency.attr, &format_attr_discard.attr, NULL, @@ -286,6 +293,9 @@ static umode_t arm_spe_pmu_format_attr_is_visible(struc= t kobject *kobj, if (attr =3D=3D &format_attr_inv_event_filter.attr && !(spe_pmu->features= & SPE_PMU_FEAT_INV_FILT_EVT)) return 0; =20 + if (attr =3D=3D &format_attr_data_src_filter.attr && !(spe_pmu->features = & SPE_PMU_FEAT_FDS)) + return 0; + if ((attr =3D=3D &format_attr_branch_filter_mask.attr || attr =3D=3D &format_attr_load_filter_mask.attr || attr =3D=3D &format_attr_store_filter_mask.attr || @@ -406,6 +416,9 @@ static u64 arm_spe_event_to_pmsfcr(struct perf_event *e= vent) if (ATTR_CFG_GET_FLD(attr, inv_event_filter)) reg |=3D PMSFCR_EL1_FnE; =20 + if (ATTR_CFG_GET_FLD(attr, data_src_filter)) + reg |=3D PMSFCR_EL1_FDS; + if (ATTR_CFG_GET_FLD(attr, min_latency)) reg |=3D PMSFCR_EL1_FL; =20 @@ -430,6 +443,12 @@ static u64 arm_spe_event_to_pmslatfr(struct perf_event= *event) return FIELD_PREP(PMSLATFR_EL1_MINLAT, ATTR_CFG_GET_FLD(attr, min_latency= )); } =20 +static u64 arm_spe_event_to_pmsdsfr(struct perf_event *event) +{ + struct perf_event_attr *attr =3D &event->attr; + return ATTR_CFG_GET_FLD(attr, data_src_filter); +} + static void arm_spe_pmu_pad_buf(struct perf_output_handle *handle, int len) { struct arm_spe_pmu_buf *buf =3D perf_get_aux(handle); @@ -788,6 +807,10 @@ static int arm_spe_pmu_event_init(struct perf_event *e= vent) if (arm_spe_event_to_pmsnevfr(event) & arm_spe_pmsevfr_res0(spe_pmu->pmsv= er)) return -EOPNOTSUPP; =20 + if (arm_spe_event_to_pmsdsfr(event) && + !(spe_pmu->features & SPE_PMU_FEAT_FDS)) + return -EOPNOTSUPP; + if (attr->exclude_idle) return -EOPNOTSUPP; =20 @@ -857,6 +880,11 @@ static void arm_spe_pmu_start(struct perf_event *event= , int flags) write_sysreg_s(reg, SYS_PMSNEVFR_EL1); } =20 + if (spe_pmu->features & SPE_PMU_FEAT_FDS) { + reg =3D arm_spe_event_to_pmsdsfr(event); + write_sysreg_s(reg, SYS_PMSDSFR_EL1); + } + reg =3D arm_spe_event_to_pmslatfr(event); write_sysreg_s(reg, SYS_PMSLATFR_EL1); =20 @@ -1116,6 +1144,9 @@ static void __arm_spe_pmu_dev_probe(void *info) if (FIELD_GET(PMSIDR_EL1_EFT, reg)) spe_pmu->features |=3D SPE_PMU_FEAT_EFT; =20 + if (FIELD_GET(PMSIDR_EL1_FDS, reg)) + spe_pmu->features |=3D SPE_PMU_FEAT_FDS; + /* This field has a spaced out encoding, so just use a look-up */ fld =3D FIELD_GET(PMSIDR_EL1_INTERVAL, reg); switch (fld) { --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f46.google.com (mail-wm1-f46.google.com [209.85.128.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EF877290084 for ; Thu, 29 May 2025 11:33:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518405; cv=none; b=oGiY3PHcEmFpyLYII4JPtST7Iy0maD+wMJc0rCQXmQrAN6UdZYovpBwLJcUso8umgb1YUn6TkNRyQK0VpoMstru49nG16oCedvD1PPW0evt8FHYwmB6zBUfJKIqzd9Z1X/yMmCK842kVG4+kRsKRsFc6nxiDw9S90DkssXfY8+U= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518405; c=relaxed/simple; bh=luGNkoeE8UlMJRKbxQ1WFt67Ydxa/TXTNRQ7E6/zPH8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=SrWzZ/w4e5oeedzwXEgx9mLhYsZuZ/yVma5UOCda702M938tUgpQ7yWeO0OZyhWrLtumyymAvzWnTI+DyMjo7O1KAIzd8wd/1wQN+IeiT40aPtVggoluWOa6qClZwu5ENOL/IShK077YOcRmbCJKqrI7MR/OT7x5JoSIIc2fM5Q= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=rjFHV2j4; arc=none smtp.client-ip=209.85.128.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="rjFHV2j4" Received: by mail-wm1-f46.google.com with SMTP id 5b1f17b1804b1-450ce3a2dd5so6681555e9.3 for ; Thu, 29 May 2025 04:33:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518401; x=1749123201; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TtNy8TV2Q7tdQ7rYLolUVZZNcwM6dcUvbileCfs7vIE=; b=rjFHV2j4uVy3MQgfdfvTMCHm8VuLc588kKmVuvvKKi+z8wC/D6yf+icdyojhvpQEeV PCulage6GBERJhvl3c9ujwirVDKsLHf1yyN4tn8y3sljY1wsYbuEOR7I33qkWBqcF6ll wxApjPpuRLgjdhHLKn2M+N9I04vmo9ajjDWTiUcFoVxUepCR5yVkwQU+PiK3hC8hwu9B 9Rcvi7eRaZwfN+J7y1w3T/3Rcs31sKoulU+hxLAZ/30xd9symOF/+kOwYkIyR8Vs6L69 SPNgBJb4TRYn6oItDc1Rjep+qL+1BEYFNq47lkh3A6ff+cLf2JrxDayNTYOzAC5RD+MW iUXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518401; x=1749123201; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TtNy8TV2Q7tdQ7rYLolUVZZNcwM6dcUvbileCfs7vIE=; b=piskOmyiRsyFERi6Z4kXg9br6DQOpjf1ZgI99Nf4E1A01W+F1HZ5B35Y/OnoULoKKH hRjxQgBfvLGdv8OONvrNvL1WaOyZADacCn07Mv3w2DMsberLpQEoi5DuibhFhQseBIkI IzpjvB6iyPTJYahDTV/jSwdZSuCYFs8tjfztfgxTh9jHuMDjGnShxPoQBXlpZLH4keYW 8PJShfSONKax567iuB90usqKTJ3s6ckW1GZGZ/Gvs199FVCBol18ZtH9BaQeQrbye5B4 1inO1OJ9jqLpjB6WUg2XmGbsmUBu6OO5BA97VjA4RoyJvLVad7oFhJz3bxo8J5+hUo9c i0+Q== X-Forwarded-Encrypted: i=1; AJvYcCWKe4XMh07JfwmNDlQ52riXoMrVRIdY8jxbuMrJm5ZZHFIdGdS5dHH44D5gRng803yJQ1rLpwN51Z7BZ+w=@vger.kernel.org X-Gm-Message-State: AOJu0YxXaB9p8Gn8AkzIU8MGvWAQRNPV1+y2p6lHHPhKTvw+xp5Sxcc0 9Ir5L/OoQixnqrACskPB5dBk5HBOSvFenNH6ikRpQPfZ7W3EAp15PktG17/mJ6f2LAU= X-Gm-Gg: ASbGncuOrV67LJTgp3lwANyYipoR1p+MaWcX4/CBbHy2+RD+e1/ILYvfs5t//WVr9dr jcjG2TPvhXr17I0pPGEarV9vBuBa1py1YB9fGwb+EyhkeFqyf3d9iOJ5x307gc4mjXdFsc8HdZx 6X5b5jwwsy9fc4oMe+C9e5oBOGGmGynKqbWFrN+zxjWjDdfZYsrUXbFoyYeYFzkyNH8dMHOTkrw 5FcPFII2RWarhnD25NXl7myzD3uCPlOWwgqHPaGS5SZdql/s21C8WNvHli8fnvXsEXE7G+ecjqg hK4U9krulzXtFTHCEDw5rorKBEsiVeBJ74A1brM/dej+M50D9BW9Ko68Ce3B X-Google-Smtp-Source: AGHT+IHrXdHKaLMm+1yIpS3FqW954SUKKGaokrQq0Fw7uhbVyrwkEnNO9Y6DJeAGvxM0rmC8BWFyjw== X-Received: by 2002:a05:600c:8411:b0:43c:fe15:41cb with SMTP id 5b1f17b1804b1-44c91fbb039mr231750785e9.15.1748518401174; Thu, 29 May 2025 04:33:21 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:20 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:30 +0100 Subject: [PATCH v2 09/11] tools headers UAPI: Sync linux/perf_event.h with the kernel sources Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-9-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 To pickup config4 changes. Signed-off-by: James Clark Tested-by: Leo Yan --- tools/include/uapi/linux/perf_event.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tools/include/uapi/linux/perf_event.h b/tools/include/uapi/lin= ux/perf_event.h index 78a362b80027..0d0ed85ad8cb 100644 --- a/tools/include/uapi/linux/perf_event.h +++ b/tools/include/uapi/linux/perf_event.h @@ -382,6 +382,7 @@ enum perf_event_read_format { #define PERF_ATTR_SIZE_VER6 120 /* Add: aux_sample_size */ #define PERF_ATTR_SIZE_VER7 128 /* Add: sig_data */ #define PERF_ATTR_SIZE_VER8 136 /* Add: config3 */ +#define PERF_ATTR_SIZE_VER9 144 /* add: config4 */ =20 /* * 'struct perf_event_attr' contains various attributes that define @@ -543,6 +544,7 @@ struct perf_event_attr { __u64 sig_data; =20 __u64 config3; /* extension of config2 */ + __u64 config4; /* extension of config3 */ }; =20 /* --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f47.google.com (mail-wm1-f47.google.com [209.85.128.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 887A728FFCA for ; Thu, 29 May 2025 11:33:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518406; cv=none; b=Ts7vzOtCw7gxoYwioNNGHzReGWTxyyEgDsv1aN4BZ1pd9GKw1wwBCyrDmpFQ17xfjIrzZXRsznvZdAKPlRYGBbqHSg9Wsx/fC6CjL+cWA9XZ3GkDsz5WnQWPIZor7kA/1wTNVVPC7ly+jSUkmHY4cTrwoFUfb3+fcdbWSprMVLg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518406; c=relaxed/simple; bh=fv8zs7U4SClL58XDHSkZwnh3zEUlaOm5ycAnfP1gusM=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ob5wHn2zRtJ32Mn/9w0afmypoEeTsVSS8suivTBtxK/gx1YESF+yTymiJGAfYeEkebhlz2izn4iwVlAWNk+L/2NEAwNI14JYtwWC0/tOre387dYuz645u/QHpN15rqZQasOS8RLAsjoSBeyAUnw2YS0GjovT4FGlx/JJqGJ1jUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=UongR5c0; arc=none smtp.client-ip=209.85.128.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="UongR5c0" Received: by mail-wm1-f47.google.com with SMTP id 5b1f17b1804b1-43ede096d73so6166365e9.2 for ; Thu, 29 May 2025 04:33:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518403; x=1749123203; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=qITqjVqZrl9SX6GSxZHwr88LBNU/7n9MeuQuQ3uKHDc=; b=UongR5c0J2Fmr75OfhnDi8wuvDmAKMu5oUPcVRSxR5qhsN1i8/YWjPyH2r6v6c3061 tFPQdbEh/gRCtrLh6+mwOc4biFWENVwoGAXouewlGWlKaomE1EFjNMEffq0u+Tm3PBeQ Dr8Z9P+9HDTttAiW3er0EFKRxPoe1e8HVeKRXsJXhT1Vi41hIlXGLjqZcpt61gpghBcI 6ecos1TXYUzREranCylbRxnHG3MQBChZOPqBWST3QhRXSyhZrx2rJPtl5p/nuh7sWWIG 0aTjrO19nrwWMn6Ai3nockvBfzGvn2Bqs+Qoyv9M3F7kmQI7+ycR+XSpcUOxz/zic0bt QnGw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518403; x=1749123203; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=qITqjVqZrl9SX6GSxZHwr88LBNU/7n9MeuQuQ3uKHDc=; b=kJunC2mO/G5gcsBVrlWbHzTCr5kgkvMDrbHMS9zhtuM8kNgBuf2lrXWLO7nVVZ4CV8 zWmxU8kGM+vmxAbKmy4mWrp2kz/KoIp+v0/W6sjS5VREG2aZEbx1AcU6JV/N0fWoA0Za ehPu1PQsmwrTzW0OebrKSsXok4Fy13iO7FEpUqM+1j4MN0T+lXSkbGGOXAEQup7YgtQ6 MxeL+EzBMYkosZaQ7+rn6SAn0UMyItA9LWB2PYh8hi/fAr8vk22gM1ji1fPEOb+y3PYn RWlBbCBIZpRsp6FHfh5+PULWsxcyFfwVS9kKXyTNkFmHao0l2DnGldUpOd31ZNuhQCad 0CzQ== X-Forwarded-Encrypted: i=1; AJvYcCUeyqM4v8fS9WlqJgJr/WskTNJJdUnL72G+rgpG1uRcYSL5x4fmLo8xNNbrxz6XsQdKJjynZhM2PbJNE6w=@vger.kernel.org X-Gm-Message-State: AOJu0YxF/ED+d0rm7+junuAKx75wvi4muWe7MPw399xxvgHN92NeXUJI vmTeL6a5PLg5dP8LitfXttEM7AXbVlvJyaGxRgRUqqP3km1a8Tt69g2uYfS6Z0YLwy8= X-Gm-Gg: ASbGncvcLbIlSX6whnVBGzJn4Erygks3wnaoauYMyXg4/r1R1cWOPRPbmZiUdEmXzPy cUqi1I3EFzBUfZkMcQchnLjJsS1iBjVZMxBECHFqs8XmgHVJA7nXmJQa02c9I/lYsTIHMZxPieV uJW2Cy1J+AcU1zV6XCvh2iBBAIjJtFP9dmtaRv/78k97qfSRivAw+oW92wrBGJjVdw7LBvSqW21 rprRygy45BPeE26a7rRBWlb1Gn/aUVih/9p9SZcvWpA2YXaEb9lPG79Z5EF/JtwoR/dw7m5ZY0Q m9iPFbM/qk6YhdgJ8eZgdrgfaM0VGQG9AlmYnodDb/SDWbxGc1tGvrqjpYEn X-Google-Smtp-Source: AGHT+IG4188DaxQr4q1DiAwcRxaSKT7JPRQ1HaA18jMnppKU9PUElMmbbzXeEo99MB4ggugZlyN3Lw== X-Received: by 2002:a05:600c:4592:b0:43d:17f1:2640 with SMTP id 5b1f17b1804b1-44c92a549d2mr188083195e9.26.1748518402784; Thu, 29 May 2025 04:33:22 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:22 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:31 +0100 Subject: [PATCH v2 10/11] perf tools: Add support for perf_event_attr::config4 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-10-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, Leo Yan , James Clark X-Mailer: b4 0.14.0 perf_event_attr has gained a new field, config4, so add support for it extending the existing configN support. Reviewed-by: Leo Yan Signed-off-by: James Clark Reviewed-by: Ian Rogers Tested-by: Leo Yan --- tools/perf/tests/parse-events.c | 14 +++++++++++++- tools/perf/util/parse-events.c | 11 +++++++++++ tools/perf/util/parse-events.h | 1 + tools/perf/util/parse-events.l | 1 + tools/perf/util/pmu.c | 8 ++++++++ tools/perf/util/pmu.h | 1 + 6 files changed, 35 insertions(+), 1 deletion(-) diff --git a/tools/perf/tests/parse-events.c b/tools/perf/tests/parse-event= s.c index 5ec2e5607987..5f624a63d550 100644 --- a/tools/perf/tests/parse-events.c +++ b/tools/perf/tests/parse-events.c @@ -615,6 +615,8 @@ static int test__checkevent_pmu(struct evlist *evlist) TEST_ASSERT_VAL("wrong config1", 1 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 3 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); + TEST_ASSERT_VAL("wrong config4", 0 =3D=3D evsel->core.attr.config4); + /* * The period value gets configured within evlist__config, * while this test executes only parse events method. @@ -637,6 +639,7 @@ static int test__checkevent_list(struct evlist *evlist) TEST_ASSERT_VAL("wrong config1", 0 =3D=3D evsel->core.attr.config1); TEST_ASSERT_VAL("wrong config2", 0 =3D=3D evsel->core.attr.config2); TEST_ASSERT_VAL("wrong config3", 0 =3D=3D evsel->core.attr.config3); + TEST_ASSERT_VAL("wrong config4", 0 =3D=3D evsel->core.attr.config4); TEST_ASSERT_VAL("wrong exclude_user", !evsel->core.attr.exclude_user); TEST_ASSERT_VAL("wrong exclude_kernel", !evsel->core.attr.exclude_kernel= ); TEST_ASSERT_VAL("wrong exclude_hv", !evsel->core.attr.exclude_hv); @@ -813,6 +816,15 @@ static int test__checkterms_simple(struct parse_events= _terms *terms) TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 4); TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config3")); =20 + /* config4=3D5 */ + term =3D list_entry(term->list.next, struct parse_events_term, list); + TEST_ASSERT_VAL("wrong type term", + term->type_term =3D=3D PARSE_EVENTS__TERM_TYPE_CONFIG4); + TEST_ASSERT_VAL("wrong type val", + term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); + TEST_ASSERT_VAL("wrong val", term->val.num =3D=3D 5); + TEST_ASSERT_VAL("wrong config", !strcmp(term->config, "config4")); + /* umask=3D1*/ term =3D list_entry(term->list.next, struct parse_events_term, list); TEST_ASSERT_VAL("wrong type term", @@ -2451,7 +2463,7 @@ struct terms_test { =20 static const struct terms_test test__terms[] =3D { [0] =3D { - .str =3D "config=3D10,config1,config2=3D3,config3=3D4,umask=3D1,read,r= 0xead", + .str =3D "config=3D10,config1,config2=3D3,config3=3D4,config4=3D5,umas= k=3D1,read,r0xead", .check =3D test__checkterms_simple, }, }; diff --git a/tools/perf/util/parse-events.c b/tools/perf/util/parse-events.c index 5152fd5a6ead..7e37f91e7b49 100644 --- a/tools/perf/util/parse-events.c +++ b/tools/perf/util/parse-events.c @@ -247,6 +247,8 @@ __add_event(struct list_head *list, int *idx, PERF_PMU_FORMAT_VALUE_CONFIG2, "config2"); perf_pmu__warn_invalid_config(pmu, attr->config3, name, PERF_PMU_FORMAT_VALUE_CONFIG3, "config3"); + perf_pmu__warn_invalid_config(pmu, attr->config4, name, + PERF_PMU_FORMAT_VALUE_CONFIG4, "config4"); } if (init_attr) event_attr_init(attr); @@ -783,6 +785,7 @@ const char *parse_events__term_type_str(enum parse_even= ts__term_type term_type) [PARSE_EVENTS__TERM_TYPE_CONFIG1] =3D "config1", [PARSE_EVENTS__TERM_TYPE_CONFIG2] =3D "config2", [PARSE_EVENTS__TERM_TYPE_CONFIG3] =3D "config3", + [PARSE_EVENTS__TERM_TYPE_CONFIG4] =3D "config4", [PARSE_EVENTS__TERM_TYPE_NAME] =3D "name", [PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD] =3D "period", [PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ] =3D "freq", @@ -830,6 +833,7 @@ config_term_avail(enum parse_events__term_type term_typ= e, struct parse_events_er case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: @@ -898,6 +902,10 @@ do { \ CHECK_TYPE_VAL(NUM); attr->config3 =3D term->val.num; break; + case PARSE_EVENTS__TERM_TYPE_CONFIG4: + CHECK_TYPE_VAL(NUM); + attr->config4 =3D term->val.num; + break; case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: CHECK_TYPE_VAL(NUM); break; @@ -1097,6 +1105,7 @@ static int config_term_tracepoint(struct perf_event_a= ttr *attr, case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: case PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ: @@ -1237,6 +1246,7 @@ do { \ case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_METRIC_ID: case PARSE_EVENTS__TERM_TYPE_RAW: @@ -1274,6 +1284,7 @@ static int get_config_chgs(struct perf_pmu *pmu, stru= ct parse_events_terms *head case PARSE_EVENTS__TERM_TYPE_CONFIG1: case PARSE_EVENTS__TERM_TYPE_CONFIG2: case PARSE_EVENTS__TERM_TYPE_CONFIG3: + case PARSE_EVENTS__TERM_TYPE_CONFIG4: case PARSE_EVENTS__TERM_TYPE_NAME: case PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD: case PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ: diff --git a/tools/perf/util/parse-events.h b/tools/perf/util/parse-events.h index e176a34ab088..6e90c26066d4 100644 --- a/tools/perf/util/parse-events.h +++ b/tools/perf/util/parse-events.h @@ -58,6 +58,7 @@ enum parse_events__term_type { PARSE_EVENTS__TERM_TYPE_CONFIG1, PARSE_EVENTS__TERM_TYPE_CONFIG2, PARSE_EVENTS__TERM_TYPE_CONFIG3, + PARSE_EVENTS__TERM_TYPE_CONFIG4, PARSE_EVENTS__TERM_TYPE_NAME, PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD, PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ, diff --git a/tools/perf/util/parse-events.l b/tools/perf/util/parse-events.l index 7ed86e3e34e3..8e2986d55bc4 100644 --- a/tools/perf/util/parse-events.l +++ b/tools/perf/util/parse-events.l @@ -317,6 +317,7 @@ config { return term(yyscanner, PARSE_EVENTS__TERM_TY= PE_CONFIG); } config1 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG1); } config2 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG2); } config3 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG3); } +config4 { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_CONFIG4); } name { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_NAME); } period { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_SAMPLE_PERIOD); } freq { return term(yyscanner, PARSE_EVENTS__TERM_TYPE_SAMPLE_FREQ); } diff --git a/tools/perf/util/pmu.c b/tools/perf/util/pmu.c index b7ebac5ab1d1..fc50df65d540 100644 --- a/tools/perf/util/pmu.c +++ b/tools/perf/util/pmu.c @@ -1427,6 +1427,10 @@ static int pmu_config_term(const struct perf_pmu *pm= u, assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); pmu_format_value(bits, term->val.num, &attr->config3, zero); break; + case PARSE_EVENTS__TERM_TYPE_CONFIG4: + assert(term->type_val =3D=3D PARSE_EVENTS__TERM_TYPE_NUM); + pmu_format_value(bits, term->val.num, &attr->config4, zero); + break; case PARSE_EVENTS__TERM_TYPE_USER: /* Not hardcoded. */ return -EINVAL; case PARSE_EVENTS__TERM_TYPE_NAME ... PARSE_EVENTS__TERM_TYPE_HARDWARE: @@ -1474,6 +1478,9 @@ static int pmu_config_term(const struct perf_pmu *pmu, case PERF_PMU_FORMAT_VALUE_CONFIG3: vp =3D &attr->config3; break; + case PERF_PMU_FORMAT_VALUE_CONFIG4: + vp =3D &attr->config4; + break; default: return -EINVAL; } @@ -1787,6 +1794,7 @@ int perf_pmu__for_each_format(struct perf_pmu *pmu, v= oid *state, pmu_format_call "config1=3D0..0xffffffffffffffff", "config2=3D0..0xffffffffffffffff", "config3=3D0..0xffffffffffffffff", + "config4=3D0..0xffffffffffffffff", "name=3Dstring", "period=3Dnumber", "freq=3Dnumber", diff --git a/tools/perf/util/pmu.h b/tools/perf/util/pmu.h index b93014cc3670..1ce5377935db 100644 --- a/tools/perf/util/pmu.h +++ b/tools/perf/util/pmu.h @@ -22,6 +22,7 @@ enum { PERF_PMU_FORMAT_VALUE_CONFIG1, PERF_PMU_FORMAT_VALUE_CONFIG2, PERF_PMU_FORMAT_VALUE_CONFIG3, + PERF_PMU_FORMAT_VALUE_CONFIG4, PERF_PMU_FORMAT_VALUE_CONFIG_END, }; =20 --=20 2.34.1 From nobody Tue Dec 16 14:37:42 2025 Received: from mail-wm1-f65.google.com (mail-wm1-f65.google.com [209.85.128.65]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2586C290D8F for ; Thu, 29 May 2025 11:33:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.128.65 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518408; cv=none; b=jyLi5uKe5HfsHTrCdgl77OrlDHJwYeQgfkZCfE7PH1ll5gpq8rfDVWt1m2RrebRjrZtlr6w1LQ1isU7sHOiwumSBfjPy7T0mY8tqva4fo8KhLapLpVlZhypmuCxjbHre21IGsVxM7LdL5ah7RtfM149M6SXhtkwz4iDGGhVVa10= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748518408; c=relaxed/simple; bh=E1yjj826OV2i042EqOElXmFPrF8pEcz4phQ8lctqMVU=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=fwMo3CmHOtv8etGyPiXt+Z4yRWMhEr7LmFosMdlBDe4MQIF3bxN345W21PpuoOFvtnWkhBU+0zXAWhY7GGEl/EM4Kgfr2EK0wht16vsJVBHBTkmrnLGEF6BzwZVc2OynaMkESKDzztz/KwJEkX0Dcvve/nSWwFexSU/OvaX/fDE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=fc/RZXSL; arc=none smtp.client-ip=209.85.128.65 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="fc/RZXSL" Received: by mail-wm1-f65.google.com with SMTP id 5b1f17b1804b1-441c99459e9so5695095e9.3 for ; Thu, 29 May 2025 04:33:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1748518404; x=1749123204; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=TxG8SPa3uepeFqsoLKl29LMbTYOpGZ70IvRiGVenFk8=; b=fc/RZXSL81pqAVuRokshOxMxcYWZPGbMkL3muIio9Dvd6yqD3m5YvT8YjprFDKmJCI oD9+co81lsqxx7AkJiZOZuvn42vzDjtB5XDbebiIkjCZBpXGyVrn3e1J4hoSzEXd7CV6 xfkZMPoNdkbtUxSRvq5BH7vbqOJhK2fTCoprUFj6HOg++WTFA8KVT7OcQE3Me7S0ma08 ivpTRaWhP0ImFUQ/bydvrGAONHsoCt8fgduU4mGHggP3vw5hxwm+VX/HUrN/s18qPQoy z80cJw8lY50SFe1i5pNgjhwONJ4C4m5HBEwFiJoo0FUoJjz/eY9HsWne2zJJeQgus3/+ 25Mg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1748518404; x=1749123204; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=TxG8SPa3uepeFqsoLKl29LMbTYOpGZ70IvRiGVenFk8=; b=iMjZnV9FzGRG5Gr/ly0crO1BaXJMjtf0cjazYVF7SMqgk0tuUJ/hhTUc8te436/2k2 +1GD8F4O8M4qr5b11CvU/dtq/lzhkySRcxL5jhKSqShbhJN+ESVbhSceRzrKitvaAj00 fYiek6ORSzb7sC4NByHC4+4KarjfJqOAFbkhRyWIlkDEIwuXkjDwMguxBHfDCVfgZMAs ciAojB+fotpnbjWMJv1pQQsHCDFrlsSChk0Puwsn0c6uvdrqw+7j2CizJ5xt+fTD8YJW ICBlZ1bEBjiKfYg6UN0ySuwFkYE/MpLlGkP4TvgbQkjZ6pYWVVliYWmzOjQbNwIdH44S JCYg== X-Forwarded-Encrypted: i=1; AJvYcCWbzCxl34vb/jR+FqXqq+oGlgDPp/1vrko5xKWj7mRrnfW6FeczVoHV3RXNMQxJX2wUqybMYhxvCS6nnsw=@vger.kernel.org X-Gm-Message-State: AOJu0YxaxHrmaO/J+mXCQvBXvrD7abi7WHWQL6hCrHZUe6PqJC/tFwiE /Ip9F+XJiJv0+WM1mHmhUbGzJXRijTj48pqO5+T2DGYJeTTZq+xn+sc84/3R6VBCKOM= X-Gm-Gg: ASbGnctwdbqWs+JQKSzJ7wD+l/C3mJ3b6Pf6MQzisI9xbfUuDPQZBjaEJFXLPj/JkTa eiohlXY+cqhz3oQ//yJW73vmgLGUnuPzK3c/gDRnYLNjZ8Z+Nm5IxIBYke/OLDbCURYIhBkzTsi e7Ls6JaWo+d81QBLYBsSCfOtuoKhSpJGUnIokiM9/7gOC7uvbN0DdOz4Qoo9WrJY1b/T0Drw8fk c6I89HKn26xvsQUK70/tvmCzvXqgNMsS0qvteXYPeBo511LHGRK0R64ZU0N3NA6phPcALHVehrK heQSA2v6l+Sod1xejl8VboZOsHNFKWGszlHj4vy6gAVhNjHuCg2oJ+3OJ/PW X-Google-Smtp-Source: AGHT+IFa3tbBIinQlu5QLSXdztzNSxtKZbpAOFxf4JVhGWyoTyRCcEYjmPGyAmzQyVI8/KRfEZZhCw== X-Received: by 2002:a05:600c:6749:b0:44b:eb56:1d48 with SMTP id 5b1f17b1804b1-45072545a0fmr59959615e9.4.1748518404390; Thu, 29 May 2025 04:33:24 -0700 (PDT) Received: from ho-tower-lan.lan ([37.18.136.128]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-450cfc3785bsm17443945e9.40.2025.05.29.04.33.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 May 2025 04:33:23 -0700 (PDT) From: James Clark Date: Thu, 29 May 2025 12:30:32 +0100 Subject: [PATCH v2 11/11] perf docs: arm-spe: Document new SPE filtering features Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250529-james-perf-feat_spe_eft-v2-11-a01a9baad06a@linaro.org> References: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> In-Reply-To: <20250529-james-perf-feat_spe_eft-v2-0-a01a9baad06a@linaro.org> To: Catalin Marinas , Will Deacon , Mark Rutland , Jonathan Corbet , Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter Cc: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, kvmarm@lists.linux.dev, James Clark X-Mailer: b4 0.14.0 FEAT_SPE_EFT and FEAT_SPE_FDS etc have new user facing format attributes so document them. Also document existing 'event_filter' bits that were missing from the doc and the fact that latency values are stored in the weight field. Signed-off-by: James Clark Reviewed-by: Leo Yan Tested-by: Leo Yan --- tools/perf/Documentation/perf-arm-spe.txt | 97 +++++++++++++++++++++++++++= +--- 1 file changed, 88 insertions(+), 9 deletions(-) diff --git a/tools/perf/Documentation/perf-arm-spe.txt b/tools/perf/Documen= tation/perf-arm-spe.txt index 37afade4f1b2..4092b53b58d2 100644 --- a/tools/perf/Documentation/perf-arm-spe.txt +++ b/tools/perf/Documentation/perf-arm-spe.txt @@ -141,27 +141,65 @@ Config parameters These are placed between the // in the event and comma separated. For exam= ple '-e arm_spe/load_filter=3D1,min_latency=3D10/' =20 - branch_filter=3D1 - collect branches only (PMSFCR.B) - event_filter=3D - filter on specific events (PMSEVFR) - see bitfie= ld description below + event_filter=3D - logical AND filter on specific events (PMSEVFR) = - see bitfield description below + inv_event_filter=3D - logical OR to filter out specific events (PM= SNEVFR, FEAT_SPEv1p2) - see bitfield description below jitter=3D1 - use jitter to avoid resonance when sampling (PMS= IRR.RND) - load_filter=3D1 - collect loads only (PMSFCR.LD) min_latency=3D - collect only samples with this latency or higher= * (PMSLATFR) pa_enable=3D1 - collect physical address (as well as VA) of load= s/stores (PMSCR.PA) - requires privilege pct_enable=3D1 - collect physical timestamp instead of virtual ti= mestamp (PMSCR.PCT) - requires privilege - store_filter=3D1 - collect stores only (PMSFCR.ST) ts_enable=3D1 - enable timestamping with value of generic timer = (PMSCR.TS) discard=3D1 - enable SPE PMU events but don't collect sample d= ata - see 'Discard mode' (PMBLIMITR.FM =3D DISCARD) + data_src_filter=3D - mask to filter from 0-63 possible data source= s (PMSDSFR, FEAT_SPE_FDS) - See 'Data source filtering' =20 +++*+++ Latency is the total latency from the point at which sampling star= ted on that instruction, rather than only the execution latency. =20 -Only some events can be filtered on; these include: - - bit 1 - instruction retired (i.e. omit speculative instructions) +Only some events can be filtered on using 'event_filter' bits. The overall +filter is the logical AND of these bits, for example if bits 3 and 5 are s= et +only samples that have both 'L1D cache refill' AND 'TLB walk' are recorded= . When +FEAT_SPEv1p2 is implemented 'inv_event_filter' can also be used to exclude +events that have any (OR) of the filter's bits set. For example setting bi= ts 3 +and 5 in 'inv_event_filter' will exclude any events that are either L1D ca= che +refill OR TLB walk. If the same bit is set in both filters it's UNPREDICTA= BLE +whether the sample is included or excluded. Filter bits for both event_fil= ter +and inv_event_filter are: + + bit 1 - Instruction retired (i.e. omit speculative instructions) + bit 2 - L1D access (FEAT_SPEv1p4) bit 3 - L1D refill + bit 4 - TLB access (FEAT_SPEv1p4) bit 5 - TLB refill - bit 7 - mispredict - bit 11 - misaligned access + bit 6 - Not taken event (FEAT_SPEv1p2) + bit 7 - Mispredict + bit 8 - Last level cache access (FEAT_SPEv1p4) + bit 9 - Last level cache miss (FEAT_SPEv1p4) + bit 10 - Remote access (FEAT_SPEv1p4) + bit 11 - Misaligned access (FEAT_SPEv1p1) + bit 12-15 - IMPLEMENTATION DEFINED events (when implemented) + bit 16 - Transaction (FEAT_TME) + bit 17 - Partial or empty SME or SVE predicate (FEAT_SPEv1p1) + bit 18 - Empty SME or SVE predicate (FEAT_SPEv1p1) + bit 19 - L2D access (FEAT_SPEv1p4) + bit 20 - L2D miss (FEAT_SPEv1p4) + bit 21 - Cache data modified (FEAT_SPEv1p4) + bit 22 - Recently fetched (FEAT_SPEv1p4) + bit 23 - Data snooped (FEAT_SPEv1p4) + bit 24 - Streaming SVE mode event (when FEAT_SPE_SME is implemented),= or + IMPLEMENTATION DEFINED event 24 (when implemented, only vers= ions + less than FEAT_SPEv1p4) + bit 25 - SMCU or external coprocessor operation event when FEAT_SPE_S= ME is + implemented, or IMPLEMENTATION DEFINED event 25 (when implem= ented, + only versions less than FEAT_SPEv1p4) + bit 26-31 - IMPLEMENTATION DEFINED events (only versions less than FEAT_= SPEv1p4) + bit 48-63 - IMPLEMENTATION DEFINED events (when implemented) + +For IMPLEMENTATION DEFINED bits, refer to the CPU TRM if these bits are +implemented. + +The driver will reject events if requested filter bits require unimplement= ed SPE +versions, but will not reject filter bits for unimplemented IMPDEF bits or= when +their related feature is not present (e.g. SME). For example, if FEAT_SPEv= 1p2 is +not implemented, filtering on "Not taken event" (bit 6) will be rejected. =20 So to sample just retired instructions: =20 @@ -171,6 +209,31 @@ or just mispredicted branches: =20 perf record -e arm_spe/event_filter=3D0x80/ -- ./mybench =20 +When set, the following filters can be used to select samples that match a= ny of +the operation types (OR filtering). If only one is set then only samples o= f that +type are collected: + + branch_filter=3D1 - Collect branches (PMSFCR.B) + load_filter=3D1 - Collect loads (PMSFCR.LD) + store_filter=3D1 - Collect stores (PMSFCR.ST) + +When extended filtering is supported (FEAT_SPE_EFT), SIMD and float +pointer operations can also be selected: + + simd_filter=3D1 - Collect SIMD loads, stores and operations (PMS= FCR.SIMD) + float_filter=3D1 - Collect floating point loads, stores and opera= tions (PMSFCR.FP) + +When extended filtering is supported (FEAT_SPE_EFT), operation type filter= s can +be changed to AND using _mask fields. For example samples could be selecte= d if +they are store AND SIMD by setting 'store_filter=3D1,simd_filter=3D1, +store_filter_mask=3D1,simd_filter_mask=3D1'. The new masks are as follows: + + branch_filter_mask=3D1 - Change branch filter behavior from OR to AND (= PMSFCR.Bm) + load_filter_mask=3D1 - Change load filter behavior from OR to AND (PM= SFCR.LDm) + store_filter_mask=3D1 - Change store filter behavior from OR to AND (P= MSFCR.STm) + simd_filter_mask=3D1 - Change SIMD filter behavior from OR to AND (PM= SFCR.SIMDm) + float_filter_mask=3D1 - Change floating point filter behavior from OR = to AND (PMSFCR.FPm) + Viewing the data ~~~~~~~~~~~~~~~~~ =20 @@ -204,6 +267,10 @@ Memory access details are also stored on the samples a= nd this can be viewed with =20 perf report --mem-mode =20 +The latency value from the SPE sample is stored in the 'weight' field of t= he +Perf samples and can be displayed in Perf script and report outputs by ena= bling +its display from the command line. + Common errors ~~~~~~~~~~~~~ =20 @@ -247,6 +314,18 @@ to minimize output. Then run perf stat: perf record -e arm_spe/discard/ -a -N -B --no-bpf-event -o - > /dev/null= & perf stat -e SAMPLE_FEED_LD =20 +Data source filtering +~~~~~~~~~~~~~~~~~~~~~ + +When FEAT_SPE_FDS is present, 'data_src_filter' can be used as a mask to f= ilter +on a subset (0 - 63) of possible data source IDs. The full range of data s= ources +is 0 - 65535 although these are unlikely to be used in practice. Data sour= ces +are IMPDEF so refer to the TRM for the mappings. Each bit N of the filter = maps +to data source N. The filter is an OR of all the bits, so for example sett= ing +bits 0 and 3 includes only packets from data sources 0 OR 3. When +'data_src_filter' is set to 0 data source filtering is disabled and all da= ta +sources are included. + SEE ALSO -------- =20 --=20 2.34.1