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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506cd3506sm1403445ad.156.2025.05.28.16.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:50:30 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v4 2/5] thermal: qcom-spmi-temp-alarm: Add temp alarm data struct based on HW subtype Date: Wed, 28 May 2025 16:50:23 -0700 Message-Id: <20250528235026.4171109-3-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> References: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=OslPyz/t c=1 sm=1 tr=0 ts=6837a148 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=YOepGyM1JLL-9Drl-x0A:9 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 9Z6deOX91hS6qo9q_Tq6nGHUYH20p6wG X-Proofpoint-GUID: 9Z6deOX91hS6qo9q_Tq6nGHUYH20p6wG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDIxMCBTYWx0ZWRfX7Dg3BDwNOe2s /Ws7XIM/m6kIRk29AeGNSaIMgthZwZxKaqdtXOcJJuSFcVUDOLYuUQIVYlSulcrnwweMh9ierDS wohpU5Huh6BRulm5cDmKLHkLMGk/HNLzRckm7JMFZWaeT8THcG8ArQ3MBffut64sTlIBstDYf74 KpcIQ5HwNZU41BbHiOzidBiLKK7aKpoIUh4FtsLBiVdbhw4Cwne+UCJENF/oICCXyvQDKo3IYJR pSzyOIsj1g8JYa7F9NsH4fladtYLGbWVfG23mZ2bjJI5EOStPcoF0dnXxjeKBGg/NB52f2qMMR4 G8YCabPrRagEUd7zpqSpKwgY2GTloo1Naso1H+KhcoKQ0eoET7UxBMmX5Ffykh6TLDbbz/o0snp WJ96rM+9JtQ1aKfroZQWoM98hZxnSe1j4/DdT3JtPRrWlWkpvaIufhp1VroEtll8XW4chKHa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_11,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505280210 Content-Type: text/plain; charset="utf-8" Currently multiple if/else statements are used in functions to decipher between SPMI temp alarm Gen 1, Gen 2 and Gen 2 Rev 1 functionality. Instead refactor the driver so that SPMI temp alarm chips will have reference to a spmi_temp_alarm_data struct which defines data and function callbacks based on the HW subtype. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 106 +++++++++++++------- 1 file changed, 69 insertions(+), 37 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 47248a843591..0d8bbc5b7af6 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -4,6 +4,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include #include #include #include @@ -31,7 +32,6 @@ =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) -#define STATUS_GEN2_STATE_SHIFT 4 =20 #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -68,10 +68,18 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_= COUNT] =3D { /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 +struct qpnp_tm_chip; + +struct spmi_temp_alarm_data { + const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*get_temp_stage)(struct qpnp_tm_chip *chip); +}; + struct qpnp_tm_chip { struct regmap *map; struct device *dev; struct thermal_zone_device *tz_dev; + const struct spmi_temp_alarm_data *data; unsigned int subtype; long temp; unsigned int thresh; @@ -81,9 +89,9 @@ struct qpnp_tm_chip { struct mutex lock; bool initialized; bool require_s2_shutdown; + long temp_thresh_map[STAGE_COUNT]; =20 struct iio_channel *adc; - const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; }; =20 /* This array maps from GEN2 alarm state to GEN1 alarm stage */ @@ -117,20 +125,19 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u= 16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int st= age) { - if (!chip->temp_map || chip->thresh >=3D THRESH_COUNT || stage =3D=3D 0 || - stage > STAGE_COUNT) + if (stage =3D=3D 0 || stage > STAGE_COUNT) return 0; =20 - return (*chip->temp_map)[chip->thresh][stage - 1]; + return chip->temp_thresh_map[stage - 1]; } =20 /** - * qpnp_tm_get_temp_stage() - return over-temperature stage + * qpnp_tm_gen1_get_temp_stage() - return over-temperature stage * @chip: Pointer to the qpnp_tm chip * - * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. + * Return: stage on success, or errno on failure. */ -static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) +static int qpnp_tm_gen1_get_temp_stage(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; @@ -139,12 +146,27 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) if (ret < 0) return ret; =20 - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) - ret =3D reg & STATUS_GEN1_STAGE_MASK; - else - ret =3D (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; + return FIELD_GET(STATUS_GEN1_STAGE_MASK, reg); +} =20 - return ret; +/** + * qpnp_tm_gen2_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: stage on success, or errno on failure. + */ +static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + ret =3D FIELD_GET(STATUS_GEN2_STATE_MASK, reg); + + return alarm_state_map[ret]; } =20 /* @@ -153,23 +175,16 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) */ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) { - unsigned int stage, stage_new, stage_old; + unsigned int stage_new, stage_old; int ret; =20 WARN_ON(!mutex_is_locked(&chip->lock)); =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) return ret; - stage =3D ret; - - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) { - stage_new =3D stage; - stage_old =3D chip->stage; - } else { - stage_new =3D alarm_state_map[stage]; - stage_old =3D alarm_state_map[chip->stage]; - } + stage_new =3D ret; + stage_old =3D chip->stage; =20 if (stage_new > stage_old) { /* increasing stage, use lower bound */ @@ -181,7 +196,7 @@ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_ch= ip *chip) - TEMP_STAGE_HYSTERESIS; } =20 - chip->stage =3D stage; + chip->stage =3D stage_new; =20 return 0; } @@ -221,8 +236,8 @@ static int qpnp_tm_get_temp(struct thermal_zone_device = *tz, int *temp) static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { - long stage2_threshold_min =3D (*chip->temp_map)[THRESH_MIN][1]; - long stage2_threshold_max =3D (*chip->temp_map)[THRESH_MAX][1]; + long stage2_threshold_min =3D (*chip->data->temp_map)[THRESH_MIN][1]; + long stage2_threshold_max =3D (*chip->data->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown =3D false; u8 reg; =20 @@ -257,6 +272,8 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, } =20 skip: + memcpy(chip->temp_thresh_map, chip->data->temp_map[chip->thresh], + sizeof(chip->temp_thresh_map)); reg |=3D chip->thresh; if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; @@ -294,6 +311,21 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .temp_map =3D &temp_map_gen2_v1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -301,7 +333,6 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) */ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { - unsigned int stage; int ret; u8 reg =3D 0; int crit_temp; @@ -315,16 +346,13 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) chip->thresh =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; chip->temp =3D DEFAULT_TEMP; =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) goto out; chip->stage =3D ret; =20 - stage =3D chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1 - ? chip->stage : alarm_state_map[chip->stage]; - - if (stage) - chip->temp =3D qpnp_tm_decode_temp(chip, stage); + if (chip->stage) + chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 mutex_unlock(&chip->lock); =20 @@ -419,10 +447,14 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 chip->subtype =3D subtype; - if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) - chip->temp_map =3D &temp_map_gen2_v1; + if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) + chip->data =3D &spmi_temp_alarm_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) + chip->data =3D &spmi_temp_alarm_gen2_rev1_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) + chip->data =3D &spmi_temp_alarm_gen2_data; else - chip->temp_map =3D &temp_map_gen1; + return -ENODEV; =20 if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) { dig_revision =3D (dig_major << 8) | dig_minor; --=20 2.34.1