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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506cd3506sm1403445ad.156.2025.05.28.16.50.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:50:29 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v4 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Wed, 28 May 2025 16:50:22 -0700 Message-Id: <20250528235026.4171109-2-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> References: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: e2FZ8WgoK3Wp1vgA3FFHEp6IqdWdGCmy X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDIxMCBTYWx0ZWRfXxS3gH2Xhmmtx hH4U2d0iprr69SvvxpBXuUjRbTazWrjXkRRha8umsUhs4VnM4pDNWWHp0CQuZEomxXsNsBb33ko 9bV67Cat1qwQDPVhU6Y0PIp2bck9PJ+6vHXWBHbs91CJIuf0TiX84mWcfXEAE+nH3ctpyj8T02c guPpt7GLQO6UhSWj3/tpeo6E6+IHNkqgUAYjvs4OMhf0XqxfjWnQw2MJ6w6KVFk4M1cfccZMs+E T2uqOPq2qmnuUm3aww71vhrqDjMErlG+wYGqDBlAcklOBaa7kivpdBG9LMy5B1X9CQ+mznieuZp dg5dlaXNhTE7rk3c9LSOFqEj2GF5+VCFy/MlJ7u8Q/MdKmT63OiTe5ykGiuRzNN7gRaf9kPlB8h aE0wd20p+NHMzmdsNxK762l6yJj6+R8fTdVIiameZEA4ub0IYxzJaakcGZTsIuGjTUCtMviV X-Authority-Analysis: v=2.4 cv=fMk53Yae c=1 sm=1 tr=0 ts=6837a147 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=e8SBnR8fKgZMydxn7aMA:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-ORIG-GUID: e2FZ8WgoK3Wp1vgA3FFHEp6IqdWdGCmy X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_11,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 malwarescore=0 adultscore=0 impostorscore=0 phishscore=0 suspectscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 clxscore=1015 mlxscore=0 mlxlogscore=999 bulkscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505280210 Content-Type: text/plain; charset="utf-8" From: David Collins Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 29 insertions(+), 3 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index a81e7d6e865f..47248a843591 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights r= eserved. + * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 #include @@ -16,6 +17,7 @@ =20 #include "../thermal_hwmon.h" =20 +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -78,6 +80,7 @@ struct qpnp_tm_chip { /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; + bool require_s2_shutdown; =20 struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; @@ -255,7 +258,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, =20 skip: reg |=3D chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; =20 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -350,8 +353,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; struct device_node *node; - u8 type, subtype, dig_major; - u32 res; + u8 type, subtype, dig_major, dig_minor; + u32 res, dig_revision; int ret, irq; =20 node =3D pdev->dev.of_node; @@ -402,6 +405,12 @@ static int qpnp_tm_probe(struct platform_device *pdev) return dev_err_probe(&pdev->dev, ret, "could not read dig_major\n"); =20 + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_DIG_MINOR, &dig_minor); + if (ret < 0) { + dev_err(&pdev->dev, "could not read dig_minor\n"); + return ret; + } + if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", @@ -415,6 +424,23 @@ static int qpnp_tm_probe(struct platform_device *pdev) else chip->temp_map =3D &temp_map_gen1; =20 + if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) { + dig_revision =3D (dig_major << 8) | dig_minor; + /* + * Check if stage 2 automatic partial shutdown must remain + * enabled to avoid potential repeated faults upon reaching + * over-temperature stage 3. + */ + switch (dig_revision) { + case 0x0001: + case 0x0002: + case 0x0100: + case 0x0101: + chip->require_s2_shutdown =3D true; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506cd3506sm1403445ad.156.2025.05.28.16.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:50:30 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v4 2/5] thermal: qcom-spmi-temp-alarm: Add temp alarm data struct based on HW subtype Date: Wed, 28 May 2025 16:50:23 -0700 Message-Id: <20250528235026.4171109-3-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> References: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=OslPyz/t c=1 sm=1 tr=0 ts=6837a148 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=YOepGyM1JLL-9Drl-x0A:9 a=1OuFwYUASf3TG4hYMiVC:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-ORIG-GUID: 9Z6deOX91hS6qo9q_Tq6nGHUYH20p6wG X-Proofpoint-GUID: 9Z6deOX91hS6qo9q_Tq6nGHUYH20p6wG X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDIxMCBTYWx0ZWRfX7Dg3BDwNOe2s /Ws7XIM/m6kIRk29AeGNSaIMgthZwZxKaqdtXOcJJuSFcVUDOLYuUQIVYlSulcrnwweMh9ierDS wohpU5Huh6BRulm5cDmKLHkLMGk/HNLzRckm7JMFZWaeT8THcG8ArQ3MBffut64sTlIBstDYf74 KpcIQ5HwNZU41BbHiOzidBiLKK7aKpoIUh4FtsLBiVdbhw4Cwne+UCJENF/oICCXyvQDKo3IYJR pSzyOIsj1g8JYa7F9NsH4fladtYLGbWVfG23mZ2bjJI5EOStPcoF0dnXxjeKBGg/NB52f2qMMR4 G8YCabPrRagEUd7zpqSpKwgY2GTloo1Naso1H+KhcoKQ0eoET7UxBMmX5Ffykh6TLDbbz/o0snp WJ96rM+9JtQ1aKfroZQWoM98hZxnSe1j4/DdT3JtPRrWlWkpvaIufhp1VroEtll8XW4chKHa X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_11,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505280210 Content-Type: text/plain; charset="utf-8" Currently multiple if/else statements are used in functions to decipher between SPMI temp alarm Gen 1, Gen 2 and Gen 2 Rev 1 functionality. Instead refactor the driver so that SPMI temp alarm chips will have reference to a spmi_temp_alarm_data struct which defines data and function callbacks based on the HW subtype. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 106 +++++++++++++------- 1 file changed, 69 insertions(+), 37 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 47248a843591..0d8bbc5b7af6 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -4,6 +4,7 @@ * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. */ =20 +#include #include #include #include @@ -31,7 +32,6 @@ =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) -#define STATUS_GEN2_STATE_SHIFT 4 =20 #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -68,10 +68,18 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_= COUNT] =3D { /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 +struct qpnp_tm_chip; + +struct spmi_temp_alarm_data { + const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*get_temp_stage)(struct qpnp_tm_chip *chip); +}; + struct qpnp_tm_chip { struct regmap *map; struct device *dev; struct thermal_zone_device *tz_dev; + const struct spmi_temp_alarm_data *data; unsigned int subtype; long temp; unsigned int thresh; @@ -81,9 +89,9 @@ struct qpnp_tm_chip { struct mutex lock; bool initialized; bool require_s2_shutdown; + long temp_thresh_map[STAGE_COUNT]; =20 struct iio_channel *adc; - const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; }; =20 /* This array maps from GEN2 alarm state to GEN1 alarm stage */ @@ -117,20 +125,19 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u= 16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int st= age) { - if (!chip->temp_map || chip->thresh >=3D THRESH_COUNT || stage =3D=3D 0 || - stage > STAGE_COUNT) + if (stage =3D=3D 0 || stage > STAGE_COUNT) return 0; =20 - return (*chip->temp_map)[chip->thresh][stage - 1]; + return chip->temp_thresh_map[stage - 1]; } =20 /** - * qpnp_tm_get_temp_stage() - return over-temperature stage + * qpnp_tm_gen1_get_temp_stage() - return over-temperature stage * @chip: Pointer to the qpnp_tm chip * - * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. + * Return: stage on success, or errno on failure. */ -static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) +static int qpnp_tm_gen1_get_temp_stage(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; @@ -139,12 +146,27 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) if (ret < 0) return ret; =20 - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) - ret =3D reg & STATUS_GEN1_STAGE_MASK; - else - ret =3D (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; + return FIELD_GET(STATUS_GEN1_STAGE_MASK, reg); +} =20 - return ret; +/** + * qpnp_tm_gen2_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: stage on success, or errno on failure. + */ +static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + ret =3D FIELD_GET(STATUS_GEN2_STATE_MASK, reg); + + return alarm_state_map[ret]; } =20 /* @@ -153,23 +175,16 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) */ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) { - unsigned int stage, stage_new, stage_old; + unsigned int stage_new, stage_old; int ret; =20 WARN_ON(!mutex_is_locked(&chip->lock)); =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) return ret; - stage =3D ret; - - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) { - stage_new =3D stage; - stage_old =3D chip->stage; - } else { - stage_new =3D alarm_state_map[stage]; - stage_old =3D alarm_state_map[chip->stage]; - } + stage_new =3D ret; + stage_old =3D chip->stage; =20 if (stage_new > stage_old) { /* increasing stage, use lower bound */ @@ -181,7 +196,7 @@ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_ch= ip *chip) - TEMP_STAGE_HYSTERESIS; } =20 - chip->stage =3D stage; + chip->stage =3D stage_new; =20 return 0; } @@ -221,8 +236,8 @@ static int qpnp_tm_get_temp(struct thermal_zone_device = *tz, int *temp) static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { - long stage2_threshold_min =3D (*chip->temp_map)[THRESH_MIN][1]; - long stage2_threshold_max =3D (*chip->temp_map)[THRESH_MAX][1]; + long stage2_threshold_min =3D (*chip->data->temp_map)[THRESH_MIN][1]; + long stage2_threshold_max =3D (*chip->data->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown =3D false; u8 reg; =20 @@ -257,6 +272,8 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, } =20 skip: + memcpy(chip->temp_thresh_map, chip->data->temp_map[chip->thresh], + sizeof(chip->temp_thresh_map)); reg |=3D chip->thresh; if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; @@ -294,6 +311,21 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .temp_map =3D &temp_map_gen2_v1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -301,7 +333,6 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) */ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { - unsigned int stage; int ret; u8 reg =3D 0; int crit_temp; @@ -315,16 +346,13 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) chip->thresh =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; chip->temp =3D DEFAULT_TEMP; =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) goto out; chip->stage =3D ret; =20 - stage =3D chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1 - ? chip->stage : alarm_state_map[chip->stage]; - - if (stage) - chip->temp =3D qpnp_tm_decode_temp(chip, stage); + if (chip->stage) + chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 mutex_unlock(&chip->lock); =20 @@ -419,10 +447,14 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 chip->subtype =3D subtype; - if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) - chip->temp_map =3D &temp_map_gen2_v1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506cd3506sm1403445ad.156.2025.05.28.16.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:50:32 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v4 3/5] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Date: Wed, 28 May 2025 16:50:24 -0700 Message-Id: <20250528235026.4171109-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> References: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=OslPyz/t c=1 sm=1 tr=0 ts=6837a14a cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=QmBY4OO-GzUMAyIBBcsA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-ORIG-GUID: SoAccFNHbwtub33O93b3byopdee_pynI X-Proofpoint-GUID: SoAccFNHbwtub33O93b3byopdee_pynI X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDIxMCBTYWx0ZWRfX6h3aT1j2BiK6 97uIrqrKvYvNvmoK4URIqmWZm5NRbZQMZjxWqrXLwfyKr0XMtehPVJeSgcuKST6DraderFkgNeU KFRGkCtahY042MUyty56cAOf7DsAT5KluYU2B7BO4hJFQimWtqSzoiqNpqST0TDYVsMpsEYCG8Q RxtyrW6EVzsSR6mCEazF6fc8bfIeiTME0CEt+EX3XFka6dC43SnsdvTMfqHuk6uz1UYs1rYTmlG 0jb+i0sYxhe6tckLsi5ahjclEpyDPNY9nYGV/esn1I6huWjDCxnL6T8N6oyBDB21q4EX3zDquLm yWcVePjMrsccXnoS/q06RT9HJYMFO82cgndw5VCxUTkFZu4F/TQjmg4JG2jeECc39m5EgR/MNLU 1ImjLCOLzaM9/TSkHIzJnY+GlvPtnl7hWL/yKSOFQkl0DM5laRw4vk4ZYTuBeztbn5wrGLKe X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_11,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 mlxlogscore=999 adultscore=0 malwarescore=0 bulkscore=0 priorityscore=1501 clxscore=1015 mlxscore=0 lowpriorityscore=0 spamscore=0 suspectscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505280210 Content-Type: text/plain; charset="utf-8" In preparation to support newer temp alarm subtypes, add the "ops" and "configure_trip_temps" references to spmi_temp_alarm_data. This will allow for each Temp Alarm subtype to define its own thermal_zone_device_ops and properly configure thermal trip temperature. Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 36 +++++++++++++++------ 1 file changed, 27 insertions(+), 9 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 0d8bbc5b7af6..59a25f02a278 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -71,8 +71,10 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { struct qpnp_tm_chip; =20 struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; =20 struct qpnp_tm_chip { @@ -311,18 +313,39 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp =3D THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); + mutex_unlock(&chip->lock); + + return ret; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen2_v1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 @@ -335,7 +358,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; - int crit_temp; =20 mutex_lock(&chip->lock); =20 @@ -356,16 +378,12 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) =20 mutex_unlock(&chip->lock); =20 - ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp =3D THERMAL_TEMP_INVALID; + ret =3D chip->data->configure_trip_temps(chip); + if (ret < 0) + return ret; =20 mutex_lock(&chip->lock); =20 - ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); - if (ret < 0) - goto out; - /* Enable the thermal alarm PMIC module in always-on mode. */ reg =3D ALARM_CTRL_FORCE_ENABLE; ret =3D qpnp_tm_write(chip, QPNP_TM_REG_ALARM_CTRL, reg); @@ -479,7 +497,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) * before the hardware initialization is completed. */ chip->tz_dev =3D devm_thermal_of_zone_register( - &pdev->dev, 0, chip, &qpnp_tm_sensor_ops); + &pdev->dev, 0, chip, chip->data->ops); if (IS_ERR(chip->tz_dev)) return dev_err_probe(&pdev->dev, PTR_ERR(chip->tz_dev), "failed to register sensor\n"); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506cd3506sm1403445ad.156.2025.05.28.16.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:50:33 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v4 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Wed, 28 May 2025 16:50:25 -0700 Message-Id: <20250528235026.4171109-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> References: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=WfoMa1hX c=1 sm=1 tr=0 ts=6837a14b cx=c_pps a=Oh5Dbbf/trHjhBongsHeRQ==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=4OMqYXV_ruVW7JoEK48A:9 a=_Vgx9l1VpLgwpw_dHYaR:22 X-Proofpoint-GUID: daZGluirUH1Y7PDTNZ8euarGonZSb7kg X-Proofpoint-ORIG-GUID: daZGluirUH1Y7PDTNZ8euarGonZSb7kg X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDIxMCBTYWx0ZWRfX5phOHP0iIiE8 mx46yTmAGmnZzDxxhlyIlQH+TDhxXDD2p93V4j14TDR6fhHzAMlh/zK6zKG6+8DC/GAN+PvRM2W kMXmd7xikw2ITPT3f4ZSBuY4ZgKdDPKhAXE8FzOs1ZW++zjArfrvFEH9h9gcXGHIOG9WsnVz0UH D/aGwrg+wgrqly4TFqF3US80iYKgtGsRs6Fs123uSfPcwoAhdMiRjDASsa4S33DlBGMtcW/cuOy may3fHNo62BWfiKxcZVKXSfjXEjKYvI7WZ6QffXL39EasgopZryt6qY2pGAN8DPmZ1qmEOHc8v6 M7osldDl8l4+1vZ0U6LjetMGPmLVF6+iWyWuFiT8T3oCtr3UeB1CT2RPtnuXxLSHy+D3Sj4t06E zZC7NmJGc7IfeuWi+g1Tq9HVarbHFyNtggCtZZps8gnzD3COsHH6E34wMi5tKovNwKuvfjxx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_11,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 phishscore=0 mlxlogscore=999 priorityscore=1501 mlxscore=0 bulkscore=0 adultscore=0 spamscore=0 suspectscore=0 malwarescore=0 clxscore=1015 impostorscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505280210 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual temp DAC registers to set the threshold temperature for over-temperature stages 1 (warning), 2 (system shutdown), and 3 (emergency shutdown) instead of a single register to specify a set of thresholds. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 140 ++++++++++++++++++++ 1 file changed, 140 insertions(+) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 59a25f02a278..29ec6445fc21 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -26,6 +26,11 @@ #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 +/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 + #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 @@ -65,6 +70,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { =20 #define TEMP_STAGE_HYSTERESIS 2000 =20 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the thr= eshold + * for each stage independently. + * TEMP_DAC_STG* =3D 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC= ). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] =3D { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -73,6 +97,7 @@ struct qpnp_tm_chip; struct spmi_temp_alarm_data { const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*setup)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; @@ -87,6 +112,7 @@ struct qpnp_tm_chip { unsigned int thresh; unsigned int stage; unsigned int base; + unsigned int ntrips; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; @@ -304,6 +330,54 @@ static const struct thermal_zone_device_ops qpnp_tm_se= nsor_ops =3D { .set_trip_temp =3D qpnp_tm_set_trip_temp, }; =20 +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, in= t trip, int temp) +{ + int ret, temp_cfg; + u8 reg; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip < 0 || trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip =3D %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp =3D %d\n", temp); + return -EINVAL; + } + + reg =3D TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg =3D TEMP_DAC_REG_TO_TEMP(reg); + + ret =3D qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -328,6 +402,60 @@ static int qpnp_tm_configure_trip_temp(struct qpnp_tm_= chip *chip) return ret; } =20 +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *= trip, void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + mutex_lock(&chip->lock); + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->tempe= rature); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chi= p) +{ + int ret, i; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, + qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + for (i =3D 1; i < STAGE_COUNT; i++) { + if (chip->temp_thresh_map[i] <=3D chip->temp_thresh_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=3D%ld <=3D threshold %d=3D%ld\n", + i, chip->temp_thresh_map[i], i - 1, + chip->temp_thresh_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_setup(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg =3D 0; + + for (i =3D 0; i < STAGE_COUNT; i++) { + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_thresh_map[i] =3D TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -349,6 +477,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev1_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = =3D { + .ops =3D &qpnp_tm_gen2_rev2_sensor_ops, + .setup =3D qpnp_tm_gen2_rev2_setup, + .configure_trip_temps =3D qpnp_tm_gen2_rev2_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -467,6 +602,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->subtype =3D subtype; if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) chip->data =3D &spmi_temp_alarm_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 2) + chip->data =3D &spmi_temp_alarm_gen2_rev2_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) @@ -491,6 +628,9 @@ static int qpnp_tm_probe(struct platform_device *pdev) } } =20 + if (chip->data->setup) + chip->data->setup(chip); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature --=20 2.34.1 From nobody Tue Dec 16 14:39:34 2025 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0705826A1B0 for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-23506cd3506sm1403445ad.156.2025.05.28.16.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:50:35 -0700 (PDT) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, srinivas.kandagatla@linaro.org, stefan.schmidt@linaro.org, quic_tsoni@quicinc.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org, dmitry.baryshkov@oss.qualcomm.com Subject: [PATCH v4 5/5] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Wed, 28 May 2025 16:50:26 -0700 Message-Id: <20250528235026.4171109-6-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> References: <20250528235026.4171109-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: BUH_D000tuAszjSc_XvgqKhHTiXS3tBv X-Proofpoint-ORIG-GUID: BUH_D000tuAszjSc_XvgqKhHTiXS3tBv X-Authority-Analysis: v=2.4 cv=X8pSKHTe c=1 sm=1 tr=0 ts=6837a14d cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=dt9VzEwgFbYA:10 a=EUspDBNiAAAA:8 a=rhdsTsYyw6L1dzp8dgcA:9 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDIwOSBTYWx0ZWRfX7bb2VZ+NQ5w7 EzRsTCEkHDvPbncVqLEWn0F+F/tKQnm35wAA6uzlLPTN5izZaTudlS8FxtkTt2cREuY6ELBCXDY IaexKRO4yyDpOJBk7XziuSk0V3/g2xZcaVe6FVRGq35sD305HXXUGZwGT6in8aTM66l8oivwDAi yh2C9yNyEAxzJ7A7J4jZJlMb50HnBRB7lm9dQIaGji0yINcpjbjXi7Fpry6wsUYbkpmI9A5YUE5 SwnTOCOwbzg88iHn7zcQo6JlyvCCySP1JXPAKJMQ+2pZW55fYhmvTubzi+3XJAqwCopOS7od2Mo CicESJ2z83jZKG0CGZKDeW0eLCa8rF1xos5miQmhrbMAnkZvJx7jsmdsIn4SzL2iqrIBcPSJeV4 OXGQ+wphEQfI6S127HVWYzJ6ExWM9zsAeoV75uFxt5IDUHp9IDBjRYASMknDlIr/4gi9wDl4 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_11,2025-05-27_01,2025-03-28_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 mlxscore=0 lowpriorityscore=0 phishscore=0 spamscore=0 adultscore=0 impostorscore=0 bulkscore=0 mlxlogscore=999 suspectscore=0 clxscore=1015 malwarescore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2505160000 definitions=main-2505280209 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 208 +++++++++++++++++++- 1 file changed, 207 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 29ec6445fc21..1dcbc4415db3 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -23,6 +23,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 @@ -30,14 +31,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 =20 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) =20 +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) =20 @@ -45,6 +52,8 @@ =20 #define ALARM_CTRL_FORCE_ENABLE BIT(7) =20 +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 =20 @@ -89,6 +98,19 @@ static const long temp_dac_max[STAGE_COUNT] =3D { 119375, 159375, 159375 }; =20 +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] =3D { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] =3D { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -197,6 +219,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_= chip *chip) return alarm_state_map[ret]; } =20 +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -378,6 +418,98 @@ static const struct thermal_zone_device_ops qpnp_tm_ge= n2_rev2_sensor_ops =3D { .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, }; =20 +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, int tri= p, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u16 addr; + u8 reg, thresh; + + WARN_ON(!mutex_is_locked(&chip->lock)); + + if (trip < 0 || trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip =3D %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map =3D temp_lite_warning_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map =3D temp_lite_shutdown_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp =3D %d\n", temp); + return -EINVAL; + } + + thresh =3D 0; + temp_cfg =3D temp_map[thresh]; + for (i =3D THRESH_MAX; i >=3D THRESH_MIN; i--) { + if (temp >=3D temp_map[i]) { + thresh =3D i; + temp_cfg =3D temp_map[i]; + break; + } + } + + if (temp_cfg =3D=3D chip->temp_thresh_map[trip]) + return 0; + + ret =3D qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=3D%d\n", ret); + return ret; + } + + reg &=3D ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |=3D FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret =3D qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -456,6 +588,70 @@ static int qpnp_tm_gen2_rev2_setup(struct qpnp_tm_chip= *chip) return 0; } =20 +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip,= void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + mutex_lock(&chip->lock); + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperatur= e); + chip->ntrips++; + mutex_unlock(&chip->lock); + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_t= rip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <=3D chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=3D%ld <=3D threshold 0=3D%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_setup(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg =3D 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in softwa= re + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] =3D temp_lite_warning_map[thresh]; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] =3D temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -484,6 +680,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev2_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data =3D { + .ops =3D &qpnp_tm_lite_sensor_ops, + .setup =3D qpnp_tm_lite_setup, + .configure_trip_temps =3D qpnp_tm_lite_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_lite_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -593,7 +796,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 - && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { + && subtype !=3D QPNP_TM_SUBTYPE_GEN2 + && subtype !=3D QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -608,6 +812,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) chip->data =3D &spmi_temp_alarm_gen2_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_LITE) + chip->data =3D &spmi_temp_alarm_lite_data; else return -ENODEV; =20 --=20 2.34.1