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Miller" , Amit Singh Tomar , Kuan-Wei Chiu , Peter Zijlstra , Bjorn Helgaas , Philipp Stanner , Shashank Gupta , , , Tanmay Jagdale Subject: [PATCH 1/2] crypto: octeontx2: Rework how engine group number is obtained Date: Wed, 28 May 2025 20:29:40 +0530 Message-ID: <20250528145941.2659706-2-amitsinght@marvell.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250528145941.2659706-1-amitsinght@marvell.com> References: <20250528145941.2659706-1-amitsinght@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: QvGPBgVmeOEd8ii4BNgzwZvcBuAQwnNC X-Proofpoint-Spam-Details-Enc: AW1haW4tMjUwNTI4MDEzMCBTYWx0ZWRfX2OQKxb9wcdNI kmHpCXzTGXTX2320W/f/dmg4lwiuOuD8OmBaPCX9snre3nvGh0Pyg/185U6e5KUCG5bSj4O8+pC PCzQum6U0febxQUq01DrAojQikeT34cfWWPO+DCf6FR7kdJTcF4ia2vlZZ6AnJZbuuEmdjKd2qb 1Qum210FNiv4FoKDWDVwNXakYVm7kAZE64RBNaGE9JQdMMueba1hoIKeiYK0JRlDaRnBNmupxYS 5giR4nb3+aOEQxnDl0ePWtImHlbvQ++qPeTatFDUbUfAwSwWS/DA25wubOxQf7C+Eg5qFk7QITe uhiOMYyQFUZ0w6NjJnHIoweBVDFWoKCXWAB6LJbOZ2ozqDcgYbnTdjAKL4PVL1V4qU69ljLA32Z oOVTFv1ZO/sTqnuAhp2FcuaK4WutBC0SBAfhj2hiICCia50vFGRI0ykXlskcUtH5qR+oPY1X X-Proofpoint-GUID: QvGPBgVmeOEd8ii4BNgzwZvcBuAQwnNC X-Authority-Analysis: v=2.4 cv=baVrUPPB c=1 sm=1 tr=0 ts=683724ed cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=dt9VzEwgFbYA:10 a=M5GUcnROAAAA:8 a=8f77AyW8qadUDfJvTo0A:9 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1099,Hydra:6.0.736,FMLib:17.12.80.40 definitions=2025-05-28_07,2025-05-27_01,2025-03-28_01 Content-Type: text/plain; charset="utf-8" By default, otx2_cpt_get_kcrypto_eng_grp_num() returns the engine group number of SE engine type. Add an engine type parameter to support retrieving the engine group number for different engine types. Since otx2_cpt_get_kcrypto_eng_grp_num() always returns the kernel crypto engine group number, rename it to otx2_cpt_get_eng_grp_num(). Signed-off-by: Amit Singh Tomar --- drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h | 3 ++- drivers/crypto/marvell/octeontx2/otx2_cptlf.h | 2 +- drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c | 6 ++++-- drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c | 13 +++++++------ drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c | 5 ++++- .../crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c | 12 ++++++++++-- 6 files changed, 28 insertions(+), 13 deletions(-) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h b/drivers/c= rypto/marvell/octeontx2/otx2_cpt_reqmgr.h index e27e849b01df..72473f0070f3 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cpt_reqmgr.h @@ -490,6 +490,7 @@ struct otx2_cptlf_wqe; int otx2_cpt_do_request(struct pci_dev *pdev, struct otx2_cpt_req_info *re= q, int cpu_num); void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe); -int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev); +int otx2_cpt_get_eng_grp_num(struct pci_dev *pdev, + enum otx2_cpt_eng_type); =20 #endif /* __OTX2_CPT_REQMGR_H */ diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h b/drivers/crypto= /marvell/octeontx2/otx2_cptlf.h index 6e004a5568d8..49ec2b92e86d 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptlf.h +++ b/drivers/crypto/marvell/octeontx2/otx2_cptlf.h @@ -124,7 +124,7 @@ struct otx2_cptlfs_info { struct cpt_hw_ops *ops; u8 are_lfs_attached; /* Whether CPT LFs are attached */ u8 lfs_num; /* Number of CPT LFs */ - u8 kcrypto_eng_grp_num; /* Kernel crypto engine group number */ + u8 kcrypto_se_eng_grp_num; /* Crypto symmetric engine group number */ u8 kvf_limits; /* Kernel crypto limits */ atomic_t state; /* LF's state. started/reset */ int blkaddr; /* CPT blkaddr: BLKADDR_CPT0/BLKADDR_CPT1 */ diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptvf_algs.c index 7eb0bc13994d..8d9f394d6b50 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_algs.c @@ -384,7 +384,8 @@ static inline int cpt_enc_dec(struct skcipher_request *= req, u32 enc) req_info->req_type =3D OTX2_CPT_ENC_DEC_REQ; req_info->is_enc =3D enc; req_info->is_trunc_hmac =3D false; - req_info->ctrl.s.grp =3D otx2_cpt_get_kcrypto_eng_grp_num(pdev); + req_info->ctrl.s.grp =3D otx2_cpt_get_eng_grp_num(pdev, + OTX2_CPT_SE_TYPES); =20 req_info->req.cptr =3D ctx->er_ctx.hw_ctx; req_info->req.cptr_dma =3D ctx->er_ctx.cptr_dma; @@ -1288,7 +1289,8 @@ static int cpt_aead_enc_dec(struct aead_request *req,= u8 reg_type, u8 enc) if (status) return status; =20 - req_info->ctrl.s.grp =3D otx2_cpt_get_kcrypto_eng_grp_num(pdev); + req_info->ctrl.s.grp =3D otx2_cpt_get_eng_grp_num(pdev, + OTX2_CPT_SE_TYPES); =20 /* * We perform an asynchronous send and once diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptvf_main.c index 56904bdfd6e8..79adc224066e 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_main.c @@ -265,17 +265,18 @@ static int cptvf_lf_init(struct otx2_cptvf_dev *cptvf) u8 eng_grp_msk; =20 /* Get engine group number for symmetric crypto */ - cptvf->lfs.kcrypto_eng_grp_num =3D OTX2_CPT_INVALID_CRYPTO_ENG_GRP; + cptvf->lfs.kcrypto_se_eng_grp_num =3D OTX2_CPT_INVALID_CRYPTO_ENG_GRP; ret =3D otx2_cptvf_send_eng_grp_num_msg(cptvf, OTX2_CPT_SE_TYPES); if (ret) return ret; =20 - if (cptvf->lfs.kcrypto_eng_grp_num =3D=3D OTX2_CPT_INVALID_CRYPTO_ENG_GRP= ) { - dev_err(dev, "Engine group for kernel crypto not available\n"); - ret =3D -ENOENT; - return ret; + if (cptvf->lfs.kcrypto_se_eng_grp_num =3D=3D + OTX2_CPT_INVALID_CRYPTO_ENG_GRP) { + dev_err(dev, + "Symmetric Engine group for crypto not available\n"); + return -ENOENT; } - eng_grp_msk =3D 1 << cptvf->lfs.kcrypto_eng_grp_num; + eng_grp_msk =3D 1 << cptvf->lfs.kcrypto_se_eng_grp_num; =20 ret =3D otx2_cptvf_send_kvf_limits_msg(cptvf); if (ret) diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c b/drivers/c= rypto/marvell/octeontx2/otx2_cptvf_mbox.c index 931b72580fd9..f36d75f40014 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_mbox.c @@ -75,6 +75,7 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptvf_= dev *cptvf, struct otx2_cpt_caps_rsp *eng_caps; struct cpt_rd_wr_reg_msg *rsp_reg; struct msix_offset_rsp *rsp_msix; + u8 grp_num; int i; =20 if (msg->id >=3D MBOX_MSG_MAX) { @@ -122,7 +123,9 @@ static void process_pfvf_mbox_mbox_msg(struct otx2_cptv= f_dev *cptvf, break; case MBOX_MSG_GET_ENG_GRP_NUM: rsp_grp =3D (struct otx2_cpt_egrp_num_rsp *) msg; - cptvf->lfs.kcrypto_eng_grp_num =3D rsp_grp->eng_grp_num; + grp_num =3D rsp_grp->eng_grp_num; + if (rsp_grp->eng_type =3D=3D OTX2_CPT_SE_TYPES) + cptvf->lfs.kcrypto_se_eng_grp_num =3D grp_num; break; case MBOX_MSG_GET_KVF_LIMITS: rsp_limits =3D (struct otx2_cpt_kvf_limits_rsp *) msg; diff --git a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c b/drivers= /crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c index 426244107037..8b4ac269330a 100644 --- a/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c +++ b/drivers/crypto/marvell/octeontx2/otx2_cptvf_reqmgr.c @@ -391,9 +391,17 @@ void otx2_cpt_post_process(struct otx2_cptlf_wqe *wqe) &wqe->lfs->lf[wqe->lf_num].pqueue); } =20 -int otx2_cpt_get_kcrypto_eng_grp_num(struct pci_dev *pdev) +int otx2_cpt_get_eng_grp_num(struct pci_dev *pdev, + enum otx2_cpt_eng_type eng_type) { struct otx2_cptvf_dev *cptvf =3D pci_get_drvdata(pdev); =20 - return cptvf->lfs.kcrypto_eng_grp_num; + switch (eng_type) { + case OTX2_CPT_SE_TYPES: + return cptvf->lfs.kcrypto_se_eng_grp_num; + default: + dev_err(&cptvf->pdev->dev, "Unsupported engine type"); + break; + } + return -ENXIO; } --=20 2.48.1