From nobody Sat Feb 7 16:49:50 2026 Received: from zg8tmja5ljk3lje4ms43mwaa.icoremail.net (zg8tmja5ljk3lje4ms43mwaa.icoremail.net [209.97.181.73]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A5A1C1F1311; Wed, 28 May 2025 04:18:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.97.181.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748405924; cv=none; b=SIF11A5LHFQeHzm6v/jUbKMig4hUEnjO3+qB9qJYdTwnkKvjgrOJ/G3g6YD2lMpnEoehgansBZJY/484OKT/DCINfDTCQlXzi1VwVtliWsAuyqAHdUn119JISi2Fz50xw4GjxGzhTs8x6QKIF58dAFjGVSEe/UHRYECmpdsIbnw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748405924; c=relaxed/simple; bh=2GspJ+bdfd7LNh3QxZy4kWKM/ckvFnpizuzn9Z579yo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=o2+oCvNCDWcnGuO3pGgSjlQ43XL4clNLnhjwPfkrF9jXzhAqfxrKWzZAZOr0NkqZnOC0+wb05k41d1AtpbSvjEwnN1zmkO4CJ4qI4zcm7UQSzByf3zW2pw8KK7nf5TwuK0A7ioXrfdeNaCHOK0tU2ITfF7Qh8tFT/jw7GTIOf14= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com; spf=pass smtp.mailfrom=eswincomputing.com; arc=none smtp.client-ip=209.97.181.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=eswincomputing.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=eswincomputing.com Received: from E0005182DT.eswin.cn (unknown [10.12.97.162]) by app2 (Coremail) with SMTP id TQJkCgAHppQCjjZobBGVAA--.51322S2; Wed, 28 May 2025 12:16:04 +0800 (CST) From: weishangjuan@eswincomputing.com To: andrew+netdev@lunn.ch, davem@davemloft.net, edumazet@google.com, kuba@kernel.org, pabeni@redhat.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, vladimir.oltean@nxp.com, rmk+kernel@armlinux.org.uk, yong.liang.choong@linux.intel.com, prabhakar.mahadev-lad.rj@bp.renesas.com, inochiama@gmail.com, jan.petrous@oss.nxp.com, jszhang@kernel.org, p.zabel@pengutronix.de, 0x1207@gmail.com, boon.khai.ng@altera.com, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org Cc: ningyu@eswincomputing.com, linmin@eswincomputing.com, lizhi2@eswincomputing.com, Shangjuan Wei Subject: [PATCH v2 1/2] dt-bindings: ethernet: eswin: Document for EIC7700 SoC Date: Wed, 28 May 2025 12:15:58 +0800 Message-ID: <20250528041558.895-1-weishangjuan@eswincomputing.com> X-Mailer: git-send-email 2.49.0.windows.1 In-Reply-To: <20250528041455.878-1-weishangjuan@eswincomputing.com> References: <20250528041455.878-1-weishangjuan@eswincomputing.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-CM-TRANSID: TQJkCgAHppQCjjZobBGVAA--.51322S2 X-Coremail-Antispam: 1UD129KBjvJXoWxtry5Gw17Gr17Kw17KF15Jwb_yoW7uFy8pF W8C347JF1Sqr43Xa1xKF10kF1aqan7Grn0krnFq343ta9Iqa4Yqr4akF15Ga4UAr1xZa45 WFy5A34Iya17Ar7anT9S1TB71UUUUU7qnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBm14x267AKxVWrJVCq3wAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW0oVCq3wA2z4x0Y4vEx4A2jsIEc7CjxVAFwI0_Gc CE3s1le2I262IYc4CY6c8Ij28IcVAaY2xG8wAqx4xG64xvF2IEw4CE5I8CrVC2j2WlYx0E 2Ix0cI8IcVAFwI0_JrI_JrylYx0Ex4A2jsIE14v26r1j6r4UMcvjeVCFs4IE7xkEbVWUJV W8JwACjcxG0xvY0x0EwIxGrwACjI8F5VA0II8E6IAqYI8I648v4I1lFIxGxcIEc7CjxVA2 Y2ka0xkIwI1lw4CEc2x0rVAKj4xxMxkF7I0En4kS14v26r4a6rW5MxkIecxEwVCm-wCF04 k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s026c02F40E14v26r1j6r18 MI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_GFv_WrylIxkGc2Ij64vIr4 1lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvEc7CjxVAFwI0_Cr0_Gr1U MIIF0xvE42xK8VAvwI8IcIk0rVWUJVWUCwCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I 8E87Iv6xkF7I0E14v26r4j6r4UJbIYCTnIWIevJa73UjIFyTuYvjTRimiiDUUUU X-CM-SenderInfo: pzhl2xxdqjy31dq6v25zlqu0xpsx3x1qjou0bp/ Content-Type: text/plain; charset="utf-8" From: Shangjuan Wei Add ESWIN EIC7700 Ethernet controller, supporting multi-rate (10M/100M/1G) auto-negotiation, clock/reset control, and AXI bus parameter optimization. Signed-off-by: Zhi Li Signed-off-by: Shangjuan Wei --- .../bindings/net/eswin,eic7700-eth.yaml | 200 ++++++++++++++++++ 1 file changed, 200 insertions(+) create mode 100644 Documentation/devicetree/bindings/net/eswin,eic7700-eth= .yaml diff --git a/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml b= /Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml new file mode 100644 index 000000000000..c76d2fbf0ebd --- /dev/null +++ b/Documentation/devicetree/bindings/net/eswin,eic7700-eth.yaml @@ -0,0 +1,200 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/net/eswin,eic7700-eth.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Eswin EIC7700 SOC Eth Controller + +maintainers: + - Shuang Liang + - Zhi Li + - Shangjuan Wei + +description: + The eth controller registers are part of the syscrg block on + the EIC7700 SoC. + +select: + properties: + compatible: + contains: + enum: + - eswin,eic7700-qos-eth + required: + - compatible + +allOf: + - $ref: snps,dwmac.yaml# + +properties: + compatible: + items: + - const: eswin,eic7700-qos-eth + - const: snps,dwmac + + reg: + description: Base address and size of the Ethernet controller registers + items: + - description: Register base address + - description: Register size + + interrupt-names: + const: macirq + + interrupts: + maxItems: 1 + + phy-mode: + $ref: /schemas/types.yaml#/definitions/string + enum: + - rgmii + - rgmii-rxid + - rgmii-txid + - rgmii-id + + phy-handle: + $ref: /schemas/types.yaml#/definitions/phandle + description: Reference to the PHY device + + clocks: + minItems: 3 + maxItems: 7 + + clock-names: + minItems: 3 + contains: + enum: + - app + - stmmaceth + - tx + + resets: + maxItems: 1 + + reset-names: + items: + - const: stmmaceth + + dma-noncoherent: true + + # Custom properties + eswin,hsp_sp_csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: HSP peripheral control register area + - description: Control registers (such as used to select TX clock + source, PHY interface mode) + - description: AXI bus low-power control related registers + - description: Status register + description: + Configure TX clock source selection, set PHY interface mode, + and control low-power bus behavior + + eswin,syscrg_csr: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: CRG's device tree node handle + - description: Enable and divide HSP ACLK control + - description: Behavior of configuring HSP controller + description: + Register that accesses the system clock controller. + Used to configure HSP clocks for Ethernet subsystems + + eswin,dly_hsp_reg: + $ref: /schemas/types.yaml#/definitions/phandle-array + items: + - items: + - description: TX delay control register offset + - description: RX delay control register offset + - description: Switch for controlling delay function + description: + Register for configuring delay compensation between MAC/PHY + + snps,axi-config: + $ref: /schemas/types.yaml#/definitions/phandle + description: AXI bus configuration + + stmmac-axi-config: + type: object + unevaluatedProperties: false + properties: + snps,blen: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: Set the burst transmission length of AXI bus + snps,rd_osr_lmt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Set OSR restrictions for read operations + snps,wr_osr_lmt: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Set OSR restrictions for write operations + snps,lpi_en: + $ref: /schemas/types.yaml#/definitions/flag + description: Low Power Interface enable flag (true/false) + required: + - snps,blen + - snps,rd_osr_lmt + - snps,wr_osr_lmt + - snps,lpi_en + additionalProperties: false + +required: + - compatible + - reg + - interrupt-names + - interrupts + - phy-mode + - clocks + - clock-names + - resets + - reset-names + - eswin,hsp_sp_csr + - eswin,syscrg_csr + - eswin,dly_hsp_reg + - snps,axi-config + +additionalProperties: false + +examples: + - | + gmac0: ethernet@50400000 { + compatible =3D "eswin,eic7700-qos-eth", "snps,dwmac"; + reg =3D <0x0 0x50400000 0x0 0x10000>; + interrupt-parent =3D <&plic>; + interrupt-names =3D "macirq"; + interrupts =3D <61>; + phy-mode =3D "rgmii-txid"; + phy-handle =3D <&phy0>; + status =3D "okay"; + clocks =3D <&clock 550>, + <&clock 551>, + <&clock 552>; + clock-names =3D "app", "stmmaceth", "tx"; + resets =3D <&reset 0x07 (1 << 26)>; + reset-names =3D "stmmaceth"; + dma-noncoherent; + eswin,hsp_sp_csr =3D <&hsp_sp_csr 0x1030 0x100 0x108>; + eswin,syscrg_csr =3D <&sys_crg 0x148 0x14c>; + eswin,dly_hsp_reg =3D <0x114 0x118 0x11c>; + snps,axi-config =3D <&stmmac_axi_setup>; + stmmac_axi_setup: stmmac-axi-config { + snps,blen =3D <0 0 0 0 16 8 4>; + snps,rd_osr_lmt =3D <2>; + snps,wr_osr_lmt =3D <2>; + snps,lpi_en; + }; + /* mdio { + compatible =3D "snps,dwmac-mdio"; + status =3D "okay"; + #address-cells =3D <1>; + #size-cells =3D <0>; + + phy0: ethernet-phy@0 { + device_type =3D "ethernet-phy"; + reg =3D <0>; + compatible =3D "ethernet-phy-id001c.c916", "realtek,rtl8211f"; + }; + }; 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charset="utf-8" From: Shangjuan Wei Add Ethernet controller support for Eswin's eic7700 SoC. The driver provides management and control of Ethernet signals for the eiC7700 series chips. Signed-off-by: Zhi Li Signed-off-by: Shangjuan Wei --- drivers/net/ethernet/stmicro/stmmac/Kconfig | 11 + drivers/net/ethernet/stmicro/stmmac/Makefile | 1 + .../ethernet/stmicro/stmmac/dwmac-eic7700.c | 410 ++++++++++++++++++ 3 files changed, 422 insertions(+) create mode 100644 drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c diff --git a/drivers/net/ethernet/stmicro/stmmac/Kconfig b/drivers/net/ethe= rnet/stmicro/stmmac/Kconfig index 67fa879b1e52..a13b15ce1abd 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Kconfig +++ b/drivers/net/ethernet/stmicro/stmmac/Kconfig @@ -67,6 +67,17 @@ config DWMAC_ANARION =20 This selects the Anarion SoC glue layer support for the stmmac driver. =20 +config DWMAC_EIC7700 + tristate "Support for Eswin eic7700 ethernet driver" + select CRC32 + select MII + depends on OF && HAS_DMA && ARCH_ESWIN || COMPILE_TEST + help + This driver supports the Eswin EIC7700 Ethernet controller, + which integrates Synopsys DesignWare QoS features. It enables + high-speed networking with DMA acceleration and is optimized + for embedded systems. + config DWMAC_INGENIC tristate "Ingenic MAC support" default MACH_INGENIC diff --git a/drivers/net/ethernet/stmicro/stmmac/Makefile b/drivers/net/eth= ernet/stmicro/stmmac/Makefile index b591d93f8503..f4ec5fc16571 100644 --- a/drivers/net/ethernet/stmicro/stmmac/Makefile +++ b/drivers/net/ethernet/stmicro/stmmac/Makefile @@ -14,6 +14,7 @@ stmmac-$(CONFIG_STMMAC_SELFTESTS) +=3D stmmac_selftests.o # Ordering matters. Generic driver must be last. obj-$(CONFIG_STMMAC_PLATFORM) +=3D stmmac-platform.o obj-$(CONFIG_DWMAC_ANARION) +=3D dwmac-anarion.o +obj-$(CONFIG_DWMAC_EIC7700) +=3D dwmac-eic7700.o obj-$(CONFIG_DWMAC_INGENIC) +=3D dwmac-ingenic.o obj-$(CONFIG_DWMAC_IPQ806X) +=3D dwmac-ipq806x.o obj-$(CONFIG_DWMAC_LPC18XX) +=3D dwmac-lpc18xx.o diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c b/drivers/= net/ethernet/stmicro/stmmac/dwmac-eic7700.c new file mode 100644 index 000000000000..98b1e63913be --- /dev/null +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-eic7700.c @@ -0,0 +1,410 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Eswin DWC Ethernet linux driver + * + * Authors: Shuang Liang + * Shangjuan Wei + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "stmmac_platform.h" +#include "dwmac4.h" + +#include + +/* eth_phy_ctrl_offset eth0:0x100; eth1:0x200 */ +#define ETH_TX_CLK_SEL BIT(16) +#define ETH_PHY_INTF_SELI BIT(0) + +/* eth_axi_lp_ctrl_offset eth0:0x108; eth1:0x208 */ +#define ETH_CSYSREQ_VAL BIT(0) + +/* hsp_aclk_ctrl_offset (0x148) */ +#define HSP_ACLK_CLKEN BIT(31) +#define HSP_ACLK_DIVSOR (0x2 << 4) + +/* hsp_cfg_ctrl_offset (0x14c) */ +#define HSP_CFG_CLKEN BIT(31) +#define SCU_HSP_PCLK_EN BIT(30) +#define HSP_CFG_CTRL_REGSET (HSP_CFG_CLKEN | SCU_HSP_PCLK_EN) + +/* PHY default addr in mdio*/ +#define PHY_ADDR -1 + +struct eswin_qos_priv { + struct device *dev; + int dev_id; + struct regmap *crg_regmap; + struct regmap *hsp_regmap; + int phyaddr; + unsigned int dly_hsp_reg[3]; + unsigned int dly_param_1000m[3]; + unsigned int dly_param_100m[3]; + unsigned int dly_param_10m[3]; +}; + +static struct clk *dwc_eth_find_clk(struct plat_stmmacenet_data *plat_dat, + const char *name) +{ + for (int i =3D 0; i < plat_dat->num_clks; i++) + if (strcmp(plat_dat->clks[i].id, name) =3D=3D 0) + return plat_dat->clks[i].clk; + + return NULL; +} + +static int dwc_eth_dwmac_config_dt(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat) +{ + struct device *dev =3D &pdev->dev; + u32 burst_map =3D 0; + u32 bit_index =3D 0; + u32 a_index =3D 0; + + if (!plat_dat->axi) { + plat_dat->axi =3D devm_kzalloc(&pdev->dev, sizeof(struct stmmac_axi), GF= P_KERNEL); + + if (!plat_dat->axi) + return -ENOMEM; + } + + plat_dat->axi->axi_lpi_en =3D device_property_read_bool(dev, + "snps,en-lpi"); + if (device_property_read_u32(dev, "snps,write-requests", + &plat_dat->axi->axi_wr_osr_lmt)) { + /** + * Since the register has a reset value of 1, if property + * is missing, default to 1. + */ + plat_dat->axi->axi_wr_osr_lmt =3D 1; + } else { + /** + * If property exists, to keep the behavior from dwc_eth_qos, + * subtract one after parsing. + */ + plat_dat->axi->axi_wr_osr_lmt--; + } + + if (device_property_read_u32(dev, "snps,read-requests", + &plat_dat->axi->axi_rd_osr_lmt)) { + /** + * Since the register has a reset value of 1, if property + * is missing, default to 1. + */ + plat_dat->axi->axi_rd_osr_lmt =3D 1; + } else { + /** + * If property exists, to keep the behavior from dwc_eth_qos, + * subtract one after parsing. + */ + plat_dat->axi->axi_rd_osr_lmt--; + } + device_property_read_u32(dev, "snps,burst-map", &burst_map); + + /* converts burst-map bitmask to burst array */ + for (bit_index =3D 0; bit_index < 7; bit_index++) { + if (burst_map & (1 << bit_index)) { + switch (bit_index) { + case 0: + plat_dat->axi->axi_blen[a_index] =3D 4; break; + case 1: + plat_dat->axi->axi_blen[a_index] =3D 8; break; + case 2: + plat_dat->axi->axi_blen[a_index] =3D 16; break; + case 3: + plat_dat->axi->axi_blen[a_index] =3D 32; break; + case 4: + plat_dat->axi->axi_blen[a_index] =3D 64; break; + case 5: + plat_dat->axi->axi_blen[a_index] =3D 128; break; + case 6: + plat_dat->axi->axi_blen[a_index] =3D 256; break; + default: + break; + } + a_index++; + } + } + + /* dwc-qos needs GMAC4, AAL, TSO and PMT */ + plat_dat->has_gmac4 =3D 1; + plat_dat->dma_cfg->aal =3D 1; + plat_dat->flags |=3D STMMAC_FLAG_TSO_EN; + plat_dat->pmt =3D 1; + + return 0; +} + +static int dwc_qos_probe(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat, + struct stmmac_resources *stmmac_res) +{ + plat_dat->pclk =3D dwc_eth_find_clk(plat_dat, "phy_ref_clk"); + + return 0; +} + +static void eswin_qos_fix_speed(void *priv, int speed, unsigned int mode) +{ + struct eswin_qos_priv *dwc_priv =3D priv; + int i; + + switch (speed) { + case SPEED_1000: + for (i =3D 0; i < 3; i++) + regmap_write(dwc_priv->hsp_regmap, + dwc_priv->dly_hsp_reg[i], + dwc_priv->dly_param_1000m[i]); + + break; + case SPEED_100: + for (i =3D 0; i < 3; i++) { + regmap_write(dwc_priv->hsp_regmap, + dwc_priv->dly_hsp_reg[i], + dwc_priv->dly_param_100m[i]); + } + + break; + case SPEED_10: + for (i =3D 0; i < 3; i++) { + regmap_write(dwc_priv->hsp_regmap, + dwc_priv->dly_hsp_reg[i], + dwc_priv->dly_param_10m[i]); + } + + break; + default: + dev_err(dwc_priv->dev, "invalid speed %u\n", speed); + break; + } +} + +static int eswin_qos_probe(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat, + struct stmmac_resources *stmmac_res) +{ + struct eswin_qos_priv *dwc_priv; + u32 hsp_aclk_ctrl_offset; + u32 hsp_aclk_ctrl_regset; + u32 hsp_cfg_ctrl_offset; + u32 eth_axi_lp_ctrl_offset; + u32 eth_phy_ctrl_offset; + u32 eth_phy_ctrl_regset; + struct clk *clk_app; + int ret; + int err; + + dwc_priv =3D devm_kzalloc(&pdev->dev, sizeof(*dwc_priv), GFP_KERNEL); + if (!dwc_priv) + return -ENOMEM; + + if (device_property_read_u32(&pdev->dev, "id", &dwc_priv->dev_id)) + return dev_err_probe(&pdev->dev, -EINVAL, + "Can not read device id!\n"); + + dwc_priv->dev =3D &pdev->dev; + + ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,phyaddr", 0, + &dwc_priv->phyaddr); + if (ret) + dev_warn(&pdev->dev, "can't get phyaddr (%d)\n", ret); + + ret =3D of_property_read_variable_u32_array(pdev->dev.of_node, "eswin,dly= _hsp_reg", + &dwc_priv->dly_hsp_reg[0], 3, 0); + if (ret !=3D 3) { + dev_err(&pdev->dev, "can't get delay hsp reg.ret(%d)\n", ret); + return ret; + } + + ret =3D of_property_read_variable_u32_array(pdev->dev.of_node, "dly-param= -1000m", + &dwc_priv->dly_param_1000m[0], 3, 0); + if (ret !=3D 3) { + dev_err(&pdev->dev, "can't get delay param for 1Gbps mode (%d)\n", ret); + return ret; + } + + ret =3D of_property_read_variable_u32_array(pdev->dev.of_node, "dly-param= -100m", + &dwc_priv->dly_param_100m[0], 3, 0); + if (ret !=3D 3) { + dev_err(&pdev->dev, "can't get delay param for 100Mbps mode (%d)\n", ret= ); + return ret; + } + + ret =3D of_property_read_variable_u32_array(pdev->dev.of_node, "dly-param= -10m", + &dwc_priv->dly_param_10m[0], 3, 0); + if (ret !=3D 3) { + dev_err(&pdev->dev, "can't get delay param for 10Mbps mode (%d)\n", ret); + return ret; + } + + dwc_priv->crg_regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_nod= e, + "eswin,syscrg_csr"); + if (IS_ERR(dwc_priv->crg_regmap)) { + dev_dbg(&pdev->dev, "No syscrg_csr phandle specified\n"); + return 0; + } + + ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,syscrg_csr",= 1, + &hsp_aclk_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, "can't get syscrg_csr 1\n"); + + regmap_read(dwc_priv->crg_regmap, hsp_aclk_ctrl_offset, &hsp_aclk_ctrl_re= gset); + hsp_aclk_ctrl_regset |=3D (HSP_ACLK_CLKEN | HSP_ACLK_DIVSOR); + regmap_write(dwc_priv->crg_regmap, hsp_aclk_ctrl_offset, hsp_aclk_ctrl_re= gset); + + ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,syscrg_csr",= 2, + &hsp_cfg_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, "can't get syscrg_csr 2\n"); + + regmap_write(dwc_priv->crg_regmap, hsp_cfg_ctrl_offset, HSP_CFG_CTRL_REGS= ET); + + dwc_priv->hsp_regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_nod= e, + "eswin,hsp_sp_csr"); + if (IS_ERR(dwc_priv->hsp_regmap)) { + dev_dbg(&pdev->dev, "No hsp_sp_csr phandle specified\n"); + return 0; + } + + ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp_sp_csr",= 2, + ð_phy_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, "can't get hsp_sp_csr 2\n"); + + regmap_read(dwc_priv->hsp_regmap, + eth_phy_ctrl_offset, + ð_phy_ctrl_regset); + eth_phy_ctrl_regset |=3D (ETH_TX_CLK_SEL | ETH_PHY_INTF_SELI); + regmap_write(dwc_priv->hsp_regmap, + eth_phy_ctrl_offset, + eth_phy_ctrl_regset); + + ret =3D of_property_read_u32_index(pdev->dev.of_node, "eswin,hsp_sp_csr",= 3, + ð_axi_lp_ctrl_offset); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "can't get hsp_sp_csr 3\n"); + + regmap_write(dwc_priv->hsp_regmap, + eth_axi_lp_ctrl_offset, + ETH_CSYSREQ_VAL); + + clk_app =3D devm_clk_get_enabled(&pdev->dev, "app"); + if (IS_ERR(clk_app)) + return dev_err_probe(&pdev->dev, PTR_ERR(clk_app), + "error getting app clock\n"); + + plat_dat->clk_tx_i =3D devm_clk_get_enabled(&pdev->dev, "tx"); + if (IS_ERR(plat_dat->clk_tx_i)) + return dev_err_probe(&pdev->dev, PTR_ERR(plat_dat->clk_tx_i), + "error getting tx clock\n"); + + plat_dat->fix_mac_speed =3D eswin_qos_fix_speed; + plat_dat->set_clk_tx_rate =3D stmmac_set_clk_tx_rate; + plat_dat->bsp_priv =3D dwc_priv; + plat_dat->phy_addr =3D PHY_ADDR; + + return 0; +} + +struct dwc_eth_dwmac_data { + int (*probe)(struct platform_device *pdev, + struct plat_stmmacenet_data *plat_dat, + struct stmmac_resources *res); + const char *stmmac_clk_name; +}; + +static const struct dwc_eth_dwmac_data eswin_qos_data =3D { + .probe =3D eswin_qos_probe, + .stmmac_clk_name =3D "stmmaceth", +}; + +static int dwc_eth_dwmac_probe(struct platform_device *pdev) +{ + const struct dwc_eth_dwmac_data *data; + struct plat_stmmacenet_data *plat_dat; + struct stmmac_resources stmmac_res; + int ret; + + data =3D device_get_match_data(&pdev->dev); + + memset(&stmmac_res, 0, sizeof(struct stmmac_resources)); + + /** + * Since stmmac_platform supports name IRQ only, basic platform + * resource initialization is done in the glue logic. + */ + stmmac_res.irq =3D platform_get_irq(pdev, 0); + if (stmmac_res.irq < 0) + return stmmac_res.irq; + stmmac_res.wol_irq =3D stmmac_res.irq; + + stmmac_res.addr =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(stmmac_res.addr)) + return PTR_ERR(stmmac_res.addr); + + plat_dat =3D devm_stmmac_probe_config_dt(pdev, stmmac_res.mac); + if (IS_ERR(plat_dat)) + return PTR_ERR(plat_dat); + + plat_dat->stmmac_clk =3D dwc_eth_find_clk(plat_dat, + data->stmmac_clk_name); + + if (data->probe) + ret =3D data->probe(pdev, plat_dat, &stmmac_res); + if (ret < 0) { + return dev_err_probe(&pdev->dev, ret, + "failed to probe subdriver\n"); + } + + ret =3D dwc_eth_dwmac_config_dt(pdev, plat_dat); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to config dt\n"); + + ret =3D stmmac_dvr_probe(&pdev->dev, plat_dat, &stmmac_res); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "Failed to driver probe\n"); + + return ret; +} + +static const struct of_device_id dwc_eth_dwmac_match[] =3D { + { .compatible =3D "eswin,eic7700-qos-eth", .data =3D &eswin_qos_data }, + { } +}; +MODULE_DEVICE_TABLE(of, dwc_eth_dwmac_match); + +static struct platform_driver eic7700_eth_dwmac_driver =3D { + .probe =3D dwc_eth_dwmac_probe, + .remove =3D stmmac_pltfr_remove, + .driver =3D { + .name =3D "eic7700-eth-dwmac", + .pm =3D &stmmac_pltfr_pm_ops, + .of_match_table =3D dwc_eth_dwmac_match, + }, +}; +module_platform_driver(eic7700_eth_dwmac_driver); + +MODULE_AUTHOR("Eswin"); +MODULE_AUTHOR("Shuang Liang "); +MODULE_AUTHOR("Shangjuan Wei "); +MODULE_DESCRIPTION("Eswin eic7700 qos ethernet driver"); +MODULE_LICENSE("GPL"); --=20 2.17.1