From nobody Wed Feb 11 02:33:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EB671C84B6; Wed, 28 May 2025 14:45:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; cv=none; b=YwEqvDBfH0rkA5fFtx9mmj2/UOi+EwhsRMy4yp/JV+iD0DmpHRtLkc0icUZJSauKMi2xzYKp4OgBA4aSX6nk7lCwOHASHICs5oWPaOQt2h0yhwMkJJmS3OiHGa+ETT+jkcpU9BGVej2T18pBnE/Oeu755WrxpQVeKjvhQofhkCw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; c=relaxed/simple; bh=PEvKO/wryGgjZziPiEVFS4XnMJm6SAdt0loKuMnLA9A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=Cb7yEZJTKw4OjML5cz6SvONgOT2g3YjTLVCL4huuJcmdiKgis0wFXuIbqcPA0VTW2brchHNXCK8dxiGtoHSreejomtZU+DAwLSBTb5jLrNcWG7BgEjhUfE98tWq/pqcQRhSmZDv7tNsHbzH8zYjHQl4WHVx5uzURD/K4KDhSKfo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=X7HZd+Ll; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="X7HZd+Ll" Received: by smtp.kernel.org (Postfix) with ESMTPS id 8E100C4CEEE; Wed, 28 May 2025 14:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748443551; bh=PEvKO/wryGgjZziPiEVFS4XnMJm6SAdt0loKuMnLA9A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=X7HZd+Ll6udHHaRkGFj2oihkjy9Is68p5WdFt4+vGRMETR7GXP76MIg2Ozb+pdPLC vVbjWD5TxYrD2Cb5u2yeVQq2gXlxR++PsNE26LaEkKu+afd4laG5ebenkf7vg59lZ1 bowfuLIrhnif7S85lOmaHWzosGGBLePLb8wGmqn/5ZP/OkvIcOlEx9a6Hyg64+0EXP zeO3kA13boOFBuHsvzn1deG0NNkvJr1RE6mwa/nL0HwJX9cpa+wtcbuDUNX7q/mAMV F3QE8vEmpMAENU3jX3eVbm9yAKYJ0EO0UEw2CvJn00BdKss0gU4G3tgawL9O04yAeh gT0fLnFAQQ5iw== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7ACA8C5B543; Wed, 28 May 2025 14:45:51 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 28 May 2025 18:45:47 +0400 Subject: [PATCH v2 1/5] clk: qcom: gcc-ipq5018: fix GE PHY reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-ipq5018-ge-phy-v2-1-dd063674c71c@outlook.com> References: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> In-Reply-To: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748443549; l=1149; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=oIkUIGsEO4IxSACM3i9ZzN1oSf3eDEKLwbaKL+SIoYs=; b=plBci8b7HYWaMG2G9Eb+G7+BUipdemJQtdLnwRhaIW7a2U+uloPVTxAQzgwBVkFZoRuft6kDd u81Ysjr9Pi7ANUj9eLZlr8hLZ2KTDpxiQX/dsHbJrA9yUUWlCn4aXW5 X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The MISC reset is supposed to trigger a resets across the MDC, DSP, and RX & TX clocks of the IPQ5018 internal GE PHY. So let's set the bitmask of the reset definition accordingly in the GCC as per the downstream driver. Link: https://git.codelinaro.org/clo/qsdk/oss/kernel/linux-ipq-5.4/-/commit= /00743c3e82fa87cba4460e7a2ba32f473a9ce932 Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- drivers/clk/qcom/gcc-ipq5018.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/clk/qcom/gcc-ipq5018.c b/drivers/clk/qcom/gcc-ipq5018.c index 70f5dcb96700f55da1fb19fc893d22350a7e63bf..02d6f08f389f24eccc961b9a427= 1288c6b635bbc 100644 --- a/drivers/clk/qcom/gcc-ipq5018.c +++ b/drivers/clk/qcom/gcc-ipq5018.c @@ -3660,7 +3660,7 @@ static const struct qcom_reset_map gcc_ipq5018_resets= [] =3D { [GCC_WCSS_AXI_S_ARES] =3D { 0x59008, 6 }, [GCC_WCSS_Q6_BCR] =3D { 0x18004, 0 }, [GCC_WCSSAON_RESET] =3D { 0x59010, 0}, - [GCC_GEPHY_MISC_ARES] =3D { 0x56004, 0 }, + [GCC_GEPHY_MISC_ARES] =3D { 0x56004, .bitmask =3D 0xf }, }; =20 static const struct of_device_id gcc_ipq5018_match_table[] =3D { --=20 2.49.0 From nobody Wed Feb 11 02:33:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EAFB1C5485; Wed, 28 May 2025 14:45:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; cv=none; b=WjQ8oyXPmcdjmisUvVS7WfBKW0Fi2vzsbo8WClfkPifVati9rLrLJRluA1sra3GgxNhXD5BLETl0QmN+FcWzeFbx4/RGBsMEp8UFl26rHO3OJYB8d9Of47IcbQNHgw/GDdgDZCi7FfjZzur4cvwMge8Vm4NJrOJfSJF8t7976lQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; c=relaxed/simple; bh=5pMjgztKFg6Bo3bS0LIzfpMDgWFo5t3faxUx133uLyY=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bltFRWVzzVDueKrf8N71I5GG/apgDIY2D9wDjG6wHywOqj4Weo1KfVU4MtBgiK53qcusDSZGuNPQztvQYJNxzRqL9M6PyyLx3/aqOk8fBuY7q4mu8ZaQCWIjntWTEp4Y0OEIvtljpzTDtrQn3WfBklrWmcBxSeOvXq73CxflvLE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=PhXEuso1; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="PhXEuso1" Received: by smtp.kernel.org (Postfix) with ESMTPS id 9E718C4CEED; Wed, 28 May 2025 14:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748443551; bh=5pMjgztKFg6Bo3bS0LIzfpMDgWFo5t3faxUx133uLyY=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=PhXEuso1uBib7KZOBvQ5Y2w2bZqEYGg64LV0+kmO4Ts0in1b1KiyUdgB/2/jxxAU7 bThl9Ap7di5zzQy5CDwkN4APnOalu8ZlZoIVme9dPxjL+cFWZ8wnny2ohMr4Ms7RG+ 7jBZScUGkwCmRDo7szamrQf57vkZXQp1jNXpgfggNilHSQKkkMOwTdE90709Qd5mRZ FQ3VBA2qQc/uNWzmb7pdCUOw5ZKfrDNxhTGpkZGKNc1vvzUKs8E2sp8Uc+SDng66lP KcadRqtDyD1KCzGSb/MlMUrie25vPusI16qWbhd/PyTk944IwmbIZRCX/2mhKBt4IO dCZfW0aBmBvHA== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8C868C5AD49; Wed, 28 May 2025 14:45:51 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 28 May 2025 18:45:48 +0400 Subject: [PATCH v2 2/5] dt-bindings: net: qca,ar803x: Add IPQ5018 Internal GE PHY support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-ipq5018-ge-phy-v2-2-dd063674c71c@outlook.com> References: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> In-Reply-To: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748443549; l=3491; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=P7wjTTsDWLxWFS7rhrkYINOQIR4qqqVUnnCYcf/iIyE=; b=YDiV2+Np/ub7nIMfml1CMK3k00v32bjdZk0DkA+kEO4xd8+B98bc0gPkH4YDPmDwV0YLmK3rV 2+4k2SIyP5HCdVcmHkiGZyu/xNMB4FBXV3X08FuX579lCTpvfafeuL+ X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem Document the IPQ5018 Internal Gigabit Ethernet PHY found in the IPQ5018 SoC. Its output pins provide an MDI interface to either an external switch in a PHY to PHY link scenario or is directly attached to an RJ45 connector. The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and 802.3az EEE. For operation, the LDO controller found in the IPQ5018 SoC for which there is provision in the mdio-4019 driver. In addition, the PHY needs to take itself out of reset and enable the RX and TX clocks. Two common archictures across IPQ5018 boards are: 1. IPQ5018 PHY --> MDI --> RJ45 connector 2. IPQ5018 PHY --> MDI --> External PHY In a phy to phy architecture, DAC values need to be set to accommodate for the short cable length. As such, add an optional boolean property so the driver sets the correct register values for the DAC accordingly. Signed-off-by: George Moussalem --- .../devicetree/bindings/net/qca,ar803x.yaml | 52 ++++++++++++++++++= +++- 1 file changed, 51 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/qca,ar803x.yaml b/Docume= ntation/devicetree/bindings/net/qca,ar803x.yaml index 3acd09f0da863137f8a05e435a1fd28a536c2acd..de0c26f59babf0b7020d7a1d542= 29005822d5472 100644 --- a/Documentation/devicetree/bindings/net/qca,ar803x.yaml +++ b/Documentation/devicetree/bindings/net/qca,ar803x.yaml @@ -14,10 +14,41 @@ maintainers: description: | Bindings for Qualcomm Atheros AR803x PHYs =20 -allOf: +oneOf: - $ref: ethernet-phy.yaml# + - if: + properties: + compatible: + contains: + enum: + - ethernet-phy-id004d.d0c0 + + then: + properties: + reg: + const: 7 # This PHY is always at MDIO address 7 in the IPQ5018 = SoC + clocks: + items: + - description: RX clock + - description: TX clock + resets: + items: + - description: + GE PHY MISC reset which triggers a reset across MDC, DSP, = RX, and TX lines. + qcom,dac-preset-short-cable: + description: + Set if this phy is connected to another phy to adjust the valu= es for + MDAC and EDAC to adjust amplitude, bias current settings, and = error + detection and correction algorithm to accommodate for short ca= ble length. + If not set, it is assumed the MDI output pins of this PHY are = directly + connected to an RJ45 connector and default DAC values will be = used. + type: boolean =20 properties: + compatible: + enum: + - ethernet-phy-id004d.d0c0 + qca,clk-out-frequency: description: Clock output frequency in Hertz. $ref: /schemas/types.yaml#/definitions/uint32 @@ -132,3 +163,22 @@ examples: }; }; }; + - | + #include + #include + + mdio { + #address-cells =3D <1>; + #size-cells =3D <0>; + + /* add alias to set qcom,dac-preset-short-cable on boards that nee= d it */ + ge_phy: ethernet-phy@7 { + compatible =3D "ethernet-phy-id004d.d0c0"; + reg =3D <7>; + + clocks =3D <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + + resets =3D <&gcc GCC_GEPHY_MISC_ARES>; + }; + }; --=20 2.49.0 From nobody Wed Feb 11 02:33:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0EC1C1D5AB7; Wed, 28 May 2025 14:45:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; cv=none; b=X3qzW5MrHlOOex9leukBhUnh6fKCdRptErT+rL+UwdiOspURBdLM1vGs4MvMyt5KDkz2r6RtAzNCSg7JHxtysof13Gb9mQoSrd72p2pyFNo6F8dIYy7y4etGy6+KIqAWENmsjjv7wktpgtES2VsC7ZB1O2BEeofMTd3IJmxtCeg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; c=relaxed/simple; bh=8Ch1dMLWM2FHMpg8Uktr1Ihz4jf3cn7XYXwzpnTS05g=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=ukqkl5+SDfikuDkuMRhMDerDZHSjd6Las+InMsizizTCHwVbPWrga65Ehy0iSRSs3J77e46rPSqi9Vsub6m3+6lGIO3DMnLZBUAWbZyxjHZgoWNm4PgsOT6HtLTY1s2aKUdWSg1xRZcJFqWBNXgjovj8kJNdL+lfYO3TVBlKZE0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=aEvTFSCD; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="aEvTFSCD" Received: by smtp.kernel.org (Postfix) with ESMTPS id AB3D4C4CEF3; Wed, 28 May 2025 14:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748443551; bh=8Ch1dMLWM2FHMpg8Uktr1Ihz4jf3cn7XYXwzpnTS05g=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=aEvTFSCDqRESaYsKAztcHDOmlw2/cG4ml1Y0KTJQuz2EWQXa3lXN9gYhkZ+PR4PAi Z3obzOMJTkSgBOX4a+NbsfE3C6hf79XW5jRq50dFu0RE9vxWipI4bJaVIz4XmOwiI1 xTRG7+vW3oLWmCxnod1rgk7e6lgBSnBoQcaU1G39Ky9g+TEJVRsy0NhQnkYcWQ7Qc5 2V00icCz5m048OvAJYe2NqXRLcnxac3C0yJIPTd9GkAWD37jnC26ROI1v6FxhjKi/3 3m58WMAMLSolhvUEqsBxEn+ZcVH0UJwgMHGGFIwHytwYa9vZir6A71nlRfe1TLMB8y 72dGxHUeasqbQ== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id A1833C3ABB2; Wed, 28 May 2025 14:45:51 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 28 May 2025 18:45:49 +0400 Subject: [PATCH v2 3/5] net: phy: qcom: at803x: Add Qualcomm IPQ5018 Internal PHY support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-ipq5018-ge-phy-v2-3-dd063674c71c@outlook.com> References: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> In-Reply-To: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748443549; l=10400; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=0oys1TqFW/zfc7JfpiP4+i00oxFAKGo9oEkBTeSE9e4=; b=jhGPRmT8F4NYaZT07nF0hZ+cl5HGSbemUjkUIE/nkmYTr86iDol38heo1NxdNu0/r9h1QVDB/ KIIcw1uKnpYC6mqh4Cshlc8wSTp9U0nvQ0YBHhMxC+TjqofZhsaOCiR X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains a single internal Gigabit Ethernet PHY which provides an MDI interface directly to an RJ45 connector or an external switch over a PHY to PHY link. The PHY supports 10/100/1000 mbps link modes, CDT, auto-negotiation and 802.3az EEE. Let's add support for this PHY in the at803x driver as it falls within the Qualcomm Atheros OUI. Signed-off-by: George Moussalem --- drivers/net/phy/qcom/Kconfig | 2 +- drivers/net/phy/qcom/at803x.c | 197 ++++++++++++++++++++++++++++++++++++++= ++-- 2 files changed, 190 insertions(+), 9 deletions(-) diff --git a/drivers/net/phy/qcom/Kconfig b/drivers/net/phy/qcom/Kconfig index 570626cc8e14d3e6615f74a6377f0f7c9f723e89..84239e08a8dfa466b0a7b2a5ec7= 24a168b692cd2 100644 --- a/drivers/net/phy/qcom/Kconfig +++ b/drivers/net/phy/qcom/Kconfig @@ -7,7 +7,7 @@ config AT803X_PHY select QCOM_NET_PHYLIB depends on REGULATOR help - Currently supports the AR8030, AR8031, AR8033, AR8035 model + Currently supports the AR8030, AR8031, AR8033, AR8035, IPQ5018 model =20 config QCA83XX_PHY tristate "Qualcomm Atheros QCA833x PHYs" diff --git a/drivers/net/phy/qcom/at803x.c b/drivers/net/phy/qcom/at803x.c index 26350b962890b0321153d74758b13d817407d094..1dc3ce7d1299de9725684f79230= 8ba65ea47f90a 100644 --- a/drivers/net/phy/qcom/at803x.c +++ b/drivers/net/phy/qcom/at803x.c @@ -7,19 +7,24 @@ * Author: Matus Ujhelyi */ =20 -#include -#include -#include -#include +#include +#include +#include #include #include -#include -#include -#include -#include +#include +#include +#include #include +#include #include +#include +#include +#include +#include +#include #include +#include #include =20 #include "qcom.h" @@ -96,6 +101,8 @@ #define ATH8035_PHY_ID 0x004dd072 #define AT8030_PHY_ID_MASK 0xffffffef =20 +#define IPQ5018_PHY_ID 0x004dd0c0 + #define QCA9561_PHY_ID 0x004dd042 =20 #define AT803X_PAGE_FIBER 0 @@ -108,6 +115,50 @@ /* disable hibernation mode */ #define AT803X_DISABLE_HIBERNATION_MODE BIT(2) =20 +#define IPQ5018_PHY_FIFO_CONTROL 0x19 +#define IPQ5018_PHY_FIFO_RESET GENMASK(1, 0) + +#define IPQ5018_PHY_DEBUG_EDAC 0x4380 +#define IPQ5018_PHY_MMD1_MDAC 0x8100 +#define IPQ5018_PHY_DAC_MASK GENMASK(15, 8) + +/* MDAC and EDAC values for short cable length */ +#define IPQ5018_PHY_DEBUG_EDAC_VAL 0x10 +#define IPQ5018_PHY_MMD1_MDAC_VAL 0x10 + +#define IPQ5018_PHY_MMD1_MSE_THRESH1 0x1000 +#define IPQ5018_PHY_MMD1_MSE_THRESH2 0x1001 +#define IPQ5018_PHY_PCS_AZ_CTRL1 0x8008 +#define IPQ5018_PHY_PCS_AZ_CTRL2 0x8009 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3 0x8074 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4 0x8075 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5 0x8076 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6 0x8077 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7 0x8078 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9 0x807a +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13 0x807e +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL14 0x807f + +#define IPQ5018_PHY_MMD1_MSE_THRESH1_VAL 0xf1 +#define IPQ5018_PHY_MMD1_MSE_THRESH2_VAL 0x1f6 +#define IPQ5018_PHY_PCS_AZ_CTRL1_VAL 0x7880 +#define IPQ5018_PHY_PCS_AZ_CTRL2_VAL 0xc8 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL 0xc040 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL 0xa060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL 0xc040 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL 0xa060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL 0xc24c +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL 0xc060 +#define IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL 0xb060 +#define IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL 0x90b0 + +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE 0x1 +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK GENMASK(7, 4) +#define IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT 0x50 +#define IPQ5018_PHY_DEBUG_ANA_DAC_FILTER 0xa080 + +#define IPQ5018_TCSR_ETH_LDO_READY BIT(0) + MODULE_DESCRIPTION("Qualcomm Atheros AR803x PHY driver"); MODULE_AUTHOR("Matus Ujhelyi"); MODULE_LICENSE("GPL"); @@ -133,6 +184,13 @@ struct at803x_context { u16 led_control; }; =20 +struct ipq5018_priv { + int num_clks; + struct clk_bulk_data *clks; + struct reset_control *rst; + bool set_short_cable_dac; +}; + static int at803x_write_page(struct phy_device *phydev, int page) { int mask; @@ -987,6 +1045,115 @@ static int at8035_probe(struct phy_device *phydev) return at8035_parse_dt(phydev); } =20 +static int ipq5018_cable_test_start(struct phy_device *phydev) +{ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL3_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL4, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL4_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL5, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL5_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL6, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL6_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL7, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL7_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL9, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL9_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL13, + IPQ5018_PHY_PCS_CDT_THRESH_CTRL13_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_CDT_THRESH_CTRL3, + IPQ5018_PHY_PCS_NEAR_ECHO_THRESH_VAL); + + /* we do all the (time consuming) work later */ + return 0; +} + +static int ipq5018_config_init(struct phy_device *phydev) +{ + struct ipq5018_priv *priv =3D phydev->priv; + u16 val =3D 0; + + /* + * set LDO efuse: first temporarily store ANA_DAC_FILTER value from + * debug register as it will be reset once the ANA_LDO_EFUSE register + * is written to + */ + val =3D at803x_debug_reg_read(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER); + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_MASK, + IPQ5018_PHY_DEBUG_ANA_LDO_EFUSE_DEFAULT); + at803x_debug_reg_write(phydev, IPQ5018_PHY_DEBUG_ANA_DAC_FILTER, val); + + /* set 8023AZ CTRL values */ + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL1, + IPQ5018_PHY_PCS_AZ_CTRL1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PCS, IPQ5018_PHY_PCS_AZ_CTRL2, + IPQ5018_PHY_PCS_AZ_CTRL2_VAL); + + /* set MSE threshold values */ + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH1, + IPQ5018_PHY_MMD1_MSE_THRESH1_VAL); + phy_write_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MSE_THRESH2, + IPQ5018_PHY_MMD1_MSE_THRESH2_VAL); + + /* PHY DAC values are optional and only set in a PHY to PHY link architec= ture */ + if (priv->set_short_cable_dac) { + /* setting MDAC (Multi-level Digital-to-Analog Converter) in MMD1 */ + phy_modify_mmd(phydev, MDIO_MMD_PMAPMD, IPQ5018_PHY_MMD1_MDAC, + IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_MMD1_MDAC_VAL); + + /* setting EDAC (Error-detection and Correction) in debug register */ + at803x_debug_reg_mask(phydev, IPQ5018_PHY_DEBUG_EDAC, + IPQ5018_PHY_DAC_MASK, IPQ5018_PHY_DEBUG_EDAC_VAL); + } + + return 0; +} + +static void ipq5018_link_change_notify(struct phy_device *phydev) +{ + mdiobus_modify_changed(phydev->mdio.bus, phydev->mdio.addr, + IPQ5018_PHY_FIFO_CONTROL, IPQ5018_PHY_FIFO_RESET, + phydev->link ? IPQ5018_PHY_FIFO_RESET : 0); +} + +static int ipq5018_probe(struct phy_device *phydev) +{ + struct device *dev =3D &phydev->mdio.dev; + struct ipq5018_priv *priv; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->set_short_cable_dac =3D of_property_read_bool(dev->of_node, + "qcom,dac-preset-short-cable"); + + priv->num_clks =3D devm_clk_bulk_get_all(dev, &priv->clks); + if (priv->num_clks < 0) + return dev_err_probe(dev, priv->num_clks, + "failed to acquire clocks\n"); + + ret =3D clk_bulk_prepare_enable(priv->num_clks, priv->clks); + if (ret) + return dev_err_probe(dev, ret, + "failed to enable clocks\n"); + + priv->rst =3D devm_reset_control_array_get_exclusive(dev); + if (IS_ERR_OR_NULL(priv->rst)) + return dev_err_probe(dev, PTR_ERR(priv->rst), + "failed to acquire reset\n"); + + ret =3D reset_control_reset(priv->rst); + if (ret) + return dev_err_probe(dev, ret, "failed to reset\n"); + + phydev->priv =3D priv; + + return 0; +} + static struct phy_driver at803x_driver[] =3D { { /* Qualcomm Atheros AR8035 */ @@ -1078,6 +1245,19 @@ static struct phy_driver at803x_driver[] =3D { .read_status =3D at803x_read_status, .soft_reset =3D genphy_soft_reset, .config_aneg =3D at803x_config_aneg, +}, { + PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID), + .name =3D "Qualcomm Atheros IPQ5018 internal PHY", + .flags =3D PHY_IS_INTERNAL | PHY_POLL_CABLE_TEST, + .probe =3D ipq5018_probe, + .config_init =3D ipq5018_config_init, + .link_change_notify =3D ipq5018_link_change_notify, + .read_status =3D at803x_read_status, + .config_intr =3D at803x_config_intr, + .handle_interrupt =3D at803x_handle_interrupt, + .cable_test_start =3D ipq5018_cable_test_start, + .cable_test_get_status =3D qca808x_cable_test_get_status, + .soft_reset =3D genphy_soft_reset, }, { /* Qualcomm Atheros QCA9561 */ PHY_ID_MATCH_EXACT(QCA9561_PHY_ID), @@ -1104,6 +1284,7 @@ static const struct mdio_device_id __maybe_unused ath= eros_tbl[] =3D { { PHY_ID_MATCH_EXACT(ATH8032_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH8035_PHY_ID) }, { PHY_ID_MATCH_EXACT(ATH9331_PHY_ID) }, + { PHY_ID_MATCH_EXACT(IPQ5018_PHY_ID) }, { PHY_ID_MATCH_EXACT(QCA9561_PHY_ID) }, { } }; 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Wed, 28 May 2025 14:45:51 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 28 May 2025 18:45:50 +0400 Subject: [PATCH v2 4/5] arm64: dts: qcom: ipq5018: Add MDIO buses Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-ipq5018-ge-phy-v2-4-dd063674c71c@outlook.com> References: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> In-Reply-To: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748443549; l=1458; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=4Z6dvq+B+YexBDa/RxyvWcr+v3oZkqxqlrrl5K8MHDY=; b=EAjnILhijNnzbfArUiedgXalZcEkkjwbe2NfRJ9PsDO1Uh6HkD4hyOBGO5iexkzcoPH3C0kAP 4dZ96UtYzZsDJk4OEOxCmSQwZPvB4ZFrDLL+W1eMkObatV7IIe8vOoV X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem IPQ5018 contains two mdio buses of which one bus is used to control the SoC's internal GE PHY, while the other bus is connected to external PHYs or switches. There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's simply add the mdio nodes for them. Signed-off-by: George Moussalem Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 130360014c5e14c778e348d37e601f60325b0b14..03ebc3e305b267c98a034c41ce4= 7a39269afce75 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -182,6 +182,30 @@ pcie0_phy: phy@86000 { status =3D "disabled"; }; =20 + mdio0: mdio@88000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00088000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO0_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + + mdio1: mdio@90000 { + compatible =3D "qcom,ipq5018-mdio"; + reg =3D <0x00090000 0x64>; + #address-cells =3D <1>; + #size-cells =3D <0>; + + clocks =3D <&gcc GCC_MDIO1_AHB_CLK>; + clock-names =3D "gcc_mdio_ahb_clk"; + + status =3D "disabled"; + }; + tlmm: pinctrl@1000000 { compatible =3D "qcom,ipq5018-tlmm"; reg =3D <0x01000000 0x300000>; --=20 2.49.0 From nobody Wed Feb 11 02:33:13 2026 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 44FC728B419; Wed, 28 May 2025 14:45:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; cv=none; b=saULwrNKzQQJk4UWpQxD3CrmirwOi00l44i12xjeddd8/4Q/5fln5d6RbF3bsyIlCeBYGWi42AFHR2Owbxj3neVQMr6C7XqTgU776IzjICfVa/faa41RSnMK36RgzF3QhNEwgpJp6zo7LNIb8ICwiz5xpBVcZauUBwaZcpbrP5I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748443552; c=relaxed/simple; bh=fY+l6Ps6NFjPp8H1FTNbFmkXe5TI6m53tpp5kLmq6ks=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=I96Y0IdtRVUycnvEUWFO+eTk7PuwqZe41RduFCFVojT4I9ykRTEorYTLS9jsxj3xdI65BuihmoyzVICND3SM2e+h89ESSs05ePvldqq0Zlkzwc/+8GDWSYf3rZxMErighWSpg1UM/Ni0AvzufOCoZs3GnYCXxtX8Mf6lovozCaA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=bu3Ddp2k; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="bu3Ddp2k" Received: by smtp.kernel.org (Postfix) with ESMTPS id C9514C4CEEF; Wed, 28 May 2025 14:45:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748443551; bh=fY+l6Ps6NFjPp8H1FTNbFmkXe5TI6m53tpp5kLmq6ks=; h=From:Date:Subject:References:In-Reply-To:To:Cc:Reply-To:From; b=bu3Ddp2ka9q5DyNFUz9Mr98I1vQjHBAMtfVqGyF929IZjna3PpCXfPW/VwbNJ0qRZ C46gIGhwpc/Ow5CzMuvFlM+wEH+hEXZfU5bl5Z+aKTUKNEH29R4gwUvciW0fezeVsi J5+pe4Q2PcMoL/XQstlE/1NnstuLUxDfgRFrTxaOCk41tdQV5+5owQo/z/Gz3sUEn2 2A477zqYoxACEfzzRAeKnwVJYOcmecknZ12dIMbqYrUD/RTvSMeH9t+b0wrZBNUdMg iw5L5cSItk/hbHofdgkK7BzB/8YU9oBos930OF2MG1ITz/upkw3m/M4e9iiw8Tgwvg wxarXmu2prKvg== Received: from aws-us-west-2-korg-lkml-1.web.codeaurora.org (localhost.localdomain [127.0.0.1]) by smtp.lore.kernel.org (Postfix) with ESMTP id BF04BC5B552; Wed, 28 May 2025 14:45:51 +0000 (UTC) From: George Moussalem via B4 Relay Date: Wed, 28 May 2025 18:45:51 +0400 Subject: [PATCH v2 5/5] arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-ipq5018-ge-phy-v2-5-dd063674c71c@outlook.com> References: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> In-Reply-To: <20250528-ipq5018-ge-phy-v2-0-dd063674c71c@outlook.com> To: Andrew Lunn , Heiner Kallweit , Russell King , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Florian Fainelli , Philipp Zabel , Bjorn Andersson , Konrad Dybcio , Michael Turquette , Stephen Boyd Cc: netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, George Moussalem X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748443549; l=2303; i=george.moussalem@outlook.com; s=20250321; h=from:subject:message-id; bh=y1umjiNASV+etOSubDvR4l343800ONATOPkAQu4T8kA=; b=kcj8aIQFIt/fW5UDnVZlEfilk6D5Bz84KOgRmYFPp4kkSwV9MLqq/D9RGVOla8XY9WTcrI+uB EYMY9578cqCBb8V/l36iuGVB4YIVhdxWUZunRRJr1jwWxv0USERltjR X-Developer-Key: i=george.moussalem@outlook.com; a=ed25519; pk=/PuRTSI9iYiHwcc6Nrde8qF4ZDhJBlUgpHdhsIjnqIk= X-Endpoint-Received: by B4 Relay for george.moussalem@outlook.com/20250321 with auth_id=364 X-Original-From: George Moussalem Reply-To: george.moussalem@outlook.com From: George Moussalem The IPQ5018 SoC contains an internal GE PHY, always at phy address 7. As such, let's add the GE PHY node to the SoC dtsi. The LDO controller found in the SoC must be enabled to provide constant low voltages to the PHY. The mdio-ipq4019 driver already has support for this, so adding the appropriate TCSR register offset. In addition, the GE PHY outputs both the RX and TX clocks to the GCC which gate controls them and routes them back to the PHY itself. So let's create two DT fixed clocks and register them in the GCC node. Signed-off-by: George Moussalem --- arch/arm64/boot/dts/qcom/ipq5018.dtsi | 29 ++++++++++++++++++++++++++--- 1 file changed, 26 insertions(+), 3 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/ipq5018.dtsi b/arch/arm64/boot/dts/qc= om/ipq5018.dtsi index 03ebc3e305b267c98a034c41ce47a39269afce75..6c42ed826c3c60960b08afb0b32= 4cfb89f02329d 100644 --- a/arch/arm64/boot/dts/qcom/ipq5018.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5018.dtsi @@ -16,6 +16,18 @@ / { #size-cells =3D <2>; =20 clocks { + gephy_rx_clk: gephy-rx-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + + gephy_tx_clk: gephy-tx-clk { + compatible =3D "fixed-clock"; + clock-frequency =3D <125000000>; + #clock-cells =3D <0>; + }; + sleep_clk: sleep-clk { compatible =3D "fixed-clock"; #clock-cells =3D <0>; @@ -184,7 +196,8 @@ pcie0_phy: phy@86000 { =20 mdio0: mdio@88000 { compatible =3D "qcom,ipq5018-mdio"; - reg =3D <0x00088000 0x64>; + reg =3D <0x00088000 0x64>, + <0x019475c4 0x4>; #address-cells =3D <1>; #size-cells =3D <0>; =20 @@ -192,6 +205,16 @@ mdio0: mdio@88000 { clock-names =3D "gcc_mdio_ahb_clk"; =20 status =3D "disabled"; + + ge_phy: ethernet-phy@7 { + compatible =3D "ethernet-phy-id004d.d0c0"; + reg =3D <7>; + + clocks =3D <&gcc GCC_GEPHY_RX_CLK>, + <&gcc GCC_GEPHY_TX_CLK>; + + resets =3D <&gcc GCC_GEPHY_MISC_ARES>; + }; }; =20 mdio1: mdio@90000 { @@ -232,8 +255,8 @@ gcc: clock-controller@1800000 { <&pcie0_phy>, <&pcie1_phy>, <0>, - <0>, - <0>, + <&gephy_rx_clk>, + <&gephy_tx_clk>, <0>, <0>; #clock-cells =3D <1>; --=20 2.49.0