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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:09 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:47 -0400 Subject: [PATCH v2 01/10] clk: add kernel docs for struct clk_core Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-1-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=3224; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=ccvc0hhbSgWY4GmJLHg7B4WAjq9gbICcuSkXsBTsGy4=; b=4HFuNr0KN0TtNnsFn27cZXoLo5n0gd64dH6POJAJfBz7XiuZ12lSLLq1YQ6SyLrA+ClPNKZx8 bhTJNhT2gFHDcGi6pn/jMhdHIoyxPccAjyxy1iaYYwFoOuJu/KoBi6X X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Document all of the members of struct clk_core. Signed-off-by: Brian Masney --- drivers/clk/clk.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 42 insertions(+) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index 0565c87656cf5c557d8259c71b5d2971a7ac87e8..a130eac9072dc7e71f840a0edf5= 1c368650f8386 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -57,6 +57,48 @@ struct clk_parent_map { int index; }; =20 +/** + * struct clk_core - This structure represents the internal state of a clk + * within the kernel's clock tree. Drivers do not interact with this struc= ture + * directly. The clk_core is manipulated by the framework to manage clock + * operations, parent/child relationships, rate, and other properties. + * + * @name: Unique name of the clk for identification. + * @ops: Pointer to hardware-specific operations for this cl= k. + * @hw: Pointer for traversing from a struct clk to its + * corresponding hardware-specific structure. + * @owner: Kernel module owning this clk (for reference counti= ng). + * @dev: Device associated with this clk (optional) + * @rpm_node: Node for runtime power management list management. + * @of_node: Device tree node associated with this clk (if appli= cable) + * @parent: Pointer to the current parent in the clock tree. + * @parents: Array of possible parents (for muxes/selectable par= ents). + * @num_parents: Number of possible parents + * @new_parent_index: Index of the new parent during parent change. + * @rate: Current clock rate (Hz). + * @req_rate: Requested clock rate (Hz). + * @new_rate: New rate to be set during a rate change operation. + * @new_parent: Pointer to new parent during parent change. + * @new_child: Pointer to new child during reparenting. + * @flags: Clock property and capability flags. + * @orphan: True if this clk is currently orphaned. + * @rpm_enabled: True if runtime power management is enabled for thi= s clk. + * @enable_count: Reference count of enables. + * @prepare_count: Reference count of prepares. + * @protect_count: Protection reference count against disable. + * @min_rate: Minimum supported clock rate (Hz). + * @max_rate: Maximum supported clock rate (Hz). + * @accuracy: Accuracy of the clock rate (Hz). + * @phase: Current phase (degrees or hardware-specific units). + * @duty: Current duty cycle configuration. + * @children: All of the children of this clk. + * @child_node: Node for linking as a child in the parent's list. + * @clks: All of the clk consumers registered. + * @notifier_count: Number of notifiers registered for this clk. + * @dentry: DebugFS entry for this clk. + * @debug_node: DebugFS node for this clk. + * @ref: Reference count for structure lifetime management. + */ struct clk_core { const char *name; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:12 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:48 -0400 Subject: [PATCH v2 02/10] clk: preserve original rate when a sibling clk changes it's rate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-2-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=5847; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=qHWMuJJeiaFRL42fA+VeDuXKnBkY09NzfffNrn6wjts=; b=daDGbjkH/b8bKqTXSFLxxEbRD/FCqFx5/x05oK7AinkKtA4WnzIRIsMAbCX5yyHOyPJZ3sqBo MK+gGq2PoMpB1u41iY8wDiJa78wIH7T5+p2tZC3f7D2cPC6g4/W+Kye X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= There are times when the requested rate on a clk cannot be fulfilled due to the current rate of the parent clk. If CLK_SET_RATE_PARENT is set, then the parent rate will be adjusted so that the child can obtain the requested rate. When the parent rate is adjusted, there's currently an issue where the rates of the other children are unnecessarily changed. Let's take the following simplified clk tree as an example: parent 24 MHz / \ child1 child2 24 MHz 24 MHz The child1 and child2 clks are simple divider clocks in this example, and it doesn't really matter what kind of clk parent is; for simplicity we can say that the parent can obtain any rate necessary. Now, let's update the value of child2 with the existing clk code: - child2 requests 48 MHz. This is incompatible the current parent rate of 24 MHz. - parent is updated to 48 MHz so that child2 can obtain the requested rate of 48 MHz by using a divider of 0. - child1 should stay at 24 MHz, and the divider should be automatically changed from 0 to 1. The current bug in the code sets the rate of child1 to 48 MHz by calling the clk_op's recalc_rate() with only the new parent rate, which keeps the clk's divider at 0. Specifically this example occurs in this part of the call tree: clk_core_set_rate_nolock(child2, 48_MHZ) -> clk_calc_new_rates(child2, 48_MHZ) # clk has CLK_SET_RATE_PARENT set, so clk_calc_new_rates() is invoked # via the following block: # if ((core->flags & CLK_SET_RATE_PARENT) && parent && # best_parent_rate !=3D parent->rate) # top =3D clk_calc_new_rates(parent, best_parent_rate); -> clk_calc_new_rates(parent, 48_MHZ) -> clk_calc_subtree(parent, 48_MHZ, ...) -> clk_recalc(child1, 48_MHZ) # BOOM! This is where the bug occurs. This invokes the # clk_op's recalc_rate() with the new parent rate of 48 MHz, # and the original divider of 0 is kept intact, so child1's # rate is changed from 24 MHz to 48 MHz by the clk core. When the clk core requests rate changes, the struct clk_core contains a new_rate field that contains the rate that the clk is changed to by clk_change_rate(). When a parent changes it's rate, only ensure that the section of the clk tree where the rate change request propagated up is changed. All other sibling nodes should try to keep the same rate (or close to it) that was previously set. We avoid this by not initially calling the clk_op's recalc_rate() for parts of the subtree that haven't been modified. Once the new_rate fields are populated with the correct values, eventually clk_change_rate() is called on the parent, and the parent will invoke clk_change_rate() for all of the children with the expected rates stored in the new_rate fields. This will invoke the clk_op's set_rate() on each of the children. This doesn't fix all of the issues where a clk can unknowingly change the rate of it's siblings, or put them in an invalid state, however this is a relatively small change that can fix some issues. A correct change that includes coordination with the other children in the subtree, and works across the various types of clks will involve a much more elaborate patch set. This change was tested with kunit tests, and also boot tested on a Lenovo Thinkpad x13s laptop. Fixes: b2476490ef11 ("clk: introduce the common clock framework") Signed-off-by: Brian Masney --- drivers/clk/clk.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/clk/clk.c b/drivers/clk/clk.c index a130eac9072dc7e71f840a0edf51c368650f8386..65408899a4ae8674e78494d77ff= 07fa658f7d3b0 100644 --- a/drivers/clk/clk.c +++ b/drivers/clk/clk.c @@ -78,6 +78,10 @@ struct clk_parent_map { * @rate: Current clock rate (Hz). * @req_rate: Requested clock rate (Hz). * @new_rate: New rate to be set during a rate change operation. + * @rate_directly_changed: Clocks have the ability to change the rate of i= t's + * parent in order to satisfy a rate change request. T= his + * flag indicates that the rate change request initiat= ed + * with this particular node. * @new_parent: Pointer to new parent during parent change. * @new_child: Pointer to new child during reparenting. * @flags: Clock property and capability flags. @@ -114,6 +118,7 @@ struct clk_core { unsigned long rate; unsigned long req_rate; unsigned long new_rate; + bool rate_directly_changed; struct clk_core *new_parent; struct clk_core *new_child; unsigned long flags; @@ -2306,7 +2311,11 @@ static void clk_calc_subtree(struct clk_core *core, = unsigned long new_rate, new_parent->new_child =3D core; =20 hlist_for_each_entry(child, &core->children, child_node) { - child->new_rate =3D clk_recalc(child, new_rate); + if (child->rate_directly_changed) + child->new_rate =3D clk_recalc(child, new_rate); + else + child->new_rate =3D child->rate; + clk_calc_subtree(child, child->new_rate, NULL, 0); } } @@ -2579,6 +2588,8 @@ static int clk_core_set_rate_nolock(struct clk_core *= core, if (clk_core_rate_is_protected(core)) return -EBUSY; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:14 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:49 -0400 Subject: [PATCH v2 03/10] clk: test: introduce a few specific rate constants for mock testing Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-3-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=996; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=XVNjQfh5u92+SvTEjJh8Vit7Er7I1Kh2/fKNBT5Mpa4=; b=oV+qwanIV17f+J9/DX6p4OuJe3bZHqW52YxbG0IgOyqpnclOSVy3avicQYBUBUGeO4QPJfXL8 fV4UGR716N4BgJ4XutJRDCF91WKbsfUwWW3h15RWnLPGj9FnIBLMk/B X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Some of the mock tests care about the relationship between two different rates, and the specific numbers are important, such as for mocking a divider. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index f08feeaa3750bc86859294650de298762dea690a..1b34d54ec9c610ffa3e91b06f5a= 5180e0395e26f 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -24,6 +24,10 @@ static const struct clk_ops empty_clk_ops =3D { }; #define DUMMY_CLOCK_INIT_RATE (42 * 1000 * 1000) #define DUMMY_CLOCK_RATE_1 (142 * 1000 * 1000) #define DUMMY_CLOCK_RATE_2 (242 * 1000 * 1000) +#define DUMMY_CLOCK_RATE_6_MHZ (6 * 1000 * 1000) +#define DUMMY_CLOCK_RATE_16_MHZ (16 * 1000 * 1000) +#define DUMMY_CLOCK_RATE_24_MHZ (24 * 1000 * 1000) +#define DUMMY_CLOCK_RATE_48_MHZ (48 * 1000 * 1000) =20 struct clk_dummy_context { struct clk_hw hw; --=20 2.49.0 From nobody Tue Dec 16 14:49:53 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 30D177F7FC for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:16 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:50 -0400 Subject: [PATCH v2 04/10] clk: test: introduce clk_dummy_div for a mock divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-4-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=1920; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=NMZgKVeLZ9BZ3EE3JsxTf6VRGRDkv/GJpoUMl51QAYU=; b=7U3GXBVbw3VpE22HalTtWkfkALmHE40v5SBTBw0dk1ipNXxawmTZsR9pCL6LvFDd6hYFh0Dmf f02/OZZLs4VBd0plkjqo/QAKFk+Hf3I9vF4QvoRCRaTlSsczLvHnoGw X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= This is used to mock up a divider in the clk kunit tests. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 41 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 1b34d54ec9c610ffa3e91b06f5a5180e0395e26f..4908fb9c0c46e34063ecf696e49= b48510da44538 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -140,6 +140,47 @@ static const struct clk_ops clk_dummy_single_parent_op= s =3D { .get_parent =3D clk_dummy_single_get_parent, }; =20 +// 4 ought to be enough for anybody +#define CLK_DUMMY_DIV_WIDTH 4 + +struct clk_dummy_div { + struct clk_hw hw; + unsigned int div; +}; + +static unsigned long clk_dummy_div_recalc_rate(struct clk_hw *hw, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + return divider_recalc_rate(hw, parent_rate, div->div, NULL, + CLK_DIVIDER_ROUND_CLOSEST, CLK_DUMMY_DIV_WIDTH); +} + +static long clk_dummy_div_round_rate(struct clk_hw *hw, unsigned long rate, + unsigned long *parent_rate) +{ + return divider_round_rate(hw, rate, parent_rate, NULL, + CLK_DUMMY_DIV_WIDTH, CLK_DIVIDER_ROUND_CLOSEST); +} + +static int clk_dummy_div_set_rate(struct clk_hw *hw, unsigned long rate, + unsigned long parent_rate) +{ + struct clk_dummy_div *div =3D container_of(hw, struct clk_dummy_div, hw); + + div->div =3D divider_get_val(rate, parent_rate, NULL, CLK_DUMMY_DIV_WIDTH, + CLK_DIVIDER_ROUND_CLOSEST); + + return 0; +} + +static const struct clk_ops clk_dummy_div_ops =3D { + .recalc_rate =3D clk_dummy_div_recalc_rate, + .round_rate =3D clk_dummy_div_round_rate, + .set_rate =3D clk_dummy_div_set_rate, +}; + struct clk_multiple_parent_ctx { struct clk_dummy_context parents_ctx[2]; struct clk_hw hw; --=20 2.49.0 From nobody Tue Dec 16 14:49:53 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D6B157F7FC for ; Wed, 28 May 2025 23:17:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:18 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:51 -0400 Subject: [PATCH v2 05/10] clk: test: introduce test suite for sibling rate changes on a divider Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-5-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=6278; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=IGEeR6GetpJ5C1jEWi5w6/QO0GccDmMEscoH2i9wX9o=; b=wz7OjZHAO1SRXStjvpw6TOd8nv7KQP7thAXi6sg6OB60ne0EEWbJghfSwYCkBwP2fyTfSNL03 lG8HK4lbStRBLcmDcC8u7Z1uB/tcA6ES5Or+h5wqLCXCxjM0vuAt2en X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test suite that creates a parent with two divider-only children, and ensure that changing the rate of one child does not affect the rate of the sibling. Some of the tests are disabled until the relevant issue(s) are fixed in the clk core. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 139 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 139 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 4908fb9c0c46e34063ecf696e49b48510da44538..35f516fd71a2e33ca19a0512bd2= db02111ea644c 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -653,6 +653,144 @@ clk_multiple_parents_mux_test_suite =3D { .test_cases =3D clk_multiple_parents_mux_test_cases, }; =20 +struct clk_rate_change_sibling_div_div_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1, child2; + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +static int clk_rate_change_sibling_div_div_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D DUMMY_CLOCK_RATE_24_MHZ; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + if (ret) + return ret; + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, + &clk_dummy_div_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ret; + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, + &clk_dummy_div_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + if (ret) + return ret; + + ctx->parent_clk =3D clk_hw_get_clk(&ctx->parent.hw, NULL); + ctx->child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->child2_clk =3D clk_hw_get_clk(&ctx->child2.hw, NULL); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_24_= MHZ); + + return 0; +} + +static void clk_rate_change_sibling_div_div_test_exit(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + + clk_put(ctx->parent_clk); + clk_put(ctx->child1_clk); + clk_put(ctx->child2_clk); +} + +/* + * Test that, for a parent with two divider-only children and one requests= a + * rate compatible with the existing parent rate, the parent and sibling r= ates + * are not affected. + */ +static void clk_test_rate_change_sibling_div_div_1(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, DUMMY_CLOCK_RATE_6_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_24_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), DUMMY_CLOCK_RATE_6_M= HZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); +} + +/* + * Test that, for a parent with two divider-only children and one requests= a + * rate incompatible with the existing parent rate, the sibling rate is not + * affected. + */ +static void clk_test_rate_change_sibling_div_div_2(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + ret =3D clk_set_rate(ctx->child1_clk, DUMMY_CLOCK_RATE_48_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_GE(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_48_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), DUMMY_CLOCK_RATE_48_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); +} + +/* + * Test that, for a parent with two divider-only children that request rat= es + * incompatible with the existing parent rate, both children end up with t= he + * requested rates. The internal divider for child1 will be changed from 0= to 2. + */ +static void clk_test_rate_change_sibling_div_div_3(struct kunit *test) +{ + struct clk_rate_change_sibling_div_div_context *ctx =3D test->priv; + int ret; + + /* Validate initial child rates and divider states. */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), DUMMY_CLOCK_RATE_24_= MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 0); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 0); + + ret =3D clk_set_rate(ctx->child1_clk, DUMMY_CLOCK_RATE_16_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + ret =3D clk_set_rate(ctx->child2_clk, DUMMY_CLOCK_RATE_48_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_GE(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_48_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), DUMMY_CLOCK_RATE_16_= MHZ); + KUNIT_EXPECT_EQ(test, ctx->child1.div, 2); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_48_= MHZ); + KUNIT_EXPECT_EQ(test, ctx->child2.div, 0); +} + +static struct kunit_case clk_rate_change_sibling_div_div_cases[] =3D { + KUNIT_CASE(clk_test_rate_change_sibling_div_div_1), + KUNIT_CASE(clk_test_rate_change_sibling_div_div_2), + KUNIT_CASE(clk_test_rate_change_sibling_div_div_3), + {} +}; + +/* + * Test suite that creates a parent with two divider-only children, and + * ensures that changing the rate of one child does not affect the rate + * of the other child. + */ +static struct kunit_suite clk_rate_change_sibling_div_div_test_suite =3D { + .name =3D "clk-rate-change-sibling-div-div", + .init =3D clk_rate_change_sibling_div_div_test_init, + .exit =3D clk_rate_change_sibling_div_div_test_exit, + .test_cases =3D clk_rate_change_sibling_div_div_cases, +}; + static int clk_orphan_transparent_multiple_parent_mux_test_init(struct kunit *test) { @@ -3445,6 +3583,7 @@ kunit_test_suites( &clk_leaf_mux_set_rate_parent_test_suite, &clk_test_suite, &clk_multiple_parents_mux_test_suite, + &clk_rate_change_sibling_div_div_test_suite, &clk_mux_no_reparent_test_suite, &clk_mux_notifier_test_suite, &clk_orphan_transparent_multiple_parent_mux_test_suite, --=20 2.49.0 From nobody Tue Dec 16 14:49:53 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E9AE9224249 for ; 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Signed-off-by: Brian Masney Reviewed-by: Maxime Ripard --- drivers/clk/clk_test.c | 34 ++++++++++++++++++++++++++++++++++ 1 file changed, 34 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 35f516fd71a2e33ca19a0512bd2db02111ea644c..c2337527873d3241e7b0a38f67e= caa13535bcc71 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -181,6 +181,40 @@ static const struct clk_ops clk_dummy_div_ops =3D { .set_rate =3D clk_dummy_div_set_rate, }; =20 +struct clk_dummy_gate { + struct clk_hw hw; + bool enabled; +}; + +static int clk_dummy_gate_enable(struct clk_hw *hw) +{ + struct clk_dummy_gate *gate =3D container_of(hw, struct clk_dummy_gate, h= w); + + gate->enabled =3D true; + + return 0; +} + +static void clk_dummy_gate_disable(struct clk_hw *hw) +{ + struct clk_dummy_gate *gate =3D container_of(hw, struct clk_dummy_gate, h= w); + + gate->enabled =3D false; +} + +static int clk_dummy_gate_is_enabled(struct clk_hw *hw) +{ + struct clk_dummy_gate *gate =3D container_of(hw, struct clk_dummy_gate, h= w); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:24 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:53 -0400 Subject: [PATCH v2 07/10] clk: test: introduce test suite for sibling rate changes on a gate Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-7-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=6771; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=kG6u7fMzlYNawhtWbFLh1LXdL8BTH4EkRE0c5G3ajEc=; b=TZ4NRb1XDMzb9R3HAchwwsRpCugASlGuEDjkadlx5srrW+6TSU+QGvVVbsc7OwSwzVUTP6J7+ I5z6gm5wj0mDjFpB+5PKfBJAYF2ZnhNkWWBmX57KC8fGAKvytGskjfD X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test suite that creates a parent with two children: a divider and a gate. Ensure that changing the rate of one child does not affect the rate of the gate. Some of the tests are disabled until the relevant issue(s) are fixed in the clk core. This is also implemented as a parameterized kunit test since additional test variations will be added. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 156 +++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 156 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index c2337527873d3241e7b0a38f67ecaa13535bcc71..1440eb3c41def8c549f92c0e95b= 2a472f3bdb4a7 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -825,6 +825,161 @@ static struct kunit_suite clk_rate_change_sibling_div= _div_test_suite =3D { .test_cases =3D clk_rate_change_sibling_div_div_cases, }; =20 +struct clk_test_rate_change_sibling_clk_ctx { + struct clk *parent_clk, *child1_clk, *child2_clk; +}; + +static void +clk_test_rate_change_sibling_clk_ctx_put(struct clk_test_rate_change_sibli= ng_clk_ctx *clk_ctx) +{ + clk_put(clk_ctx->parent_clk); + clk_put(clk_ctx->child1_clk); + clk_put(clk_ctx->child2_clk); +} + +struct clk_rate_change_sibling_div_gate_sibling_context { + struct clk_dummy_context parent; + struct clk_dummy_div child1; + struct clk_dummy_gate child2; + struct clk_test_rate_change_sibling_clk_ctx clk_ctx; +}; + +static struct clk_test_rate_change_sibling_clk_ctx * +clk_rate_change_sibling_div_gate_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_div_gate_sibling_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + test->priv =3D ctx; + + ctx->parent.hw.init =3D CLK_HW_INIT_NO_PARENT("parent", &clk_dummy_rate_o= ps, 0); + ctx->parent.rate =3D DUMMY_CLOCK_RATE_24_MHZ; + ret =3D clk_hw_register_kunit(test, NULL, &ctx->parent.hw); + if (ret) + return ERR_PTR(ret); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", &ctx->parent.hw, + &clk_dummy_div_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ERR_PTR(ret); + + ctx->child2.hw.init =3D CLK_HW_INIT_HW("child2", &ctx->parent.hw, + &clk_dummy_gate_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child2.hw); + if (ret) + return ERR_PTR(ret); + + ctx->clk_ctx.parent_clk =3D clk_hw_get_clk(&ctx->parent.hw, NULL); + ctx->clk_ctx.child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->clk_ctx.child2_clk =3D clk_hw_get_clk(&ctx->child2.hw, NULL); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->clk_ctx.parent_clk), + DUMMY_CLOCK_RATE_24_MHZ); + + return &ctx->clk_ctx; +} + +struct clk_test_rate_change_sibling_test_case { + const char *desc; + struct clk_test_rate_change_sibling_clk_ctx *(*init)(struct kunit *test); +}; + +static struct clk_test_rate_change_sibling_test_case clk_test_rate_change_= sibling_test_cases[] =3D { + { + .desc =3D "div_gate", + .init =3D clk_rate_change_sibling_div_gate_test_init, + }, +}; + +KUNIT_ARRAY_PARAM_DESC(clk_test_rate_change_sibling_test_case, + clk_test_rate_change_sibling_test_cases, desc); + +/* + * Test that, for a parent with two children and one requests a rate chang= e that + * requires a change to the parent rate, the sibling rates are not affecte= d. + */ +static void clk_test_rate_change_sibling_1(struct kunit *test) +{ + struct clk_test_rate_change_sibling_test_case *testcase =3D + (struct clk_test_rate_change_sibling_test_case *) test->param_value; + struct clk_test_rate_change_sibling_clk_ctx *ctx; + int ret; + + kunit_skip(test, "This needs to be fixed in the core."); + + ctx =3D testcase->init(test); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); + + ret =3D clk_set_rate(ctx->child1_clk, DUMMY_CLOCK_RATE_48_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_GE(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_48_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), DUMMY_CLOCK_RATE_48_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); + + clk_test_rate_change_sibling_clk_ctx_put(ctx); +} + +/* + * Test that, for a parent with two children where one requests an exclusi= ve + * rate and the other requests a rate change that requires a change to the + * parent rate, the sibling rates are not affected. + */ +static void clk_test_rate_change_sibling_2(struct kunit *test) +{ + struct clk_test_rate_change_sibling_test_case *testcase =3D + (struct clk_test_rate_change_sibling_test_case *)(test->param_value); + struct clk_test_rate_change_sibling_clk_ctx *ctx; + int ret; + + ctx =3D testcase->init(test); + KUNIT_ASSERT_NOT_ERR_OR_NULL(test, ctx); + + ret =3D clk_rate_exclusive_get(ctx->child2_clk); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); + + ret =3D clk_set_rate(ctx->child1_clk, DUMMY_CLOCK_RATE_48_MHZ); + KUNIT_ASSERT_EQ(test, ret, 0); + + KUNIT_EXPECT_GE(test, clk_get_rate(ctx->parent_clk), DUMMY_CLOCK_RATE_24_= MHZ); + /* child1 is rounded to the closest supported rate */ + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child1_clk), DUMMY_CLOCK_RATE_24_= MHZ); + KUNIT_EXPECT_EQ(test, clk_get_rate(ctx->child2_clk), DUMMY_CLOCK_RATE_24_= MHZ); + + clk_rate_exclusive_put(ctx->child2_clk); + + clk_test_rate_change_sibling_clk_ctx_put(ctx); +} + + +static struct kunit_case clk_rate_change_sibling_cases[] =3D { + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_1, + clk_test_rate_change_sibling_test_case_gen_params), + KUNIT_CASE_PARAM(clk_test_rate_change_sibling_2, + clk_test_rate_change_sibling_test_case_gen_params), + {} +}; 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Ensure that changing the= rate + * of one child does affect the rate of the other child. + */ +static struct kunit_suite clk_rate_change_sibling_test_suite =3D { + .name =3D "clk-rate-change-sibling", + .test_cases =3D clk_rate_change_sibling_cases, +}; + static int clk_orphan_transparent_multiple_parent_mux_test_init(struct kunit *test) { @@ -3618,6 +3773,7 @@ kunit_test_suites( &clk_test_suite, &clk_multiple_parents_mux_test_suite, &clk_rate_change_sibling_div_div_test_suite, + &clk_rate_change_sibling_test_suite, &clk_mux_no_reparent_test_suite, &clk_mux_notifier_test_suite, &clk_orphan_transparent_multiple_parent_mux_test_suite, --=20 2.49.0 From nobody Tue Dec 16 14:49:53 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.133.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FE2B224AE9 for ; Wed, 28 May 2025 23:17:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:26 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:54 -0400 Subject: [PATCH v2 08/10] clk: test: introduce helper to create a mock mux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-8-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=7421; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=O2dam44l6BAOHzopP51WKdXl85jM4U2hjqdRMXfjkcI=; b=CUG6QvAnQNxhMFGNanvklQpYfOpElHasZJtBONqjWEZxiH/axBCu3zQ47b8GAP8rkCpFIeT54 H9mOGaN9E8HBy4OUE49fmxWDg0B4wtYrxqJFgHF+pcc8Z0VbjlYXzVe X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a helper to create a mock mux to reduce code duplication. This also changes it so that the relevant clk_hws are registered with the kunit framework. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 141 ++++++++++++++++++---------------------------= ---- 1 file changed, 52 insertions(+), 89 deletions(-) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 1440eb3c41def8c549f92c0e95b2a472f3bdb4a7..147935975969f8da4a9365c0fac= 6ffe37e310933 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -538,45 +538,64 @@ static struct kunit_suite clk_uncached_test_suite =3D= { .test_cases =3D clk_uncached_test_cases, }; =20 -static int -clk_multiple_parents_mux_test_init(struct kunit *test) -{ - struct clk_multiple_parent_ctx *ctx; - const char *parents[2] =3D { "parent-0", "parent-1"}; +static int clk_init_multiple_parent_ctx(struct kunit *test, + struct clk_multiple_parent_ctx *ctx, + const char *parent0_name, + unsigned long parent0_rate, + const char *parent1_name, + unsigned long parent1_rate, + const char *mux_name, int mux_flags, + const struct clk_ops *mux_ops) +{ + const struct clk_hw *parents[2]; int ret; =20 - ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); - if (!ctx) - return -ENOMEM; - test->priv =3D ctx; - - ctx->parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", + ctx->parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT(parent0_name, &clk_dummy_rate_ops, 0); - ctx->parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; + ctx->parents_ctx[0].rate =3D parent0_rate; ret =3D clk_hw_register_kunit(test, NULL, &ctx->parents_ctx[0].hw); if (ret) return ret; =20 - ctx->parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", + ctx->parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT(parent1_name, &clk_dummy_rate_ops, 0); - ctx->parents_ctx[1].rate =3D DUMMY_CLOCK_RATE_2; + ctx->parents_ctx[1].rate =3D parent1_rate; ret =3D clk_hw_register_kunit(test, NULL, &ctx->parents_ctx[1].hw); if (ret) return ret; =20 - ctx->current_parent =3D 0; - ctx->hw.init =3D CLK_HW_INIT_PARENTS("test-mux", parents, - &clk_multiple_parents_mux_ops, - CLK_SET_RATE_PARENT); + parents[0] =3D &ctx->parents_ctx[0].hw; + parents[1] =3D &ctx->parents_ctx[1].hw; + ctx->hw.init =3D CLK_HW_INIT_PARENTS_HW(mux_name, parents, + mux_ops, mux_flags); ret =3D clk_hw_register_kunit(test, NULL, &ctx->hw); if (ret) return ret; =20 + ctx->current_parent =3D 0; + return 0; } =20 +static int +clk_multiple_parents_mux_test_init(struct kunit *test) +{ + struct clk_multiple_parent_ctx *ctx; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return -ENOMEM; + test->priv =3D ctx; + + return clk_init_multiple_parent_ctx(test, ctx, + "parent-0", DUMMY_CLOCK_RATE_1, + "parent-1", DUMMY_CLOCK_RATE_2, + "test-mux", CLK_SET_RATE_PARENT, + &clk_multiple_parents_mux_ops); +} + /* * Test that for a clock with multiple parents, clk_get_parent() * actually returns the current one. @@ -2536,7 +2555,6 @@ static int clk_leaf_mux_set_rate_parent_test_init(struct kunit *test) { struct clk_leaf_mux_ctx *ctx; - const char *top_parents[2] =3D { "parent-0", "parent-1" }; int ret; =20 ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); @@ -2544,27 +2562,11 @@ clk_leaf_mux_set_rate_parent_test_init(struct kunit= *test) return -ENOMEM; test->priv =3D ctx; =20 - ctx->mux_ctx.parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[0].hw); - if (ret) - return ret; - - ctx->mux_ctx.parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[1].rate =3D DUMMY_CLOCK_RATE_2; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[1].hw); - if (ret) - return ret; - - ctx->mux_ctx.current_parent =3D 0; - ctx->mux_ctx.hw.init =3D CLK_HW_INIT_PARENTS("test-mux", top_parents, - &clk_multiple_parents_mux_ops, - 0); - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.hw); + ret =3D clk_init_multiple_parent_ctx(test, &ctx->mux_ctx, + "parent-0", DUMMY_CLOCK_RATE_1, + "parent-1", DUMMY_CLOCK_RATE_2, + "test-mux", 0, + &clk_multiple_parents_mux_ops); if (ret) return ret; =20 @@ -2752,7 +2754,6 @@ static int clk_mux_notifier_callback(struct notifier_= block *nb, static int clk_mux_notifier_test_init(struct kunit *test) { struct clk_mux_notifier_ctx *ctx; - const char *top_parents[2] =3D { "parent-0", "parent-1" }; int ret; =20 ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); @@ -2763,27 +2764,11 @@ static int clk_mux_notifier_test_init(struct kunit = *test) init_waitqueue_head(&ctx->pre_rate_change.wq); init_waitqueue_head(&ctx->post_rate_change.wq); =20 - ctx->mux_ctx.parents_ctx[0].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-0", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[0].rate =3D DUMMY_CLOCK_RATE_1; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[0].hw); - if (ret) - return ret; - - ctx->mux_ctx.parents_ctx[1].hw.init =3D CLK_HW_INIT_NO_PARENT("parent-1", - &clk_dummy_rate_ops, - 0); - ctx->mux_ctx.parents_ctx[1].rate =3D DUMMY_CLOCK_RATE_2; - ret =3D clk_hw_register(NULL, &ctx->mux_ctx.parents_ctx[1].hw); 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:29 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:55 -0400 Subject: [PATCH v2 09/10] clk: test: introduce test variation for sibling rate changes on a mux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-9-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=2566; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=sQ+5ETviPsufC2rC/jxYhJ16ZkKYEBNOFVNqjLFU4VM=; b=ChBC/ilvuXXJXRyiziNjnFOkucSkSvvLHNZzLHSQQdueZGY9aWrJAP9J9NkBCRVXMyUsjqlxk THzafP5HRIGAFYJKQKPa6Caxb9n9anfpeIxZbJB4un1a6UdrxCEo9d1 X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test variation that creates a parent with two children: a divider and a mux. Ensure that changing the rate of the divider does not affect the rate of the mux. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index 147935975969f8da4a9365c0fac6ffe37e310933..b5cf0de16abd1e098368a67626f= ff9044f7a1a6a 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -904,6 +904,48 @@ clk_rate_change_sibling_div_gate_test_init(struct kuni= t *test) return &ctx->clk_ctx; } =20 +struct clk_rate_change_sibling_div_mux_sibling_context { + struct clk_dummy_div child1; + struct clk_multiple_parent_ctx child2_mux; + struct clk_test_rate_change_sibling_clk_ctx clk_ctx; +}; + +static struct clk_test_rate_change_sibling_clk_ctx * +clk_rate_change_sibling_div_mux_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_div_mux_sibling_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + test->priv =3D ctx; + + ret =3D clk_init_multiple_parent_ctx(test, &ctx->child2_mux, + "parent0", DUMMY_CLOCK_RATE_24_MHZ, + "parent1", DUMMY_CLOCK_RATE_48_MHZ, + "child2", CLK_SET_RATE_NO_REPARENT, + &clk_multiple_parents_mux_ops); + if (ret) + return ERR_PTR(ret); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", + &ctx->child2_mux.parents_ctx[0].hw, + &clk_dummy_div_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ERR_PTR(ret); + + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->clk_ctx.parent_clk =3D clk_hw_get_clk(&ctx->child2_mux.parents_ctx[0= ].hw, NULL); + ctx->clk_ctx.child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->clk_ctx.child2_clk =3D clk_hw_get_clk(&ctx->child2_mux.hw, NULL); + + return &ctx->clk_ctx; +} + struct clk_test_rate_change_sibling_test_case { const char *desc; struct clk_test_rate_change_sibling_clk_ctx *(*init)(struct kunit *test); @@ -914,6 +956,10 @@ static struct clk_test_rate_change_sibling_test_case c= lk_test_rate_change_siblin .desc =3D "div_gate", .init =3D clk_rate_change_sibling_div_gate_test_init, }, + { + .desc =3D "div_mux", + .init =3D clk_rate_change_sibling_div_mux_test_init, + }, }; =20 KUNIT_ARRAY_PARAM_DESC(clk_test_rate_change_sibling_test_case, --=20 2.49.0 From nobody Tue Dec 16 14:49:53 2025 Received: from us-smtp-delivery-124.mimecast.com (us-smtp-delivery-124.mimecast.com [170.10.129.124]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 507F1225A29 for ; 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[73.183.52.120]) by smtp.gmail.com with ESMTPSA id af79cd13be357-7d09a0f984fsm13437985a.43.2025.05.28.16.17.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 28 May 2025 16:17:32 -0700 (PDT) From: Brian Masney Date: Wed, 28 May 2025 19:16:56 -0400 Subject: [PATCH v2 10/10] clk: test: introduce test variation for sibling rate changes on a gate/mux Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250528-clk-wip-v2-v2-10-0d2c2f220442@redhat.com> References: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> In-Reply-To: <20250528-clk-wip-v2-v2-0-0d2c2f220442@redhat.com> To: Stephen Boyd , Maxime Ripard Cc: linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, Arnd Bergmann , Thomas Gleixner , Michael Turquette , Alberto Ruiz , Brian Masney X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1748474226; l=2565; i=bmasney@redhat.com; s=20250528; h=from:subject:message-id; bh=2UyuBFVBF7/NqDq+ovnhAtBjPjcIVQGpsNux7ISwlE4=; b=5fozoClZaz3cF6k4P4348t7plBzvForrhLSMk0Pp0guJb4WPQJlBDPhK0JHbk/o6+gBWT/w/0 ej3nCkgUHHFCW2CQldcwiDaZlKZM5RiBeuoM38YlJDqfNV3RHJuEBIh X-Developer-Key: i=bmasney@redhat.com; a=ed25519; pk=x20f2BQYftANnik+wvlm4HqLqAlNs/npfVcbhHPOK2U= Introduce a test variation that creates a parent with two children: a gate and a mux. Ensure that changing the rate of the gate does not affect the rate of the mux. Signed-off-by: Brian Masney --- drivers/clk/clk_test.c | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/drivers/clk/clk_test.c b/drivers/clk/clk_test.c index b5cf0de16abd1e098368a67626fff9044f7a1a6a..c5b856e224f057b011b095d998c= a3016b6a041a8 100644 --- a/drivers/clk/clk_test.c +++ b/drivers/clk/clk_test.c @@ -946,6 +946,48 @@ clk_rate_change_sibling_div_mux_test_init(struct kunit= *test) return &ctx->clk_ctx; } =20 +struct clk_rate_change_sibling_gate_mux_sibling_context { + struct clk_dummy_gate child1; + struct clk_multiple_parent_ctx child2_mux; + struct clk_test_rate_change_sibling_clk_ctx clk_ctx; +}; + +static struct clk_test_rate_change_sibling_clk_ctx * +clk_rate_change_sibling_gate_mux_test_init(struct kunit *test) +{ + struct clk_rate_change_sibling_gate_mux_sibling_context *ctx; + int ret; + + ctx =3D kunit_kzalloc(test, sizeof(*ctx), GFP_KERNEL); + if (!ctx) + return ERR_PTR(-ENOMEM); + test->priv =3D ctx; + + ret =3D clk_init_multiple_parent_ctx(test, &ctx->child2_mux, + "parent0", DUMMY_CLOCK_RATE_24_MHZ, + "parent1", DUMMY_CLOCK_RATE_48_MHZ, + "child2", CLK_SET_RATE_NO_REPARENT, + &clk_multiple_parents_mux_ops); + if (ret) + return ERR_PTR(ret); + + ctx->child1.hw.init =3D CLK_HW_INIT_HW("child1", + &ctx->child2_mux.parents_ctx[0].hw, + &clk_dummy_gate_ops, + CLK_SET_RATE_PARENT); + ret =3D clk_hw_register_kunit(test, NULL, &ctx->child1.hw); + if (ret) + return ERR_PTR(ret); + + KUNIT_ASSERT_EQ(test, ret, 0); + + ctx->clk_ctx.parent_clk =3D clk_hw_get_clk(&ctx->child2_mux.parents_ctx[0= ].hw, NULL); + ctx->clk_ctx.child1_clk =3D clk_hw_get_clk(&ctx->child1.hw, NULL); + ctx->clk_ctx.child2_clk =3D clk_hw_get_clk(&ctx->child2_mux.hw, NULL); + + return &ctx->clk_ctx; +} + struct clk_test_rate_change_sibling_test_case { const char *desc; struct clk_test_rate_change_sibling_clk_ctx *(*init)(struct kunit *test); @@ -960,6 +1002,10 @@ static struct clk_test_rate_change_sibling_test_case = clk_test_rate_change_siblin .desc =3D "div_mux", .init =3D clk_rate_change_sibling_div_mux_test_init, }, + { + .desc =3D "gate_mux", + .init =3D clk_rate_change_sibling_gate_mux_test_init, + }, }; =20 KUNIT_ARRAY_PARAM_DESC(clk_test_rate_change_sibling_test_case, --=20 2.49.0