From nobody Tue Dec 16 10:34:24 2025 Received: from mail.actia.se (mail.actia.se [212.181.117.226]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B7E26202996; Tue, 27 May 2025 07:16:09 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=212.181.117.226 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748330171; cv=none; b=vBdGEiWZMBYBNmoXlHyAD5cnlfrxC54OIk2DhII4ioCJXOwuur7TgHsOW2iuMU1jNi3vNRjyqTSH0Iczr80zyRIKHb+PNKgzjwgwaNV8PqVcdWYd3L+hU2eF1FZFjv1VbWCJ7zRyzOgNL2HcKoFkowKyLaNev7HnroL8Hyw2Qzs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748330171; c=relaxed/simple; bh=Y08a/dTVSVM+/XsHWHTfPzKKXmUsqI91RqkkVefuBdk=; h=From:To:CC:Subject:Date:Message-ID:References:In-Reply-To: Content-Type:MIME-Version; b=gjhDbwtjYSWJMkIGO888egVoa6mvI5LubRKMeKBsN3KJH1/OsM+OrWq84vbm53Oadv7PtdevvtEM2qX8/9ERSdg0Y56xLD0xBlZ0uGGoGn2KCAYLqYv2GWcQ+FppBWYGGUHoVzxaE/q6V3nfAJ9T+uU0G3UGZeDHy8gtJxDIYng= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se; spf=pass smtp.mailfrom=actia.se; arc=none smtp.client-ip=212.181.117.226 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=actia.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=actia.se Received: from S036ANL.actianordic.se (10.12.31.117) by S035ANL.actianordic.se (10.12.31.116) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Tue, 27 May 2025 09:16:03 +0200 Received: from S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69]) by S036ANL.actianordic.se ([fe80::e13e:1feb:4ea6:ec69%3]) with mapi id 15.01.2507.039; Tue, 27 May 2025 09:16:03 +0200 From: John Ernberg To: =?utf-8?B?SG9yaWEgR2VhbnTEgw==?= , Pankaj Gupta , Gaurav Jain , Herbert Xu , "David S . Miller" , "Rob Herring" , Krzysztof Kozlowski , "Conor Dooley" , Shawn Guo , Sascha Hauer CC: Frank Li , Pengutronix Kernel Team , Fabio Estevam , Thomas Richard , "linux-crypto@vger.kernel.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "imx@lists.linux.dev" , "linux-arm-kernel@lists.infradead.org" , John Ernberg Subject: [PATCH v2 4/4] arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support Thread-Topic: [PATCH v2 4/4] arm64: dts: freescale: imx8qxp/imx8qm: Add CAAM support Thread-Index: AQHbztc0T1fA+eNp8E2a5tgCivNrBA== Date: Tue, 27 May 2025 07:16:03 +0000 Message-ID: <20250527071552.1424997-5-john.ernberg@actia.se> References: <20250527071552.1424997-1-john.ernberg@actia.se> In-Reply-To: <20250527071552.1424997-1-john.ernberg@actia.se> Accept-Language: en-US, sv-SE Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-mailer: git-send-email 2.49.0 x-esetresult: clean, is OK x-esetid: 37303A2956B1445360726A Content-Type: text/plain; charset="utf-8" Content-ID: <26D9C3FA2C04A740B422139B30F6361A@actia.se> Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 From: Horia Geant=C4=83 The iMX8QXP and iMX8QM have a CAAM (Cryptographic Acceleration and Assurance Module) like many other iMXs. Add the definitions for it. Job Rings 0 and 1 are bound to the SECO (Security Controller) ARM core and are not exposed outside it. There's no point to define them in the bindings as they cannot be used outside the SECO. Signed-off-by: Horia Geant=C4=83 [jernberg: Commit message, fixed dtbs_check warnings, trimmed memory ranges] Signed-off-by: John Ernberg --- Imported from NXP tree, trimmed down and fixed the dtbs_check warnings. Constrained the ranges to the needed ones. Changed the commit message. Original here: https://github.com/nxp-imx/linux-imx/commit/699e54b386cb9b53= def401798d0a4e646105583d --- v2: - Use new compatibles introduced in 3/4 (Frank Li) --- .../boot/dts/freescale/imx8-ss-security.dtsi | 38 +++++++++++++++++++ arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 + arch/arm64/boot/dts/freescale/imx8qxp.dtsi | 1 + 3 files changed, 40 insertions(+) create mode 100644 arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi diff --git a/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi b/arch/arm= 64/boot/dts/freescale/imx8-ss-security.dtsi new file mode 100644 index 000000000000..9ecabb2d03e9 --- /dev/null +++ b/arch/arm64/boot/dts/freescale/imx8-ss-security.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2019 NXP + */ + +#include + +security_subsys: bus@31400000 { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x31400000 0x0 0x31400000 0x90000>; + + crypto: crypto@31400000 { + compatible =3D "fsl,imx8qm-caam", "fsl,sec-v4.0"; + reg =3D <0x31400000 0x90000>; + interrupts =3D ; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0 0x31400000 0x90000>; + fsl,sec-era =3D <9>; + power-domains =3D <&pd IMX_SC_R_CAAM_JR2>; + + sec_jr2: jr@30000 { + compatible =3D "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring"; + reg =3D <0x30000 0x10000>; + interrupts =3D ; + power-domains =3D <&pd IMX_SC_R_CAAM_JR2>; + }; + + sec_jr3: jr@40000 { + compatible =3D "fsl,imx8qm-job-ring", "fsl,sec-v4.0-job-ring"; + reg =3D <0x40000 0x10000>; + interrupts =3D ; + power-domains =3D <&pd IMX_SC_R_CAAM_JR3>; + }; + }; +}; diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dt= s/freescale/imx8qm.dtsi index 6fa31bc9ece8..6df018643f20 100644 --- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi @@ -612,6 +612,7 @@ vpu_dsp: dsp@556e8000 { }; =20 /* sorted in register address */ + #include "imx8-ss-security.dtsi" #include "imx8-ss-cm41.dtsi" #include "imx8-ss-audio.dtsi" #include "imx8-ss-vpu.dtsi" diff --git a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi b/arch/arm64/boot/d= ts/freescale/imx8qxp.dtsi index 05138326f0a5..e140155d65c6 100644 --- a/arch/arm64/boot/dts/freescale/imx8qxp.dtsi +++ b/arch/arm64/boot/dts/freescale/imx8qxp.dtsi @@ -321,6 +321,7 @@ map0 { /* sorted in register address */ #include "imx8-ss-img.dtsi" #include "imx8-ss-vpu.dtsi" + #include "imx8-ss-security.dtsi" #include "imx8-ss-cm40.dtsi" #include "imx8-ss-gpu0.dtsi" #include "imx8-ss-adma.dtsi" --=20 2.49.0