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Tue, 27 May 2025 14:56:50 -0700 (PDT) Received: from localhost ([2a00:79e0:9d:4:8e02:75c1:e352:cd00]) by smtp.gmail.com with UTF8SMTPSA id 5b1f17b1804b1-450064a1ac4sm1241745e9.12.2025.05.27.14.56.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 May 2025 14:56:50 -0700 (PDT) From: Jann Horn Date: Tue, 27 May 2025 23:56:42 +0200 Subject: [PATCH] x86/mm: Limit INVLPGB to VA in invlpgb_flush_addr_nosync() Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250527-x86-overbroad-invlpgb-v1-1-64ca98aa2a3a@google.com> X-B4-Tracking: v=1; b=H4sIABk1NmgC/x3MTQqAIBBA4avErBsw7f8q0SJrqoHQGEGE6O5Jy 2/x3gOBhCnAWDwgFDmwdxlVWcB6Lu4g5C0btNKNanSHqW/RRxIrftmQXbzuw6Kp90GZdSBtDeT 2Fto5/d9pft8Po7i4j2cAAAA= X-Change-ID: 20250527-x86-overbroad-invlpgb-34f903c9e2b3 To: Rik van Riel , Borislav Petkov , Ingo Molnar , Dave Hansen , Andy Lutomirski , Peter Zijlstra Cc: linux-kernel@vger.kernel.org, Jann Horn X-Mailer: b4 0.15-dev X-Developer-Signature: v=1; a=ed25519-sha256; t=1748383006; l=1544; i=jannh@google.com; s=20240730; h=from:subject:message-id; bh=H6RdSfdrrWnEqfuvZ74jCpn12+bkjOdAgwdgoViDX0c=; b=LlUTfSF9TgfmJn97RSUv3H9eY1zpnykhquCEBz3jgZngzgmAQSk49U/P0fkCjicp83AA7aVwn B+TwVhAZt7wDhoAmzDQlgDHXF9Iut3tRFQ6DlYM2mRU6bYj0mgOSl0K X-Developer-Key: i=jannh@google.com; a=ed25519; pk=AljNtGOzXeF6khBXDJVVvwSEkVDGnnZZYqfWhP1V+C8= The intent of invlpgb_flush_addr_nosync() is to flush a specific virtual address range, but INVLPGB_FLAG_VA is not set. If I understand AMD's documentation correctly, this means this will flush the entire TLB (except entries for guest ASIDs). That's safe, but seems like an unintentionally broad flush. Fix it by setting INVLPGB_FLAG_VA. Fixes: b7aa05cbdc52 ("x86/mm: Add INVLPGB support code") Signed-off-by: Jann Horn Reviewed-by: Rik van Riel --- I am not entirely sure about this; Rik, can you confirm if this was an oversight, or if there's actually a reason for not passing INVLPGB_FLAG_VA here? I feel a bit uncomfortable touching TLB flushing and narrowing a flush there... --- arch/x86/include/asm/tlb.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/x86/include/asm/tlb.h b/arch/x86/include/asm/tlb.h index 866ea78ba156..e257201a141a 100644 --- a/arch/x86/include/asm/tlb.h +++ b/arch/x86/include/asm/tlb.h @@ -153,7 +153,8 @@ static inline void invlpgb_flush_all(void) /* Flush addr, including globals, for all PCIDs. */ static inline void invlpgb_flush_addr_nosync(unsigned long addr, u16 nr) { - __invlpgb(0, 0, addr, nr, PTE_STRIDE, INVLPGB_FLAG_INCLUDE_GLOBAL); + __invlpgb(0, 0, addr, nr, PTE_STRIDE, + INVLPGB_FLAG_VA | INVLPGB_FLAG_INCLUDE_GLOBAL); } =20 /* Flush all mappings for all PCIDs except globals. */ --- base-commit: b1456f6dc167f7f101746e495bede2bac3d0e19f change-id: 20250527-x86-overbroad-invlpgb-34f903c9e2b3 --=20 Jann Horn